Hybrid DC-DC converter

This application claims the benefit of U.S. Provisional Application No. 63/151,015, filed on Feb. 18, 2021, which is incorporated herein by reference in its entirety.

1. Field of the Invention

The present invention relates generally to electrical circuits, and more particularly but not exclusively to DC-DC converters.

2. Description of the Background Art

A DC-DC converter converts a DC input voltage to a regulated DC output voltage, which is higher than the input voltage in the case of a boost converter or lower than the input voltage in the case of a buck converter. DC-DC converters that allow for buck or boost operation are referred to as buck-boost converters. Yet another type of DC-DC converter generates a regulated output voltage at the same level as the input voltage.

Various circuit topologies have been developed to implement DC-DC converters. Examples of such circuit topologies include hard-switching full bridge, phase shift soft switching full bridge, and soft switching full bridge with a series resonant circuit. A DC-DC converter with a combination of circuit structures, such as a soft switching full bridge with a series resonant circuit, is referred to as a hybrid DC-DC converter.

Problems with currently-available DC-DC converters include low-efficiency, low power density, and relatively high manufacturing cost.

In one embodiment, a hybrid DC-DC converter includes a converter circuit, a first bridge circuit with a bridge path that includes a first winding of a transformer, and a second bridge circuit with a bridge path that includes a second winding of the transformer. Current through the bridge path of the second bridge circuit flows through the converter circuit in one direction and bypasses the converter circuit in the other direction. The converter circuit can be configured to operate in buck, boost, or buck-boost mode.

These and other features of the present invention will be readily apparent to persons of ordinary skill in the art upon reading the entirety of this disclosure, which includes the accompanying drawings and claims.

FIG. 1 shows a schematic diagram of a hybrid DC-DC converter in accordance with an embodiment of the present invention.

FIG. 2 shows a schematic diagram of a hybrid buck DC-DC converter in accordance with an embodiment of the present invention.

FIG. 3 shows a schematic diagram of a hybrid boost DC-DC converter in accordance with an embodiment of the present invention.

The use of the same reference label in different drawings indicates the same or like components.

In the present disclosure, numerous specific details are provided, such as examples of circuits, components, and methods, to provide a thorough understanding of embodiments of the invention. Persons of ordinary skill in the art will recognize, however, that the invention can be practiced without one or more of the specific details. In other instances, well-known details are not shown or described to avoid obscuring aspects of the invention.

FIG. 1 shows a schematic diagram of a hybrid DC-DC converter 100 in accordance with an embodiment of the present invention. As will be more apparent below, the DC-DC converter 100 operates as a buck-boost converter.

In the example of FIG. 1 , the DC-DC converter 100 includes a full bridge circuit 110 , a full bridge circuit 120 , and a converter circuit 130 . The full bridge circuit 110 is on the primary side of a transformer T 1 , whereas the full bridge circuit 120 and the converter circuit 130 are on the secondary side of the transformer T 1 . The transformer T 1 has a primary winding Np and a secondary winding Ns. The inductor Lm represents the magnetizing inductance on the primary winding Np of the transformer T 1 .

The full bridge circuit 110 comprises transistors Q 1 , Q 2 , Q 3 , and Q 4 and a resonant LLC circuit that forms a bridge path between a bridge node 112 and a bridge node 113 . The LLC circuit comprises an inductor Lr, the primary winding Np of the transformer T 1 , and a capacitor Cr 1 . The full bridge circuit 110 receives an input voltage Vin across a capacitor Cin. Current flows in one direction through the LLC circuit when the transistors Q 1 and Q 4 are ON (i.e., closed) while the transistors Q 2 and Q 3 are OFF (i.e., open) in a first half cycle, and in the other direction through the LLC circuit when the transistors Q 1 and Q 4 are OFF while the transistors Q 2 and Q 3 are ON in a following half cycle. The transistors Q 1 -Q 4 are controlled such that an AC voltage develops on the primary winding Np.

The full bridge circuit 120 comprises transistors S 1 , S 2 , S 3 , and S 4 and an LC circuit that forms a bridge path between a bridge node 121 and a bridge node 122 . The LC circuit comprises a capacitor Cr 2 and the secondary winding Ns of the transformer T 1 . The AC voltage on the primary winding Np is reflected on the secondary winding Ns. Current flows in the LC circuit in one direction to the converter circuit 130 when the transistors S 1 and S 4 are OFF while the transistors S 2 and S 3 are ON, and in the other direction to bypass the converter circuit 130 when the transistors S 1 and S 4 are ON while the transistors S 2 and S 3 are OFF.

In the example of FIG. 1 , a drain of the transistor S 2 is connected to a source of the transistor S 1 at the node 121 and a drain of the transistor S 4 is connected to a source of the transistor S 3 at the node 122 . The sources of the transistors S 2 and S 4 are connected to a common node 125 . Note, however, that the transistors S 1 and S 3 are not directly connected together at a same node.

More particularly, a drain of the transistor S 1 is connected to an output node 124 where an output voltage Vout is developed, whereas a drain of the transistor S 3 is connected to an input node 123 of the converter circuit 130 . Accordingly, current through the LC circuit flows directly to the output voltage Vout (and bypasses the converter circuit 130 ) when the transistors S 1 and S 4 are ON while the transistors S 2 and S 3 are OFF. However, when the transistors S 1 and S 4 are OFF while the transistors S 2 and S 3 are ON, current through the LC circuit flows to the converter circuit 130 .

The transistors S 1 -S 4 are controlled to regulate a middle voltage Vmid across the nodes 123 and 125 to regulate the output voltage Vout across the nodes 124 and 125 . In the example of FIG. 1 , the middle voltage Vmid is developed across a middle capacitor Cmid and the output voltage Vout is developed across a capacitor Cout. A resistor RL represents a load connected to receive the output voltage Vout.

In the example of FIG. 1 , the converter circuit 130 is a buck-boost converter. The converter circuit 130 comprises transistors S 5 , S 6 , S 7 , and S 8 and a middle inductor Lmid between a node 126 and a node 127 . During buck mode operation, the transistor S 7 is always ON and the transistor S 8 is always OFF, while the transistors S 5 and S 6 are controlled to generate the regulated output voltage Vout. The output voltage Vout during buck mode operation is given by,

where D is the duty cycle of the transistor S 5 , Vin is the input voltage, Dbuck is the duty cycle of the converter circuit 130 in buck mode, and Ns/Np is the turns ratio of the transformer T 1 . Pulse width modulation (PWM) control may be applied on the transistors S 5 and S 6 to achieve buck regulation.

During boost mode operation, the transistor S 5 is always ON and the transistor S 6 is always OFF, while the transistors S 7 and S 8 are controlled to generate the regulated output voltage Vout. The output voltage Vout during boost mode operation is given by,

where Vin is the input voltage, Dboost is the duty cycle of the converter circuit 130 in boost mode, and Ns/Np is the turns ratio of the transformer T 1 . PWM control may be applied on the transistors S 7 and S 8 to achieve boost regulation.

The transistors Q 1 -Q 4 and S 1 -S 8 may comprise metal oxide semiconductor field effect transistors (MOSFETs), field effect transistors (FETs), bipolar transistors, and/or other switching components. The transistors Q 1 -Q 4 and S 1 -S 8 may be controlled by PWM or other control methodology to generate the regulated voltage Vout.

The DC-DC converter 100 incorporates a novel partial power transfer topology, wherein the converter circuit 130 only handles around 50% of the power generated by the DC-DC converter 100 . This is because the full bridge circuit 120 has provisions to bypass the converter circuit 130 . By regulating the middle voltage Vmid to regulate the output voltage Vout, the LLC circuit on the primary side still operates as a non-regulated converter, which allows for improved LLC efficiency.

FIG. 2 shows a schematic diagram of a hybrid DC-DC converter 200 in accordance with an embodiment of the present invention. The DC-DC converter 200 is an embodiment of the DC-DC converter 100 where the converter circuit 130 (now relabeled as 130 A) is configured as a buck converter. The DC-DC converters 100 and 200 are otherwise the same. That is, the DC-DC converter 200 is the same as the DC-DC converter 100 except that the transistor S 7 has been replaced with a short to directly connect an end of the inductor Lmid to the node 124 (instead of going through the transistor S 7 ) and the transistor S 8 has been completely removed. The DC-DC converter 200 thus operates only as a buck converter.

FIG. 3 shows a schematic diagram of a hybrid DC-DC converter 300 in accordance with an embodiment of the present invention. The DC-DC converter 300 is an embodiment of the DC-DC converter 100 where the converter circuit 130 (now relabeled as 130 B) is configured as a boost converter. The DC-DC converters 100 and 300 are otherwise the same. That is, the DC-DC converter 300 is the same as the DC-DC converter 100 except that the transistor S 5 has been replaced with a short to directly connect an end of the inductor Lmid to the node 123 (instead of going through the transistor S 5 ) and the transistor S 6 has been completely removed. The DC-DC converter 300 thus operates only as a boost converter.

A high-efficiency hybrid DC-DC converter has been disclosed. While specific embodiments of the present invention have been provided, it is to be understood that these embodiments are for illustration purposes and not limiting. Many additional embodiments will be apparent to persons of ordinary skill in the art reading this disclosure.