Signalling coding and modulation method and demodulation and decoding method and device

This application is a continuation application of U.S. patent application Ser. No. 16/748,739 filed Jan. 21, 2020, which is a continuation application of U.S. patent application Ser. No. 15/558,184 filed Sep. 13, 2017 and issued Mar. 17, 2020 with U.S. Pat. No. 10,594,435, which is a national phase entry under 35 USC § 371 of International Application PCT/CN2016/076129, filed Mar. 11, 2016, which claims priority to and benefits of Chinese Patent Applications Serial No. 201510111992.X filed with the State Intellectual Property Office of P. R. China on Mar. 13, 2015, and Chinese Patent Applications Serial No. 201510125240.9 filed with the State Intellectual Property Office of P. R. China on Mar. 20, 2015, the entire contents of which are incorporated herein by reference.

The present invention relates to the technical field of digital televisions, and in particular to a signalling coding and modulation method and a demodulation and decoding method and device.

In the existing broadcast communication standards, such as a DVB-T2 system, every physical frame contains signalling and data, wherein the signalling indicates information such as coding and modulation, an interleaving mode, etc. of each service contained in the data. A receiving threshold of the signalling must be lower than a receiving threshold of all the services contained in the data in the physical frame. Therefore, coding and modulation of the signalling should provide stronger protection than the data, and at the same time should also provide a spectrum frequency as high as possible. In addition, the length of the signalling is variable with regard to each physical frame, and therefore coding and modulation of the signalling must also provide corresponding flexibility.

With the emergence of services of a large data volume such as ultra HD, etc., receiving thresholds of some services are also improved. The receiving thresholds of some services in a white noise channel have exceeded 25 dB or even 30 dB, then the existing technology is hard to provide a signalling coding and modulation and demodulation and decoding method which requires high efficiency and flexibility.

The objective of the present invention is to provide a corresponding high-efficient and flexible signalling coding and modulation method and a demodulation and decoding method and device for a service with a relatively high receiving threshold.

In order to solve the above problem, an embodiment of the present invention provides a signalling coding and modulation method, characterized in that the method comprises the steps of: extending signalling which has been subjected to first predetermined processing according to an extension pattern table to obtain an extended codeword, and conducting predetermined coding on the extended codeword to obtain a encoded codeword; conducting parity bit permutation on a parity bit portion in the encoded codeword and then splicing the permutated parity bits to the end of information bits in the encoded codeword, to obtain a permutated encoded codeword; according to the length of the signalling, punching the permutated encoded codeword according to a predetermined punching rule to obtain a punched encoded codeword; and conducting second predetermined processing on the punched encoded codeword to obtain a tuple sequence, which is used for mapping, and then mapping the tuple sequence, which is used for mapping, into a signalling symbol according to a predetermined mapping rule.

Optionally, the step of extending signalling which has been subjected to first predetermined processing according to an extension pattern table to obtain an extended codeword, and conducting predetermined coding on the extended codeword to obtain a encoded codeword comprises: scrambling the signalling, then conducting BCH coding on the scrambled signalling, extending an obtained BCH codeword to obtain an extended BCH codeword as the extended codeword, and conducting LDPC coding on the extended BCH codeword to obtain an LDPC codeword as the encoded codeword.

Optionally, the step of extending an obtained BCH codeword to obtain an extended BCH codeword comprises: the length of the BCH codeword being N BCH , the number of bits of an LDPC codeword contained in each bit group being Q, the extended codeword having a length of K LDPC being formed by sequentially splicing K LDPC /Q bit groups, and if the number of completely extended bit groups N Pad is greater than zero, then

N P ⁢ a ⁢ d = ⌊ K L ⁢ D ⁢ P ⁢ C - N B ⁢ C ⁢ H Q ⌋ > 0 ,

and then filling the π(0)th group to the π(N Pad −1)th group in the extended BCH codeword with zeros; if the number N Pad of the remaining extended bits is greater than zero, i.e. N Pad =K LDPC −N BCH −QN Pad >0, then filling the first K LDPC −N BCH −QN Pad bits of the π(N Pad )th group with zeros; and filling bits which have not been filled with zeros of the extended BCH codeword with the BCH codeword from front to back.

Optionally, the π(0)th group, π(1)th group, . . . ,

π ⁡ ( K LDPC Q - 1 )

th group in the extended BCH codeword are a predetermined extension pattern table.

Optionally, in the step of conducting predetermined coding on the extended codeword to obtain the encoded codeword, the predetermined coding uses LDPC coding determined by a predetermined LDPC code table.

Optionally, the method comprises conducting first parity bit permutation on the parity bit portion to obtain a first permutated parity bits; dividing the first permutated parity bits into several continuous bit groups, exchanging the positions of the bit groups so that the π p (k)th bit group before the exchange becomes the k th bit group after the exchange to obtain a second permutated parity bits; and sequentially splicing information bits and the second permutated parity bits to obtain the permutated encoded codeword.

Optionally, in the step of exchanging the positions of the bit groups so that the π p (k)th bit group before the exchange becomes the k th bit group after the exchange, it is determined according to a predetermined position permutation table.

Optionally, the predetermined punching rule comprises the steps of: calculating a first punching number by means of a first punching calculation formula according to the length of the signalling; calculating a second punching number by means of a second punching calculation formula according to the first punching number; and removing the second punching number of last bits of the permutated encoded codeword to obtain the punched encoded codeword.

Optionally, the first punching calculation formula uses:

the first punching number N punc_temp =└A* (K LDPC −K sig −L p )+B┘,

wherein the values of the first constant A and the second constant B enable signalling with different lengths to have close receiving thresholds after being subjected to coding and modulation, in the formula, K LDPC is the length of the extended BCH codeword, K sig is the signalling length, L p is a definition of the length of parity bits of the BCH codeword, and A and B are two constant parameters, respectively valued as:

Optionally, the second punching calculation formula uses:

the second punching number,

wherein N punc_temp is the first punching number calculated by the first punching calculation formula, N BCH is the length of the BCH codeword obtained after conducting BCH coding on scrambled signalling, K LDPC is the length of the extended BCH codeword, N LDPC is the length of the encoded codeword after being subjected to LDPC coding, and η mod is the number of orders of predetermined constellation mapping.

Optionally, the step of conducting second predetermined processing on the punched encoded codeword to obtain a tuple sequence comprises removing zeros added to the punched encoded codeword in an extension operation, conducting bit demultiplexing on an obtained encoded codeword with zeros removed to obtain a tuple sequence, and conducting a rotation operation on the tuple sequence to obtain a tuple sequence, which is used for mapping.

Optionally, the step of conducting bit demultiplexing on a encoded codeword with zeros removed to obtain a tuple sequence comprises: successively writing the encoded codeword with zeros removed into a matrix containing η mod columns and

⌈ N B ⁢ C ⁢ H + N L ⁢ D ⁢ P ⁢ C - K L ⁢ D ⁢ P ⁢ C - N punc_tem ⁢ p η m ⁢ o ⁢ d ⌉

rows according to columns; and sequentially reading out from the matrix by rows, and forming one tuple with η mod bits in each row to obtain the tuple sequence containing

⌈ N B ⁢ C ⁢ H + N L ⁢ D ⁢ P ⁢ C - K L ⁢ D ⁢ P ⁢ C - N punc_tem ⁢ p η m ⁢ o ⁢ d ⌉

tuples.

Optionally, the step of mapping the tuple sequence, which is used for mapping, into a signalling symbol according to the predetermined mapping rule comprises: mapping the tuple sequence, which is used for mapping, into the signalling symbol according to a mapping rule table containing predetermined mapping parameters.

In addition, an embodiment of the present invention further provides a signalling demodulation and decoding method, characterized in that the method comprises the steps of: demapping a receiving end signalling symbol corresponding to a sending end signalling symbol according to a predetermined mapping rule to obtain a log likelihood ratio; conducting corresponding inverse second predetermined processing, inverse punching and inverse permutation on the log likelihood ratio according to the steps of parity bit permutation, punching and second predetermined processing in the signalling coding and modulation method at a sending end to obtain a log likelihood ratio of a receiving end encoded codeword corresponding to a sending end encoded codeword; and conducting corresponding decoding, inverse extension and inverse first predetermined processing on the log likelihood ratio of the receiving end encoded codeword according to the steps of first predetermined processing, extension and predetermined coding in the signalling coding and modulation method at a sending end to obtain signalling.

In addition, an embodiment of the present invention further provides a signalling coding and modulation device, characterized in that the device comprises: an extension coding module: extending signalling which has been subjected to first predetermined processing according to an extension pattern table to obtain an extended codeword, and conducting predetermined coding on the extended codeword to obtain a encoded codeword; a permutation module: conducting parity bit permutation on parity bits in the encoded codeword and then splicing the permutated parity bits to the information bits in the encoded codeword, to obtain a permutated encoded codeword; a punching module: according to the length of the signalling, punching the permutated encoded codeword according to a predetermined punching rule to obtain a punched encoded codeword; and a processing and mapping module: conducting second predetermined processing on the punched encoded codeword to obtain a tuple sequence, which is used for mapping, and then mapping the obtained tuple sequence into a signalling symbol according to a predetermined mapping rule.

In addition, an embodiment of the present invention further provides a signalling demodulation and decoding device, characterized in that the device comprises: a demapping module: demapping a receiving end signalling symbol corresponding to a sending end signalling symbol according to a predetermined mapping rule to obtain a log likelihood ratio; a corresponding permutation deprocessing module: conducting corresponding inverse second predetermined processing, inverse punching and inverse permutation on the log likelihood ratio according to the steps of parity bit permutation, punching and second predetermined processing in the signalling coding and modulation device at a sending end to obtain a log likelihood ratio of a receiving end encoded codeword corresponding to a sending end encoded codeword; and a decoding module: conducting corresponding decoding, inverse extension and inverse first predetermined processing on the log likelihood ratio of the receiving end encoded codeword according to the steps of first predetermined processing, extension and predetermined coding in the signalling coding and modulation device at a sending end to obtain signalling. Compared with the prior art, the technical solution of the present invention provides the following advantages:

taking providing signalling for a high throughput data service with a relatively high receiving threshold as an objective, the present invention conducts a series of extension, coding, parity bit permutation, punching and mapping processing on signalling to obtain a signalling symbol, which provides a high-efficient and robust signalling coding and modulation method not only for signalling of a high throughput data service, but also particularly for signalling with a variable length.

FIG. 1 is a schematic diagram of the overall procedure of a signalling coding and modulation method in an embodiment of the present invention;

FIG. 2 is a schematic diagram of the specific procedure of a signalling coding and modulation method in an embodiment of the present invention; and

FIG. 3 is a schematic diagram of the procedure of a signalling demodulation and decoding method in an embodiment of the present invention.

The inventor has found that in the prior art, there is no signalling coding and modulation method designed for a service with a relatively high receiving threshold (e.g. greater than 25 dB) in a predetermined channel.

With regard to the above problem, the inventor provides, through research, a signalling coding and modulation method and a demapping and decoding method to conduct a series of extension, coding, parity bit permutation, punching and mapping processing on signalling, and further designs and provides specific technical parameters of extension, coding, parity bit permutation, punching, mapping, etc. to conduct a high-efficient and robust signalling coding and modulation method.

To make the foregoing objectives, features, and advantages of the present invention more evident and comprehensible, the following describes specific implementation manners of the present invention in details with reference to the accompanying drawings.

For example, in a DVB-T2 system, one primary mode is an LDPC code with a code rate of 2/3 in cooperation with 256QAM mapping, a receiving threshold of the mode has reached 17 dB to 18 dB, and with the continuous increase of system capacity, for example, a coding and modulation mode of an LDPC code with a code rate of 2/3 in cooperation with 1024QAM mapping or even in cooperation with 4096QAM mapping would also emerge, and at this time, the receiving threshold would reach 25 dB or even 30 dB. It can be seen that the receiving threshold of a data service is determined based on a coding and modulation mode of a system. The present invention does not limit the specific numerical value of the receiving threshold, which is above a predetermined high threshold value, of a data service. In the embodiments below, a data service with a receiving threshold being greater than 25 dB in a white noise channel is chosen for description.

FIG. 1 is a schematic diagram of the overall procedure of a signalling coding and modulation method in an embodiment of the present invention;

In the embodiment of the present invention, a signalling coding and modulation method at a transmitting end comprises the steps of:

step S 1 - 1 : extending signalling which has been subjected to first predetermined processing according to an extension pattern table to obtain an extended codeword, and conducting predetermined coding on the extended codeword to obtain a encoded codeword;

step S 1 - 2 : conducting parity bit permutation on the encoded codeword to obtain a permutated encoded codeword;

step S 1 - 3 : according to the length of the signalling, punching the permutated encoded codeword according to a predetermined punching rule to obtain a punched encoded codeword; and

step S 1 - 4 : conducting second predetermined processing on the punched encoded codeword to obtain a tuple sequence, which is used for mapping, and then mapping the obtained tuple sequence into a signalling symbol according to a predetermined mapping rule.

It can be seen from step S 1 - 1 to step S 1 - 4 above that the signalling coding and modulation method conducts a series of extension, coding, parity bit permutation, punching and mapping processing on signalling, and furthermore, as a preferred example, the following processing is complementarily conducted on the basis of step S 1 - 1 to step S 1 - 4 . That is, firstly scrambling is conducted on the signalling, and then BCH coding, extension, LDPC coding, parity bit permutation, punching, zero removing, bit demultiplexing, bit rotation and constellation mapping are successively conducted to obtain a signalling symbol. Specifically, FIG. 2 is a schematic diagram of the specific procedure of a signalling coding and modulation method in an embodiment of the present invention, as shown in FIG. 2 :

A signalling coding and modulation method comprises the steps of:

step S 1 - 1 *: scrambling signalling with a length being K sig bits to obtain scrambled signalling with a length being K sig bits;

step S 1 - 2 *: conducting BCH coding on the scrambled signalling, i.e. conducting calculation according to information bits to obtain 168 BCH parity bits; and splicing the BCH parity bits to the end of the scrambled signalling to obtain a BCH codeword with a length being N BCH =K sig +168 bits, wherein the BCH coding is specifically used to describe the problem of confirming the number of parity bits, that is, the number of the parity bits (168) is determined according to coding characteristics (e.g. BCH characteristics) in combination with the consideration of an overall block error ratio of signalling coding and modulation, for example, 168 BCH parity bits are able to correct 12-bit errors in signalling with a length being smaller than 6480 bits, while the number of 12-bit bits is further determined based on an overall block error ratio for improving signalling coding and modulation, and therefore the signalling may further be protected on the basis of an LDPC code by means of the processing in step S 1 - 2 *, thereby effectively improving the overall performance of signalling coding and modulation;

step S 1 - 3 *: extending the BCH codeword to obtain an extended BCH codeword with a length being K LDPC =6480 bits;

step S 1 - 4 *: conducting LDPC coding on the obtained extended BCH codeword, to obtain an LDPC codeword with a length being N LDPC =16200 bits;

step S 1 - 5 *: the LDPC codeword containing information bits of the first K LDPC bits and parity bits of the last N LDPC −K LDPC bits, conducting parity bit permutation on the parity bits to obtain permutated parity bits, and splicing the permutated parity bits to the end of the information bits to obtain a permutated LDPC codeword;

step S 1 - 6 *: calculating the number of punchings according to the length of the signalling (K sig bits), and punching a corresponding number of parity bits in the permutated LDPC codeword according to a predetermined punching rule, to obtain a punched LDPC codeword;

step S 1 - 7 *: removing zeros added in an extension operation from the punched LDPC codeword to obtain an LDPC codeword with zeros removed;

step S 1 - 8 *: conducting bit demultiplexing on the LDPC codeword with zeros removed to obtain a tuple sequence, wherein each tuple contains η mod =8 bits;

step S 1 - 9 *: conducting bit rotation on each tuple in the tuple sequence to obtain a tuple sequence, which is used for mapping; and

step S 1 - 10 *: mapping the tuple sequence, which is used for mapping, into a signalling symbol according to a predetermined mapping rule.

The extension processing in step S 1 - 3 * above is specifically described as follows. In this embodiment, step S 1 - 3 * comprises the specific steps of:

defining the extended BCH codeword to be formed by sequentially splicing K LDPC /Q bit groups, wherein each bit group contains Q bits, the number of bits Q within the bit group is the side length of an LDPC codeword sub-block, the value of Q is 360, and the K LDPC /Q bit groups respectively form the 0th group, the 1st group, until the K LDPC /Q−1th bit group from front to back;

if the number N Pad of completely extended bit groups is greater than zero, wherein

N P ⁢ a ⁢ d = ⌊ K L ⁢ D ⁢ P ⁢ C - N B ⁢ C ⁢ H Q ⌋ ,

filling the π(0)th group to the π(N Pad −1)th group in the extended BCH codeword with zeros, wherein

π ⁡ ( 0 ) , π ⁡ ( 1 ) , … ⁢ , π ⁡ ( K L ⁢ D ⁢ P ⁢ C Q - 1 )

is defined by the extension pattern table in Table 1;

if the number N Pad of the remaining extended bits is greater than zero, wherein N Pad =K LDPC −N BCH −QN Pad , then filling the first N Pad bits of the π(N Pad )th group with zeros; and filling bits which have not been filled with zeros of the extended BCH codeword with the BCH codeword with a length being N BCH from front to back.

The extension patterns in Table 1 below are jointly designed according to the capacity of each bit in constellation mapping and degree distribution of different variable nodes in the information bits of the LDPC codeword, and by optimizing the extension patterns, the coding and modulation performance may be effectively improved.

The LDPC coding processing in step S 1 - 4 * above is specifically described as follows, N LDPC −K LDPC parity bits p=[p 0 , p 1 , . . . , p N LDPC -K LDPC -1 ] are generated according to the extended BCH codeword m=[m 0 , m 1 , . . . , m K LDPC-1 ], and the parity bits are sequentially spliced to the end of the extended BCH codeword to obtain the LDPC codeword. Step S 1 - 4 * comprises the specific steps of:

initializing p i =0 (i=0, 1, . . . , N LDPC −K LDPC −1);

accumulating the parity bits of which the first row of digits is an address in the LDPC code table in Table 2 below, defining a set formed by the first row of digits as Φ 0 , firstly conducting p k =p k ⊕m 0 on all k satisfying k∈Φ 0 , and then with regard to all k satisfying k∈Φ 0 , conducting

then with regard to all k satisfying k∈Φ 0 , conducting

and by analogy, finally, with regard to all k satisfying k∈Φ 0 , conducting

accumulating the parity bits of which the second row of digits is an address in Table 2 below, defining a set formed by the second row of digits as Φ 1 , firstly conducting p k =p k αm Q on all k satisfying k∈Φ 1 , and then with regard to all k satisfying k∈Φ 1 , conducting

then with regard to all k satisfying k∈Φ 1 , conducting

and by analogy, finally, with regard to all k satisfying k∈Φ 1 , conducting

p ( k + ( Q - 1 ) ⁢ N L ⁢ D ⁢ P ⁢ C - K LDPC Q ) ⁢ m ⁢ o ⁢ d ⁡ ( N L ⁢ D ⁢ P ⁢ C - K LDPC ) = p ( k + ( Q - 1 ) ⁢ N L ⁢ D ⁢ P ⁢ C - K LDPC Q ) ⁢ m ⁢ o ⁢ d ⁡ ( N LDPC - K LDPC ) ⊕ m 2 ⁢ Q - 1 ;

and

by analogy, accumulating the parity bits of all the rows in the table until the

K L ⁢ D ⁢ P ⁢ C - N B ⁢ C ⁢ H Q

th

row, firstly conducting p k =p k ⊕m K LDPC -Q on all k satisfying

k ∈ Φ K L ⁢ D ⁢ P ⁢ C Q - 1 ,

and then with regard to all k satisfying

k ∈ Φ K L ⁢ D ⁢ P ⁢ C Q - 1 ,

conducting

then with regard to all k satisfying

k ∈ Φ K L ⁢ D ⁢ P ⁢ C Q - 1 ,

conducting

and by analogy, finally, with regard to all k satisfying

k ∈ Φ K L ⁢ D ⁢ P ⁢ C Q - 1 ,

conducting

p ( k + ( Q - 1 ) ⁢ N LDPC - K LDPC Q ⁢ mod ⁡ ( N LDPC - K LDPC ) = p ( k + ( Q - 1 ) ⁢ N LDPC - K LDPC Q ⁢ mod ⁡ ( N LDPC - K LDPC ) ⊕ m K LDPC - 1 ;

and

conducting p 1 =p 1 ⊕p 0 , then conducting p 2 =p 2 ⊕+p 1 , and then conducting p 3 =p 3 ⊕p 2 , and by analogy finally conducting

p N LDPC -K LDPC -1 =p N LDPC -K LDPC -1 ⊕p N LDPC -K LDPC -2 ; and

finally, after all the parity bits are sequentially spliced to the end of the extended BCH codeword, obtaining the LDPC codeword.

The parity bit permutation processing in step S 1 - 5 * above is specifically described as follows. In this embodiment, step S 1 - 5 * comprises the specific steps of:

conducting first parity bit permutation on the parity bits p=[p 0 , p 1 , . . . , p N LDPC -K LDPC -1 ] to obtain a first permutated parity bits u=[u 0 , u 1 , . . . , u N LDPC -K LDPC -1 ],

wherein

dividing the first permutated parity bits into

N L ⁢ D ⁢ P ⁢ C - K L ⁢ D ⁢ P ⁢ C Q

continuous bit groups, wherein each bit group contains Q bits, exchanging the positions of the bit groups so that the π p (k)th bit group

( 0 ≤ k < N L ⁢ D ⁢ P ⁢ C - K L ⁢ D ⁢ P ⁢ C Q )

before the exchange becomes the k th bit group after the exchange to obtain a second permutated parity bits,

wherein a permutation sequence

π p ⁡ ( 0 ) , π p ⁡ ( 1 ) , … ⁢ , π p ⁡ ( N L ⁢ D ⁢ P ⁢ C - K L ⁢ D ⁢ P ⁢ C Q )

is defined in the predetermined position permutation table in Table 3; and

sequentially splicing information bits and the second permutated parity bits to obtain the permutated LDPC codeword.

The permutation sequence in Table 3 below is jointly designed according to the capacity of each bit in constellation mapping and degree distribution of different variable nodes in the parity bits of the LDPC codeword, and by optimizing the permutation sequence, the coding and modulation performance may be effectively improved.

The specific numerical value of the number of bits in Table 3 is described as follows: in practical applications, in a transmission standard, information bits of the first several number of bits (e.g. 18 bits) are taken into consideration, and the parity bits are following the information bits so that the counting of the number of bits of the parity bits starts from the number of bits of that information bit (counting from the 18th bit). It needs to be noted that in Table 3 of this embodiment, what is described is to start counting from the 0th bit with regard to the parity bits, and if the preceding information bits and the following parity bits are comprehensively taken into consideration, the counting for the parity bits should accumulate the number of bits of the information bits. Those skilled in the art would readily understand that this is not limited by the difference of the starting point of specific numerical values of counting, so as to infer other specific parameters in a similar manner herein.

The punching processing in step S 1 - 6 * above is specifically described as follows. In this embodiment, step S 1 - 6 * comprises the specific steps of:

calculating the first punching number N punc_temp by means of a first punching formula according to the length K sig of the signalling, the first punching formula being N punc_temp =└A(K LDPC −K sig −168)+B┘, and in this embodiment, the length of the extended BCH codeword being K LDPC =6480 and A and B being constants

A = 4 ⁢ 9 2 ⁢ 5 ⁢ 6 , B = 8 ⁢ 2 ⁢ 4 ⁢ 6 ,

wherein 168 in K LDPC −K sig −168 is the number of bits L p of parity bits of the BCH, wherein the constant A and the constant B are designed and determined in order to enable the signalling coding and modulation scheme to have a close receiving threshold with different K sig ;

calculating the second punching number N punc by means of a second punching formula according to the first punching number N punc_temp the second punching formula being:

N p ⁢ u ⁢ n ⁢ c = N punc_temp - ( ⌈ N B ⁢ C ⁢ H + N L ⁢ D ⁢ P ⁢ C - K L ⁢ D ⁢ P ⁢ C - N punc_temp η m ⁢ o ⁢ d ⌉ ⁢ η m ⁢ o ⁢ d - N B ⁢ C ⁢ H - N L ⁢ D ⁢ P ⁢ C + K L ⁢ D ⁢ P ⁢ C + N punc_temp ) ;

and

removing the last N punc bits of the LDPC codeword to obtain a punched LDPC codeword.

The bit demultiplexing processing in step S 1 - 8 * above is specifically described as follows. In this embodiment, step S 1 - 8 * comprises the specific steps of:

successively writing the LDPC codeword with zeros removed into a matrix containing η mod columns and

⌈ N B ⁢ C ⁢ H + N L ⁢ D ⁢ P ⁢ C - K L ⁢ D ⁢ P ⁢ C - N punc_temp η m ⁢ o ⁢ d ⌉

rows according to columns; and

sequentially reading out from the matrix by rows, and forming one tuple with η mod bits in each row so as to obtain the tuple sequence containing

⌈ N B ⁢ C ⁢ H + N L ⁢ D ⁢ P ⁢ C - K L ⁢ D ⁢ P ⁢ C - N punc_temp η m ⁢ o ⁢ d ⌉

tuples.

The bit rotation processing in step S 1 - 9 * above is specifically described as follows. In this embodiment, step S 1 - 9 * comprises the specific steps of:

keeping the first tuple in the tuple sequence unchanged; rotating the second tuple in the tuple sequence by one bit, i.e. the first bit of the tuple after rotation is the η mod th bit in the original tuple, the second bit of the tuple after rotation is the first bit in the original tuple, the third bit of the tuple after rotation is the second bit of the original tuple, and by analogy, the η mod th bit of the tuple after rotation is the η mod −1th bit of the original tuple; by the same reasoning, rotating the third tuple of the tuple sequence by two bits; by the same reasoning, rotating the fourth tuple of the tuple sequence by three bits; and by analogy, rotating all the tuples in the tuple sequence to obtain a rotated tuple sequence.

In other words, the first tuple (the tuple number y corresponds to 0) of the tuple sequence is kept unchanged, and the yth tuple (the tuple number y corresponds to 1, 2, 3 . . . ) of the tuple sequence is rotated by y−1 bits, thereby correspondingly rotating all the tuples in the tuple sequence to obtain the rotated tuple sequence.

It is noted that rotating the η MOD +1th, the 2η MOD +1th tuples, etc. by an integral multiple of η MOD bits is equivalent to no rotation, and rotating the η MOD +2th, the 2η MOD +2 th, tuples, etc. is equivalent to rotating one bit.

The predetermined mapping rule in step S 1 - 10 * above is specifically described as follows. In this embodiment, step S 1 - 10 * comprises the specific steps of:

mapping each tuple of the tuple sequence into one signalling symbol, wherein the mapping rule is as shown in the constellation mapping rule table in Table 4, for example, when one tuple is “00000001”, it will be mapped into 1.2668+0.8034i.

In summary, the constellation mapping rule table in Table 4 provides a 256QAM mapping rule. If a constellation mapping rule table different from Table 4 is used, then parameter values in a corresponding extension pattern table and a predetermined position permutation table and the specific values of the constants A and B in the first punching formula in the punching processing in step S 1 - 6 * will also change accordingly.

The 256QAM constellation mapping rule table, parameter values in the corresponding extension pattern table and the predetermined position permutation table and the specific values of the constants A and B in the first punching formula in the punching processing in step S 1 - 6 * used in this embodiment are optimally designed, which can effectively reduce the computation complexity of coding and modulation, and demodulation and decoding of a system, and improve system performance.

In the present invention, not only all of step S 1 - 1 * to step S 1 - 10 * as above are necessarily contained in the signalling coding and modulation method, but also one or at least any two free combinations of step S 1 - 1 * to step S 1 - 10 * above may be selectively utilized to conduct coding and modulation on signalling and correspondingly conduct demodulation and decoding, and the specific steps of one or at least any two free combinations involved may be obtained correspondingly and will not be listed one by one for description, and only [1] a signalling coding and modulation method containing the above extension processing, [2] a signalling coding and modulation method containing the above parity bit permutation processing, and [3] a signalling coding and modulation method containing the above punching processing, are merely taken as examples for description.

With regard to [1] a signalling coding and modulation method containing the above extension processing: an embodiment of the present invention further provides a signalling coding and modulation method, comprising the steps of:

conducting BCH coding on the signalling, and extending an obtained BCH codeword to obtain an extended BCH codeword; and processing the extended BCH codeword to obtain a signalling symbol,

wherein if the number N Pad of completely extended groups is greater than zero, then the π(0)th group until the π(N Pad −1)th group in the extended BCH codeword are filled with zeros; if the number N Pad of the remaining extended bits is greater than zero, then the first K LDPC −N BCH −QN Pad bits of the π(N Pad )th group are filled with zeros; and bit positions which have not been filled with zeros in the extended BCH codeword are filled with the BCH codeword from front to back.

By the same reasoning, the π(0)th group, π(1)th group, . . . ,

π ⁡ ( K LDPC Q - 1 )

th group are defined by the extension pattern table in Table 1 above.

With regard to [2] a signalling coding and modulation method containing the above parity bit permutation processing: an embodiment of the present invention further provides a signalling coding and modulation method, comprising the steps of:

conducting signalling processing to obtain a encoded codeword; conducting parity bit permutation on the encoded codeword to obtain a permutated encoded codeword; processing the permutated encoded codeword to obtain a signalling symbol,

wherein the encoded codeword contains information bits and parity bits; conducting parity bit permutation on the parity bits to obtain permutated parity bits, and splicing the permutated parity bits to the end of the information bits to obtain a permutated LDPC codeword;

conducting first parity bit permutation on the parity bits to obtain a first permutated parity bits; dividing the first permutated parity bits into several continuous bit groups, determining the positions of exchange bit groups by means of the predetermined position permutation table Table 3 so that the π p (k)th bit group before the exchange becomes the k th bit group after the exchange to obtain a second permutated parity bits; and sequentially splicing information bits and the second permutated parity bits to obtain the permutated encoded codeword.

By the same reasoning, the predetermined position permutation table uses the predetermined position permutation table in Table 3 above.

With regard to [3] a signalling coding and modulation method containing the above punching processing: an embodiment of the present invention further provides a signalling coding and modulation method, comprising the steps of:

conducting processing on signalling to obtain a processed encoded codeword; according to the length of the signalling, punching the processed encoded codeword according to a predetermined punching rule to obtain a punched encoded codeword; and processing the punched encoded codeword to obtain a signalling symbol,

wherein the predetermined punching rule comprises the steps of: calculating a first punching number by means of a first punching calculation formula according to the length of the signalling; calculating a second punching number by means of a second punching calculation formula according to the first punching number; and removing the second punching number of last bits of the processed encoded codeword.

In addition, an embodiment of the present invention further provides a signalling demodulation and decoding method. FIG. 3 shows a schematic diagram of the procedure of a specific embodiment of signalling demodulation and decoding of the present invention. With reference to FIG. 3 , signalling demodulation and decoding comprises the steps of:

step S 2 - 1 : demapping a receiving end signalling symbol corresponding to a sending end signalling symbol according to a predetermined mapping rule to obtain a log likelihood ratio;

step S 2 - 2 : conducting corresponding inverse second predetermined processing, inverse punching and inverse permutation on the log likelihood ratio according to the steps of parity bit permutation, punching and second predetermined processing in the signalling coding and modulation method at a sending end to obtain a log likelihood ratio of a receiving end encoded codeword corresponding to a sending end encoded codeword; and

step S 2 - 3 : conducting corresponding decoding, inverse extension and inverse first predetermined processing on the log likelihood ratio of the receiving end encoded codeword according to the steps of first predetermined processing, extension and predetermined coding in the signalling coding and modulation method at a sending end to obtain signalling.

Step S 2 - 1 to step S 2 - 3 at the receiving end are described corresponding to step S 1 - 1 to step S 1 - 4 in the overall procedure at the sending end. When the signalling coding and modulation method does not only conduct a series of extension, coding, parity bit permutation, punching and mapping processing on signalling, but also further conducts at least any complementary processing such as step S 1 - 1 * to step S 1 - 10 *, e.g. scrambling the signalling, and then successively conducting BCH coding, extension, LDPC coding, parity bit permutation, zero removing, bit demultiplexing, bit rotation and constellation mapping and the like, then correspondingly, signalling demodulation and decoding at the receiving end has the specific steps as follows.

Step S 2 - 2 comprises: according to parity bit permutation, punching, zero removing, bit demultiplexing and bit rotation rules at the transmitting end, conducting corresponding inverse processing on the log likelihood ratio, to obtain a receiving end LDPC encoded codeword log likelihood ratio corresponding to the LDPC encoded codeword; and

step S 2 - 3 : according to the scrambling, BCH coding, extension and LDPC coding rules at the transmitting end, conducting decoding and corresponding inverse processing on the LDPC encoded codeword log likelihood ratio at the receiving end to obtain the signalling.

It needs to be noted that in step S 2 - 2 , the corresponding inverse processing corresponds to parity bit permutation, punching, zero removing, bit demultiplexing and bit rotation rules at the transmitting end, and the specific implementation does not necessarily need to be conducted in an order opposite to the transmitting end, and the order of specific steps can be altered by various conversions or mutual combinations. In step 2 - 3 , the rule for decoding the LDPC encoded codeword log likelihood ratio at the receiving end corresponds to the LDPC coding rule at the transmitting end. The corresponding inverse processing corresponds to scrambling, BCH coding and extension rules at the transmitting end, and the specific implementation does not necessarily need to be conducted in an order opposite to the transmitting end, and the order of specific steps can be altered by various conversions or mutual combinations. The BCH decoding rule corresponds to the BCH coding rule at the transmitting end.

In particular, the inverse extension step, inverse parity bit permutation step, inverse punching rule and the involved parameters, tables, formulas, etc. used in the signalling demodulation and decoding method respectively correspond to the signalling coding and modulation method in the embodiment above, which will not be described again.

In addition, an embodiment of the present invention further provides a signalling coding and modulation device, characterized in that the device comprises: an extension coding module: extending signalling which has been subjected to first predetermined processing according to an extension pattern table to obtain an extended codeword, and conducting predetermined coding on the extended codeword to obtain a encoded codeword; a permutation module: conducting parity bit permutation on parity bits in the encoded codeword and then splicing the permutated parity bits to the end of information bits in the encoded codeword, to obtain a permutated encoded codeword; a punching module: according to the length of the signalling, punching the permutated encoded codeword according to a predetermined punching rule to obtain a punched encoded codeword; and a processing and mapping module: conducting second predetermined processing on the punched encoded codeword to obtain a tuple sequence, which is used for mapping, and then mapping the obtained tuple sequence into a signalling symbol according to a predetermined mapping rule.

In addition, an embodiment of the present invention further provides a signalling demodulation and decoding device, characterized in that the device comprises: a demapping module: demapping a receiving end signalling symbol corresponding to a sending end signalling symbol according to a predetermined mapping rule to obtain a log likelihood ratio; a corresponding permutation deprocessing module: conducting corresponding inverse second predetermined processing, inverse punching and inverse permutation on the log likelihood ratio according to the steps of parity bit permutation, punching and second predetermined processing in the signalling coding and modulation device at a sending end to obtain a log likelihood ratio of a receiving end encoded codeword corresponding to a sending end encoded codeword; and a decoding module: conducting corresponding decoding, inverse extension and inverse first predetermined processing on the log likelihood ratio of the receiving end encoded codeword according to the steps of first predetermined processing, extension and predetermined coding in the signalling coding and modulation device at a sending end to obtain signalling.

The signalling coding and modulation device and signalling demodulation and decoding device provided in this embodiment respectively correspond to the signalling coding and modulation method and signalling demodulation and decoding method in the embodiments above, and therefore the structures of and technical factors in the devices may be formed by corresponding conversion of generation methods, and will not be described again herein.

Although the present invention has been disclosed above with preferred embodiments, they do not mean to limit the present invention. Any skilled in the art may utilize the method and technical contents disclosed above to make possible changes and amendments on the technical solutions of the present invention without departing from the spirit and scope of the present invention. Therefore, any content that does not depart from the technical solutions of the present invention, and any simple amendments, equivalent variations and modifications made on the above embodiments according to the technical essence of the present invention all fall within the scope of protection of the technical solutions of the present invention.