Electrostatic discharge protection circuit

The invention relates to a protection circuit, and more particularly to an electrostatic discharge (ESD) protection circuit.

As the semiconductor manufacturing process develops, electrostatic discharge (ESD) protection has become one of the most critical reliability issues for integrated circuits (IC). In particular, as the semiconductor manufacturing process advances into the deep sub-micron stage, scaled-down devices and thinner gate oxides are more vulnerable to ESD stress.

In accordance with an embodiment of the disclosure, an electrostatic discharge (ESD) protection circuit comprises a detection circuit, a voltage-divider element, and a discharge element. The detection circuit is coupled between a first power line and a second power line. In response to an ESD event, the detection circuit enables a turn-on signal. The voltage-divider element is coupled between the first power line and a third power line and receives the turn-on signal. The discharge element is coupled between the second and third power lines. In response to the turn-on signal being enabled, the first discharge element discharges an ESD current.

In accordance with another embodiment of the disclosure, an ESD protection circuit comprises a detection circuit, a first transistor, and a second transistor. The detection circuit is coupled between a first power line and a second power line. In response to an ESD event, the detection circuit enables a turn-on signal. The first transistor comprises a first bulk, a first gate receiving the turn-on signal, a first drain coupled to a third power line, and a first source coupled to the second power line. The second transistor comprises a second bulk, a second gate receiving the turn-on signal, a second drain coupled to the third power line, and a second source coupled to the first power line. In response to the turn-on signal being enabled, the first and second transistors are turned on to discharge an ESD current. The junction voltage between the first drain and the first bulk is higher than the junction voltage between the first source and the first bulk. The junction voltage between the second drain and the second bulk is higher than the junction voltage between the second source and the second bulk.

The invention can be more fully understood by referring to the following detailed description and examples with references made to the accompanying drawings, wherein:

FIG. 1 is a schematic diagram of an exemplary embodiment of an electrostatic discharge (ESD) protection circuit according to various aspects of the present disclosure.

FIG. 2 is a schematic diagram of another exemplary embodiment of the ESD protection circuit according to various aspects of the present disclosure.

FIG. 3 is a schematic diagram of an exemplary embodiment of a detection circuit according to various aspects of the present disclosure.

FIG. 4 is a schematic diagram of an exemplary embodiment of a low-voltage transistor according to various aspects of the present disclosure.

FIG. 5 is a schematic diagram of an exemplary embodiment of a high-voltage transistor according to various aspects of the present disclosure.

The present invention will be described with respect to particular embodiments and with reference to certain drawings, but the invention is not limited thereto and is only limited by the claims. The drawings described are only schematic and are non-limiting. In the drawings, the size of some of the elements may be exaggerated for illustrative purposes and not drawn to scale. The dimensions and the relative dimensions do not correspond to actual dimensions in the practice of the invention.

FIG. 1 is a schematic diagram of an exemplary embodiment of an electrostatic discharge (ESD) protection circuit according to various aspects of the present disclosure. The ESD protection circuit 100 comprises a detection circuit 110 , a voltage-divider element 120 , and a discharge element 130 . The detection circuit 110 is coupled between power lines PL 1 and PL 2 and determines whether an ESD event occurs. When the ESD event occurs, the detection circuit 110 enables a turn-on signal SON. When no ESD event occurs, the detection circuit 110 does not enable the turn-on signal SON. In one embodiment, when there is no ESD event, the power line PL 1 receives a low operation voltage VDD, and the power line PL 2 receives a ground voltage VSS. In this case, the low operation voltage VDD is higher than the ground voltage VSS. In one embodiment, the low operation voltage VDD is about 5V, and the ground voltage VSS is about 0V.

The voltage-divider element 120 is coupled between the power lines PL 1 and PL 3 and receives the turn-on signal SON. In this embodiment, the voltage-divider element 120 is a bridge between the high operation voltage VCC and the low operation voltage VDD. For example, in a normal mode (no ESD event), the power line PL 1 receives the low operation voltage VDD, and the power line PL 3 receive the high operation voltage VCC. In one embodiment, the low operation voltage VDD is lower than the high operation voltage VCC. For example, the low operation voltage VDD is about 1.8V, 3.3V, or 5V, and the high operation voltage VCC is about 30V. Since the voltage-divider element 120 is a high-voltage element, the voltage-divider element 120 is capable of accepting the high operation voltage VCC.

In this embodiment, the voltage-divider element 120 is a high-voltage transistor HVN 2 . The gate 121 of the high-voltage transistor HVN 2 receives the turn-on signal SON. The drain 122 of the high-voltage transistor HVN 2 is coupled to the power line PL 3 . The source 123 of the high-voltage transistor HVN 2 is coupled to the power line PL 1 . The bulk 124 of the high-voltage transistor HVN 2 is coupled to the power line PL 2 .

The type of high-voltage transistor HVN 2 is not limited in the present disclosure. In this embodiment, the high-voltage transistor HVN 2 is an N-type transistor, but the disclosure is not limited thereto. In other embodiments, the high-voltage transistor HVN 2 is a P-type transistor. In some embodiments, the junction voltage between the drain 122 and the bulk 124 of the high-voltage transistor HVN 2 is higher than the junction voltage between the source 123 and the bulk 124 of the high-voltage transistor HVN 2 . In one embodiment, the drain 122 of the high-voltage transistor HVN 2 is formed in a diffused region. Since the doped concentration of the diffused region is low, the drain 122 is capable of accepting the high voltage. In one embodiment, the high-voltage transistor HVN 2 is a lateral diffused metal-oxide-semiconductor field-effect transistor (LDMOSFET) or a double diffused metal-oxide-semiconductor field-effect transistor (DDMOSFET).

The discharge element 130 is coupled between the power lines PL 2 and PL 3 . When the turn-on signal SON is enabled, the discharge element 130 discharges an ESD current. In this embodiment, the discharge element 130 is a high-voltage transistor HVN 1 . The gate 131 of the high-voltage transistor HVN 1 receives the turn-on signal SON. The drain 132 of the high-voltage transistor HVN 1 is coupled to the power line PL 3 . The source 133 and the bulk 134 of the high-voltage transistor HVN 1 are coupled to the power line PL 2 . The type of high-voltage transistor HVN 1 is not limited in the present disclosure. In this embodiment, the high-voltage transistor HVN 1 is an N-type transistor, but the disclosure is not limited thereto. In other embodiments, the high-voltage transistor HVN 1 is a P-type transistor. In some embodiments, the junction voltage between the drain 132 and the bulk 134 of the high-voltage transistor HVN 1 is higher than the junction voltage between the source 133 and the bulk 134 of the high-voltage transistor HVN 1 . In one embodiment, the high-voltage transistor HVN 1 is a LDMOSFET or a DDMOSFET.

When an ESD event occurs in the power line PL 3 and the power line PL 1 is at a floating level, since the high-voltage transistor HVN 2 does not be turned off completely, a portion of the ESD current flows from the power line PL 3 , through the high-voltage transistor HVN 2 and to the detection circuit 110 . At this time, the detection circuit 110 enables the turn-on signal SON. Therefore, the high-voltage transistor HVN 1 is turned on. At this time, the majority ESD current passes from the power line PL 3 , through the high-voltage transistor HVN 1 , and to the power line PL 2 .

When there is no ESD event, the power line PL 1 receives the low operation voltage VDD, the power line PL 3 receives the high operation voltage VCC, and the power line PL 2 receives the ground voltage VSS. At this time, the detection circuit 110 does not enable the turn-on signal SON. Therefore, the high-voltage transistors HVN 1 and HVN 2 are turned off. Since the high-voltage transistor HVN 2 prevents the high operation voltage VCC from entering the detection circuit 110 , the elements (e.g., transistors) in the detection circuit 110 do not be damaged by the high operation voltage VCC.

FIG. 2 is a schematic diagram of another exemplary embodiment of the ESD protection circuit according to various aspects of the present disclosure. FIG. 2 is similar to FIG. 1 except for the addition of a discharge element 140 . The discharge element 140 is coupled between the power lines PL 1 and PL 2 . When the turn-on signal SON is enabled, the discharge element 140 discharges an ESD current. In this embodiment, the discharge element 140 is a low-voltage transistor LVN 1 . The gate 141 of the low-voltage transistor LVN 1 receives the turn-on signal SON. The drain 142 of the low-voltage transistor LVN 1 is coupled to the power line PL 1 . The source 143 and the bulk 144 of the low-voltage transistor LVN 1 are coupled to the power line PL 2 .

The type of low-voltage transistor LVN 1 is not limited in the present disclosure. In this embodiment, the low-voltage transistor LVN 1 is an N-type transistor, but the disclosure is not limited thereto. In other embodiments, the low-voltage transistor LVN 1 is a P-type transistor. In some embodiments, the junction voltage between the drain 122 and the bulk 124 of the high-voltage transistor HVN 2 is higher than the junction voltage between the drain 142 and the bulk 144 of the low-voltage transistor LVN 1 . In another embodiment, the junction voltage between the drain 132 and the bulk 134 of the high-voltage transistor HVN 1 is also higher than the junction voltage between the drain 142 and the bulk 144 of the low-voltage transistor LVN 1 . In one embodiment, the drain 142 and the source 143 of the low-voltage transistor LVN 1 are formed in the same well, e.g., a P-type well.

FIG. 3 is a schematic diagram of an exemplary embodiment of a detection circuit according to various aspects of the present disclosure. The detection circuit 110 comprises a resistor R, a capacitor C, low-voltage transistors LVP and LVN 2 . The resistor R is coupled between the power line PL 1 and the node A. The capacitor C is coupled between the node A and the power line PL 2 . In other embodiments, the capacitor C is a transistor. In this case, the gate of the transistor is coupled to the node A, and the drain, the source, and the bulk of the transistor are coupled to the power line PL 2 .

The gate 311 of the low-voltage transistor LVP is coupled to the node A. The source 312 of the low-voltage transistor LVP is coupled to the power line PL 1 . The drain 313 of the low-voltage transistor LVP is coupled to the node B. The gate 315 of the low-voltage transistor LVN 2 is coupled to the node A. The source 317 of the low-voltage transistor LVN 2 is coupled to the power line PL 2 . The drain 316 of the low-voltage transistor LVN 2 is coupled to the node B. In this embodiment, the low-voltage transistors LVP and LVN 2 are low-voltage transistors. In one embodiment, the low-voltage transistor LVP is a P-type transistor, and the low-voltage transistor LVN 2 is an N-type transistor. In this case, the low-voltage transistors LVP and LVN 2 constitute an inverter to invert the level of the node A. For example, when an ESD event occurs, the level of the node A is a low level. Therefore, the level of the node B is a high level. When no ESD event occurs, the level of the node A is a high level. Therefore, the level of the node B is a low level.

In this embodiment, the junction voltage between the source 312 and the bulk 314 of the low-voltage transistor LVP or the junction voltage between the drain 313 and the bulk 314 of the low-voltage transistor LVP is lower than the junction voltage between the drain 122 and the bulk 124 of the high-voltage transistor HVN 2 . In this case, the junction voltage between the source 312 and the bulk 314 of the low-voltage transistor LVP or the junction voltage between the drain 313 and the bulk 314 of the low-voltage transistor LVP is lower than the junction voltage between the drain 132 and the bulk 134 of the high-voltage transistor HVN 1 .

In another embodiment, the junction voltage between the drain 316 and the bulk 318 of the low-voltage transistor LVN 2 and the junction voltage between the source 317 and the bulk 318 of the low-voltage transistor LVN 2 are lower than the junction voltage between the drain 122 and the bulk 124 of the high-voltage transistor HVN 2 . In this case, the junction voltage between the drain 316 and the bulk 318 of the low-voltage transistor LVN 2 and the junction voltage between the source 317 and the bulk 318 of the low-voltage transistor LVN 2 are lower than the junction voltage between the drain 132 and the bulk 314 of the high-voltage transistor HVN 1 .

FIG. 4 is a schematic diagram of an exemplary embodiment of a low-voltage transistor according to various aspects of the present disclosure. The low-voltage transistor 400 comprises a well 410 , doped regions 421 ˜ 423 , and a gate structure 424 . The doped regions 421 ˜ 423 are disposed in the well 410 . In this embodiment, each of the well 410 and the doped region 421 has a first conductive type. The doped concentration of the doped region 421 is higher than the doped concentration of the well 410 . Each of the doped regions 422 and 423 has a second conductive type. In this embodiment, the junction voltage between the doped 423 and the well 410 is similar to the junction voltage between the doped region 422 and the well 410 . In one embodiment, the first conductive type is a P-type, and the second conductive type is N-type. The gate structure 424 is formed on the well 410 .

In some embodiments, the doped region 421 is electrically connected to a bulk contact pad 431 . The doped region 422 is electrically connected to a source contact pad 432 . The gate structure 424 is electrically connected to a gate contact pad 433 . The doped region 423 is electrically connected to a drain contact pad 434 . In this case, the bulk contact pad 431 serves as the bulk of the transistor 400 , the source contact pad 432 serves as the source of the transistor 400 , the gate contact pad 433 serves as the gate of the transistor 400 , and the drain contact pad 434 serves as a drain of the transistor 400 .

FIG. 5 is a schematic diagram of an exemplary embodiment of a high-voltage transistor according to various aspects of the present disclosure. The high-voltage transistor 500 comprises a well 510 , a diffused region 520 , doped regions 531 ˜ 533 , and a gate structure 534 . The doped regions 531 and 532 are disposed in the well 510 . In this embodiment, each of the well 510 and the doped region 531 has a first conductive type. The doped concentration of the doped region 531 is higher than the doped concentration of the well 510 . The doped region 532 has a second conductive type. The second conductive type is opposite to the first conductive type. For example, when the first conductive type is a P-type, the second conductive type is N-type.

The diffused region 520 is disposed in the well 510 . The doped region 533 is formed in the diffused region 520 . Each of the diffused region 520 and the doped region 533 has the second conductive type. The doped concentration of the diffused region 520 is lower than the doped concentration of the doped region 533 . In one embodiment, the diffused region 520 is a high-voltage N-type diffused region (HVNDD). In this embodiment, the junction voltage between the diffused region 520 and the well 510 is higher than the junction voltage between the doped region 532 and the well 510 . In one embodiment, the junction voltage between the doped region 532 and the well 510 is similar to the junction voltage between the doped region 423 and the well 410 and the junction voltage between the doped region 422 and the well 410 of FIG. 4 . In this embodiment, the gate structure 534 is formed on the well 510 and overlaps a portion of the diffused region 520 .

In some embodiments, the doped region 531 is electrically connected to a bulk contact pad 541 . The doped region 532 is electrically connected to a source contact pad 542 . The gate structure 534 is electrically connected to a gate contact pad 543 . The doped region 533 is electrically connected to a drain contact pad 544 . In such cases, the bulk contact pad 541 serves as the bulk of the transistor 500 , the source contact pad 542 serves as the source of the transistor 500 , the gate contact pad 543 serves as the gate of the transistor 500 , and the drain contact pad 544 serves as a drain of the transistor 500 .

Since the diffused region 520 has a low doped concentration, the junction voltage between the doped region 533 and the bulk 510 is increased so that the doped region 533 can accept a high operation voltage, such as VCC. In FIG. 1 , when the high-voltage transistor 500 serves as the voltage-divider element 120 , the high-voltage transistor 500 can accept the high operation voltage VCC and avoid the high operation voltage VCC from damaging the elements in the detection circuit 110 .

It will be understood that when an element or layer is referred to as being “on”, “connected to” or “coupled to” another element or layer, it can be directly on, connected or coupled to the other element or layer or intervening elements or layers may be present.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. It should be understood that although the terms “first,” “second,” etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another.

While the invention has been described by way of example and in terms of the preferred embodiments, it should be understood that the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). For example, it should be understood that the system, device and method may be realized in software, hardware, firmware, or any combination thereof. Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.