Display device and driving method thereof

This application claims priority to and the benefit of Korean Patent Application No. 10-2021-0020156 filed in the Korean Intellectual Property Office on Feb. 15, 2021, the entire contents of which are incorporated herein by reference.

1. Field

The present disclosure generally relates to a display device and a driving method of the same. More particularly, the present disclosure relates to a display device that enables to prevent a flicker and a driving method of the same.

2. Description of the Related Art

As information technology has developed, importance of a display device, which is a connection medium between a user and information, has been highlighted. Accordingly, the use of display devices such as a liquid crystal display device, an organic light emitting display device, and the like has been increasing.

When the display device displays a moving picture, it is preferable to display it at a high frequency because its motion may be smoothly displayed. However, when the display device displays a still image, since there is no motion, it is fine even to display the still image at a low frequency. In addition, when the still image is displayed at a low frequency, it is advantageous in terms of power consumption.

However, when a display frequency of the display device is switched from a high frequency to a low frequency, there is a problem that a flicker may be viewed as a luminance reduction period is changed. In addition, a flicker may occur when a specific pattern is displayed during low-frequency driving.

The present disclosure has been made in an effort to provide a display device and a driving method thereof that may prevent a flicker from being viewed when a display frequency is switched from a high frequency to a low frequency.

In addition, the present disclosure has been made in an effort to provide a display device and a driving method thereof that may prevent a flicker from occurring when a specific pattern is displayed during low-frequency driving.

An embodiment of the present disclosure provides a display device including: a pixel unit in which respective pixel rows extend in a first direction, odd numbered pixel rows and even numbered pixel rows are alternately disposed in a second direction, and pixels included in the respective pixel rows are designated as dots in two or more units; a gray difference calculator that calculates a difference between representative grays of dots adjacent in the second direction among dots of a p-th pair of the pixel rows; an edge detector that increases an edge dot number when a first condition in which the difference between the representative grays is larger than a first threshold value is satisfied; and a first pattern detector that increases an edge number when the edge dot number is larger than a second threshold value, and that generates a first pattern detection signal when the edge number is larger than a third threshold value.

The display device may further include a scan driver that, when the first pattern detection signal is not generated and when an image is determined to be a still image, provides scan signals having a turn-on level to the odd-numbered pixel rows during a first sub-frame period, and provides scan signals having a turn-on level to the even-numbered pixel rows during a second sub-frame period after the first sub-frame period.

When the first pattern detection signal is generated and when the image is determined to be the still image, the scan driver may alternately provide the scan signals having the turn-on level to the odd numbered pixel rows and the even numbered pixel rows.

The gray difference calculator may calculate a difference between the representative grays of a predetermined number of dots including q-th dots in the first direction among the dots of the p-th pair, and may increase q.

When a second condition that the edge number is 0 or a (p−1)-th pair is an edge is satisfied in addition to the first condition, the edge detector may increase the edge dot number and registers the p-th pair as the edge.

When at least one of the first condition and the second condition is not satisfied, the edge detector may register the p-th pair as a non-edge, and may initialize the edge dot number.

After the p-th pair is registered as the edge or the non-edge, when increased q-th dots are not last dots of the p-th pair, the gray difference calculator may calculate a difference between representative grays of a predetermined number of dots including the increased q-th dots.

The first pattern detector may operate only when the increased q-th dots are the last dots of the p-th pair after the p-th pair is registered as the edge or the non-edge.

When the edge dot number is smaller than the second threshold value, the first pattern detector may initialize the edge number.

When the edge dot number is smaller the second threshold value or the edge number is smaller than the third threshold value, the gray difference calculator may calculate a difference between representative grays of dots adjacent to the second direction among dots of a (p+1)-th pair of the pixel rows.

The first pattern detector, when the first pattern detection signal is generated, may further generate pattern position information for a detected pattern, and the display device may further include a pattern luminance calculator that calculates luminance of the pattern based on the pattern position information and the representative grays.

The pattern luminance calculator may generate a pattern valid signal when the luminance of the pattern is larger than a reference luminance, and the display device may further include a second pattern detector that generates a second pattern detection signal only when both the pattern valid signal and the first pattern detection signal are received.

The display device may further include a scan driver that, when the second pattern detection signal is not generated and when an image is determined to be a still image, provides scan signals having a turn-on level to the odd-numbered pixel rows during the first sub-frame period, and provides scan signals having a turn-on level to the even-numbered pixel rows during the second sub-frame period after the first sub-frame period.

When the second pattern detection signal is generated and when the image is determined to be the still image, the scan driver may alternately provide the scan signals having the turn-on level to the odd numbered pixel rows and the even numbered pixel rows.

Another embodiment of the present disclosure provides a driving method of a display device that includes a pixel unit in which respective pixel rows extend in a first direction, odd numbered pixel rows and even numbered pixel rows are alternately disposed in a second direction, and pixels included in the respective pixel rows are designated as dots in two or more units, including: calculating a difference between representative grays of dots adjacent in the second direction among dots of a p-th pair of the pixel rows; increasing an edge dot number when a first condition that the difference between the representative grays is larger than the first threshold value is satisfied; increasing an edge number when the edge dot number is larger than a second threshold value; and generating a first pattern detection signal when the edge number is larger than a third threshold value.

The driving method may further include: providing, when the first pattern detection signal is not generated and when an image is determined to be a still image, scan signals having a turn-on level to the odd-numbered pixel rows during a first sub-frame period, and providing scan signals having a turn-on level to the even-numbered pixel rows during a second sub-frame period after the first sub-frame period.

The driving method may further include: alternately providing, when the first pattern detection signal is generated and when the image is determined to be the still image, the scan signals having the turn-on level to the odd numbered pixel rows and the even numbered pixel rows.

The driving method may further include: generating, when the first pattern detection signal is generated, pattern position information for a detected pattern; calculating luminance of the pattern based on the pattern position information and the representative grays; generating a pattern valid signal when the luminance of the pattern is larger than a reference luminance; and generating a second pattern detection signal only when both the pattern valid signal and the first pattern detection signal are received.

The driving method may further include: providing, when the second pattern detection signal is not generated and when an image is determined to be a still image, scan signals having a turn-on level to the odd-numbered pixel rows during the first sub-frame period, and providing scan signals having a turn-on level to the even-numbered pixel rows during the second sub-frame period after the first sub-frame period.

The driving method may further include: alternately providing, when the second pattern detection signal is generated and when the image is determined to be the still image, the scan signals having the turn-on level to the odd numbered pixel rows and the even numbered pixel rows.

The display device and the driving method thereof according to the present disclosure may prevent a flicker from being viewed when a display frequency is switched from a high frequency to a low frequency.

The display device and the driving method thereof according to the present disclosure may prevent a flicker from occurring when a specific pattern is displayed during low-frequency driving.

FIG. 1 illustrates a schematic view for explaining a display device according to an embodiment of the present disclosure.

FIG. 2 illustrates a schematic view for explaining a pixel according to an embodiment of the present disclosure.

FIG. 3 illustrates a schematic view for explaining a scan driver according to an embodiment of the present disclosure.

FIG. 4 illustrates a schematic view for explaining a stage according to an embodiment of the present disclosure.

FIG. 5 illustrates a schematic view for explaining a driving method of a scan driver according to an embodiment of the present disclosure.

FIGS. 6, 7, 8, and 9 illustrate schematic views for explaining a first frame period and a second frame period according to an embodiment of the present disclosure.

FIGS. 10, 11, 12, and 13 illustrate schematic views for explaining a first frame period and a second frame period according to another embodiment of the present disclosure.

FIG. 14 illustrates a schematic view for explaining a first frame period and a second frame period according to another embodiment of the present disclosure.

FIG. 15 illustrates a schematic view for explaining a scan driver according to another embodiment of the present disclosure.

FIG. 16 illustrates a schematic view for explaining a pixel unit according to an embodiment of the present disclosure.

FIG. 17 illustrates a schematic view for explaining a display mode controller according to an embodiment of the present disclosure.

FIGS. 18, 19, and 20 illustrate schematic views for explaining a pattern determiner according to an embodiment of the present disclosure.

FIGS. 21 and 22 illustrate schematic views for explaining a pattern determiner according to another embodiment of the present disclosure.

The present disclosure will be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the disclosure are shown. As those skilled in the art would realize, the described embodiment may be modified in various different ways, all without departing from the spirit or scope of the present.

In order to clearly describe the present disclosure, parts that are irrelevant to the description are omitted, and identical or similar constituent elements throughout the specification are denoted by the same reference numerals. Therefore, the above-mentioned reference numerals may be used in other drawings.

Further, in the drawings, the size and thickness of each element are arbitrarily illustrated for ease of description, and the present disclosure is not necessarily limited to those illustrated in the drawings. In the drawings, the thicknesses of layers, films, panels, regions, etc. may be exaggerated for clarity.

In addition, the expression “equal to or the same as” in the description may mean “substantially equal to or the same as”. That is, it may be the same enough to convince those skilled in the art to be the same. Even other expressions may be expressions from which “substantially” is omitted.

FIG. 1 illustrates a schematic view for explaining a display device according to an embodiment of the present disclosure.

Referring to FIG. 1 , a display device 10 according to an embodiment of the present disclosure may include a timing controller 11 , a data driver 12 , a scan driver 13 , a pixel unit 14 , and a display mode controller 15 .

The timing controller 11 may receive an external input signal from an external processor. The external input signal may include a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, RGB data, and the like. The vertical synchronization signal may include a plurality of pulses, and may indicate that a previous frame period ends and a current frame period begins based on a time point at which each pulse is generated. An interval between adjacent pulses of the vertical synchronization signal may correspond to one frame period. The horizontal synchronization signal may include a plurality of pulses, and may indicate that a previous horizontal period ends and a new horizontal period begins based on a time point at which each pulse is generated. An interval between adjacent pulses of the horizontal synchronization signal may correspond to one horizontal period. The data enable signal may indicate that the RGB data is supplied in the horizontal period. The RGB data may be supplied in units of pixel rows in the horizontal periods in response to the data enable signal. The RGB data corresponding to one frame may be referred to as one input image.

The display mode controller 15 may determine a first display mode or a second display mode based on an input image. The timing controller 11 may control scan signals of the scan driver 13 , depending on the determined display mode. For example, the timing controller 11 may control supply timing of scan signals of a turn-on level of the scan driver 13 , depending on the determined display mode. In some embodiments, the timing controller 11 may control grays to be supplied to the data driver 12 depending on the determined display mode.

The display mode controller 15 may be configured as an independent integrated chip (IC) or hardware that is separate from the timing controller 11 . In another embodiment, the display mode controller 15 may be configured as the same IC or hardware integrated with the timing controller 11 . In another embodiment, the display mode controller 15 may be configured as software of the timing controller 11 .

The data driver 12 may provide data voltages corresponding to grays of the input images to the pixels. For example, the data driver 12 may sample grays by using a clock signal and apply data voltages corresponding to the grays to the data output lines DL 1 to DLn in units of scan lines, wherein “n” may be an integer larger than zero.

The scan driver 13 may receive a clock signal, a scan start signal, and the like from the timing controller 11 to generate scan signals to be provided to scan lines (SL 1 , SL 2 , SL 3 , . . . , SLm), wherein “m” may be an integer larger than zero.

The pixel unit 14 includes dots. Each dot may include at least two pixels of different colors. The dot may be a display unit for displaying a combined color. For example, an external processor may provide grays in dot units. Each pixel PXij may be connected to a corresponding data line and scan line, wherein i and j may be integers larger than zero. For example, a pixel PXij may mean a pixel in which a scan transistor is connected to an i-th scan line and a j-th data line.

Although not shown, the display device 10 may further include an emission driver. The emission driver may receive a clock signal, an emission stop signal, and the like from the timing controller 11 to generate emission signals to provide to emission lines. For example, the emission driver may include emission stages connected to the emission lines. The emission stages may be configured in a form of a shift register. For example, a first emission stage may generate an emission signal of a turn-off level based on the emission stop signal of a turn-off level, and the remaining emission stages may sequentially generate emission signals of a turn-off level based on an emission signal of a turn-off level of a previous emission stage.

When the display device 10 includes the above-described emission driver, each pixel PXij further includes a transistor connected to the emission line. This transistor may be turned off during a data writing period of each pixel PXij to prevent light emitting of the pixel PXij. Hereinafter, it will be assumed and described that the emission driver is not provided.

FIG. 2 illustrates a schematic view for explaining a pixel according to an embodiment of the present disclosure.

A gate electrode of a first transistor T 1 may be connected to an i-th scan line SLi, a first electrode thereof may be connected to a j-th data line DLj, and a second electrode thereof may be connected to a second electrode of a storage capacitor Cst. The first transistor T 1 may be referred to as a scan transistor.

A gate electrode of a second transistor T 2 may be connected to the second electrode of the first transistor T 1 , a first electrode thereof may be connected to a first power line ELVDDL, and a second electrode thereof may be connected to the anode of a light emitting diode LD. The second transistor T 2 may be referred to as a driving transistor.

A first electrode of the storage capacitor Cst may be connected to the first power line ELVDDL, and the second electrode thereof may be connected to the gate electrode of the second transistor T 2 and the second electrode of the first transistor T 1 simultaneously.

The anode of the light emitting diode LD may be connected to the second electrode of the second transistor T 2 , and a cathode thereof may be connected to a second power line ELVSSL. During a light emitting period of the light emitting diode LD, a first power voltage applied to the first power line ELVDDL may be greater than a second power voltage applied to the second power line ELVSSL.

Here, the transistors T 1 and T 2 are illustrated as P-type transistors, but those skilled in the art may replace at least one of the transistors with an N-type transistor by inverting a phase of a signal.

When a scan signal having a turn-on level (here, a logic low level) is applied through the scan line SLi, the first transistor T 1 is turned on. In this case, a data voltage applied to the data line DLj is stored in the storage capacitor Cst.

A driving current, which corresponds to a voltage difference between the first electrode and the second electrode of the storage capacitor Cst, flows between the first electrode and the second electrode of the second transistor T 2 . Thus, the light emitting diode LD emits light with luminance corresponding to the data voltage.

Next, when a scan signal of a turn-off level (here, a logic high level) is applied through the scan line SLi, the first transistor T 1 is turned off, and the data line DLj and the second electrode of the storage capacitor Cst are electrically separated. Therefore, even if the data voltage of the data line DLj is changed, the voltage stored in the second electrode of the storage capacitor Cst is not changed.

The embodiments of the present disclosure may be applied not only to the pixel PXij of FIG. 2 , but also to a pixel having another pixel circuit according to the conventional art.

FIG. 3 illustrates a schematic view for explaining a scan driver according to an embodiment of the present disclosure.

The scan driver 13 may include first stages (ST 1 , ST 3 , . . . ) connected to the first scan lines (SL 1 , SL 3 , . . . ) and second stages (ST 2 , ST 4 , . . . ) connected to the second scan lines (SL 2 , SL 4 , . . . ).

The first scan lines (SL 1 , SL 3 , . . . ) may be connected to the first dots. For example, the first scan lines (SL 1 , SL 3 , . . . ) may be odd-numbered scan lines. For example, the first stages (ST 1 , ST 3 , . . . ) may be odd-numbered stages.

The second scan lines (SL 2 , SL 4 , . . . ) may be connected to the second dots. For example, the second scan lines (SL 2 , SL 4 , . . . ) may be even-numbered scan lines. For example, the second stages (ST 2 , ST 4 , . . . ) may be even-numbered stages.

Each of the stages ST 1 , ST 2 , ST 3 , and ST 4 may include a first input terminal 1001 , a second input terminal 1002 , a third input terminal 1003 , and an output terminal 1004 . The first start stage ST 1 of the first stages (ST 1 , ST 3 , . . . ) and the second start stage ST 2 of the second stages (ST 2 , ST 4 , . . . ) may be connected to the same scan start line FLML. For example, the first input terminal 1001 of the first start stage ST 1 and the first input terminal 1001 of the second start stage ST 2 may be connected to the same scan start line FLML. The output terminal 1004 of the first start stage ST 1 may be connected to the first scan line SL 1 , and the output terminal 1004 of the second start stage ST 2 may be connected to the second scan line SL 2 .

Each of the first stages (ST 3 , . . . ) excluding the first start stage ST 1 may be connected to the first scan line of the previous first stage. Each of the second stages (ST 4 , . . . ) excluding the second start stage ST 2 may be connected to the second scan line of the previous second stage. For example, the first input terminal 1001 of the first stage ST 3 may be connected to the first scan line SL 1 of the first start stage ST 1 . In addition, the first input terminal 1001 of the second stage ST 4 may be connected to the second scan line SL 2 of the second start stage ST 2 .

The first stages (ST 1 , ST 3 , . . . ) may be connected to first clock lines CKL 1 and CKL 3 . The first clock lines CKL 1 and CKL 3 may be alternately connected to the second input terminal 1002 and the third input terminal 1003 of the first stages (ST 1 , ST 3 , . . . ). That is, the second input terminal 1002 of the first start stage ST 1 is connected to CKL 1 , and the third input terminal 1003 of the first start stage ST 1 is connected to CKL 3 . On the contrary, the second input terminal 1002 of the third start stage ST 3 is connected to CKL 3 , and the third input terminal 1003 of the third start stage ST 3 is connected to CKL 1 . The second stages (ST 2 , ST 4 , . . . ) may be connected to second clock lines CKL 2 and CKL 4 different from the first clock lines CKL 1 and CKL 3 . The second clock lines CKL 2 and CKL 4 may be alternately connected to the second input terminal 1002 and the third input terminal 1003 of the second stages (ST 2 , ST 4 , . . . ). That is, the second input terminal 1002 of the second start stage ST 2 is connected to CKL 2 , and the third input terminal 1003 of the second start stage ST 2 is connected to CKL 4 . On the contrary, the second input terminal 1002 of the fourth start stage ST 4 is connected to CKL 4 , and the third input terminal 1003 of the fourth start stage ST 4 is connected to CKL 2 .

Each of the stages ST 1 , ST 2 , ST 3 , and ST 4 may be connected to a power line VHPL and a power line VLPL. Here, a voltage of the power line VHPL may be set to a turn-off level (gate-off voltage, logic high level). In addition, a voltage of the power line VLPL may be set to a turn-on level (gate-on voltage, logic low level).

In the embodiment of FIG. 3 , the first start stage ST 1 and the second start stage ST 2 are connected to the same scan start line FLML, but in some embodiments, the first start stage ST 1 and the second start stage ST 2 may also be connected to different scan start lines from each other. Even when the first start stage ST 1 and the second start stage ST 2 are connected to different scan start lines, a driving method thereof may be the same as that of the embodiment of FIG. 3 , so that a redundant description will be omitted below.

FIG. 4 illustrates a schematic view for explaining a stage according to an embodiment of the present disclosure.

For better understanding and ease of description, FIG. 4 illustrates the first start stage ST 1 and the second start stage ST 2 . Referring to FIG. 4 , the first start stage ST 1 may include a first driver 1210 , a second driver 1220 , and an output portion (buffer) 1230 .

The output portion 1230 controls a voltage supplied to the output terminal 1004 in response to voltages of a node NP 1 and a node NP 2 . To this end, the output portion 1230 includes a transistor M 5 and a transistor M 6 .

The transistor M 5 is disposed between the power line VHPL and the output terminal 1004 , and a gate electrode thereof is connected to the node NP 1 . The transistor M 5 controls connection between the power line VHPL and the output terminal 1004 in response to a voltage applied to the node NP 1 .

The transistor M 6 is disposed between the output terminal 1004 and the third input terminal 1003 , and a gate electrode thereof is connected to the node NP 2 . The transistor M 6 controls connection between the output terminal 1004 and the third input terminal 1003 in response to a voltage applied to the node NP 2 . The output unit 1230 is driven as a buffer. Additionally, the transistors M 5 and M 6 may be configured by connecting a plurality of transistors in parallel.

The first driver 1210 controls a voltage of the node NP 3 in response to signals supplied to the first input terminal 1001 to the third input terminal 1003 . To this end, the first driver 1210 includes transistors M 2 , M 3 , and M 4 .

The transistor M 2 is disposed between the first input terminal 1001 and the node NP 3 , and a gate electrode thereof is connected to the second input terminal 1002 . The transistor M 2 controls connection between the first input terminal 1001 and the node NP 3 in response to a signal supplied to the second input terminal 1002 .

The transistor M 3 and the transistor M 4 are connected in series and disposed between the node NP 3 and power line VHPL. The transistor M 3 is disposed between the transistor M 4 and the node NP 3 , and a gate electrode thereof is connected to the third input terminal 1003 . The transistor M 3 controls connection between the transistor M 4 and the node NP 3 in response to a signal supplied to the third input terminal 1003 .

The transistor M 4 is disposed between the transistor M 3 and the power line VHPL, and the gate electrode thereof is connected to the node NP 1 . The transistor M 4 controls connection between the transistor M 3 and the power line VHPL in response to a voltage of the node NP 1 .

The second driver 1220 controls a voltage of the node NP 1 in response to voltages of the second input terminal 1002 and the node NP 3 . To this end, the second driver 1220 includes a transistor M 1 , a transistor M 7 , a transistor M 8 , a capacitor CP 1 , and a capacitor CP 2 .

The capacitor CP 1 is connected between the node NP 2 and the output terminal 1004 . The capacitor CP 1 is charged with a voltage corresponding to the turn-on and turn-off of the transistor M 6 .

The capacitor CP 2 is connected between the node NP 1 and the power line VHPL. The capacitor CP 2 is charged with a voltage applied to the node NP 1 .

The transistor M 7 is disposed between the node NP 1 and the second input terminal 1002 , and a gate electrode thereof is connected to the node NP 2 . The transistor M 7 controls connection between the node NP 1 and the second input terminal 1002 in response to a voltage of the node NP 3 .

The transistor M 8 is disposed between the node NP 1 and the power line VLPL, and a gate electrode thereof is connected to the second input terminal 1002 . The transistor M 8 controls connection between the node NP 1 and the power line VLPL in response to a signal of the second input terminal 1002 .

The transistor M 1 is disposed between the node NP 3 and the node NP 2 , and a gate electrode thereof is connected to the power line VLPL. The transistor M 1 maintains an electrical connection between the node NP 3 and the node NP 2 while maintaining a turn-on state. Additionally, the transistor M 1 limits a voltage drop width of the node NP 3 in response to a voltage of the node NP 2 . In other words, even if a voltage of the node NP 2 drops to a voltage lower than that of the power line VLPL, a voltage of the node NP 3 is not lower than a voltage obtained by subtracting a threshold voltage of the transistor M 1 from the voltage the power line VLPL.

FIG. 5 illustrates a schematic view for explaining a driving method of a scan driver according to an embodiment of the present disclosure. In FIG. 5 , for better comprehension and ease of description, an operation process will be described using the first start stage ST 1 .

Referring to FIG. 5 , a first clock signal CK 1 and a third clock signal CK 3 have a period of 4 horizontal periods (4H), and are supplied in different horizontal periods. In other words, the first clock signal CK 3 is set as a signal shifted by half a period (that is, 2 horizontal periods) from the first clock signal CK 1 . In addition, the scan start signal FLM supplied to the first input terminal 1001 may be supplied in synchronization with the first clock signal CK 1 supplied to the second input terminal 1002 . One horizontal period (1H) may correspond to a period of pulses of a horizontal synchronization signal Hsync.

Supply of specific signals may mean that specific signals have a turn-on level (here, a logic low level). Stopping the supply of specific signals may mean that the specific signals have a turn-off level (here, a logic high level).

Additionally, when the scan start signal FLM is supplied, the first input terminal 1001 may be set to a voltage of the logic low level, and when the scan start signal FLM is not supplied, the first input terminal 1001 may be set to a voltage of the logic high level. In addition, when a clock signal is supplied to the second input terminal 1002 and the third input terminal 1003 , the second input terminal 1002 and the third input terminal 1003 may be set to a voltage of the logic low level, and when the clock signal is not supplied thereto, the second input terminal 1002 and the third input terminal 1003 may be set to a voltage of the logic high level,

When the operation process is described in detail, the scan start signal FLM is first supplied to be synchronized with the first clock signal CK 1 .

When the first clock signal CK 1 is supplied, the transistors M 2 and M 8 are turned on. When the transistor M 2 is turned on, the first input terminal 1001 and the node NP 3 are electrically connected. Here, since the transistor M 1 is turned on in most of the period, the node NP 2 maintains an electrical connection with the node NP 3 .

When the first input terminal 1001 and the node NP 3 are electrically connected, voltages VNP 2 and VNP 3 of the nodes NP 3 and NP 2 are set to the low levels by the scan start signal FLM supplied to the first input terminal 1001 . When the voltages VNP 2 and VNP 3 of the nodes NP 3 and NP 2 are set to the low levels, the transistors M 6 and M 7 are turned on.

When the transistor M 6 is turned on, the third input terminal 1003 and the output terminal 1004 are electrically connected. Here, the third input terminal 1003 is set to the high-level voltage (that is, the first clock signal CK 3 is not supplied), and accordingly, the high-level voltage is also outputted to the output terminal 1004 . When the transistor M 7 is turned on, the second input terminal 1002 and the node NP 1 are electrically connected. According to the first clock signal CK 1 supplied to the second input terminal 1002 , the voltage VNP 1 of the node NP 1 is set to the low level.

Additionally, when the first clock signal CK 1 is supplied, the transistor M 8 is turned on. When the transistor M 8 is turned on, the voltage of the power line VLPL is supplied to the node NP 1 . Here, the voltage of the power line VLPL is set to the same (or similar) voltage as the low level of the first clock signal CK 1 , and accordingly, the node NP 1 stably maintains the low level voltage.

When the node NP 1 is set to the low-level voltage, the transistor M 4 and the transistor M 5 are turned on. When the transistor M 4 is turned on, the power line VHPL and the transistor M 3 are electrically connected. Here, since the transistor M 3 is set to the turn-off state, the node NP 3 stably maintains the low-level voltage even when the transistor M 4 is turned on. When the transistor M 5 is turned on, the voltage of the power line VHPL is supplied to the output terminal 1004 . Here, the voltage of the power line VHPL is set to the same (or similar) voltage as the high level voltage supplied to the third input terminal 1003 , and accordingly, the output terminal 1004 stably maintains the high level voltage.

Thereafter, the supply of the scan start signal FLM and the first clock signal CK 1 is stopped. When the supply of the first clock signal CK 1 is stopped, the transistors M 2 and M 8 are turned off. In this case, the transistor M 6 and the transistor M 7 maintain a turn-on state in response to a voltage stored in the capacitor CP 1 . That is, the node NP 2 and the node NP 3 maintain the low level voltage by the voltage stored in the capacitor CP 1 .

When the transistor M 6 maintains the turn-on state, the output terminal 1004 and the third input terminal 1003 maintain their electrical connection. When the transistor M 7 maintains the turn-on state, the node NP 1 maintains an electrical connection with the second input terminal 1002 . Here, the voltage of the second input terminal 1002 is set to the high level voltage in response to stopping of the supply of the first clock signal CK 1 , and accordingly, the voltage VNP 1 of the node NP 1 is also set to the high level voltage. When the high-level voltage is supplied to the node NP 1 , the transistors M 4 and M 5 are turned off.

Thereafter, the first clock signal CK 3 is supplied to the third input terminal 1003 . In this case, since the transistor M 6 is set to the turn-on state, the first clock signal CK 3 supplied to the third input terminal 1003 is supplied to the output terminal 1004 . In this case, the output terminal 1004 outputs the first clock signal CK 3 as a scan signal SS 1 of a turn-on level to the first scan line SL 1 .

Meanwhile, when the first clock signal CK 3 is supplied to the output terminal 1004 , the voltage of the node NP 2 is lowered to a voltage lower than that of the power line VLPL due to coupling of the capacitor CP 1 , and accordingly, the transistor M 6 stably maintains the turn-on state.

Meanwhile, even if the voltage of the node NP 2 is lowered, the node NP 3 may approximately maintain the voltage of the power line VLPL (for example, a voltage obtained by subtracting a threshold voltage of the transistor M 1 from the voltage of the power line VLPL) by the transistor M 1 .

After the first scan signal SS 1 of the turn-on level is outputted to the first scan line SL 1 , the supply of the first clock signal CK 3 is stopped. When the supply of the first clock signal CK 3 is stopped, the output terminal 1004 outputs the high level voltage. In addition, the voltage VNP 2 of the node NP 2 increases to approximately the voltage of the power line VLPL in response to the high level voltage of the output terminal 1004 .

Thereafter, the first clock signal CK 1 is supplied. When the first clock signal CK 1 is supplied, the transistors M 2 and M 8 are turned on. When the transistor M 2 is turned on, the first input terminal 1001 and the node NP 3 are electrically connected. In this case, the scan start signal FLM is not supplied to the first input terminal 1001 , and accordingly, the node NP 3 is set to the high level voltage. Therefore, the high level voltage is supplied to the node NP 3 and the node NP 2 , and accordingly, the transistor M 6 and the transistor M 7 are turned off.

When the transistor M 8 is turned on, the voltage of the power line VLPL is supplied to the node NP 1 , and accordingly, the transistors M 4 and M 5 are turned on. When the transistor M 5 is turned on, the voltage of the power line VHPL is supplied to the output terminal 1004 . Thereafter, the transistor M 4 and the transistor M 5 maintain the turn-on state corresponding to the voltage charged in the capacitor CP 2 , and accordingly, the output terminal 1004 stably receives the voltage of the power line VHPL.

Additionally, when the first clock signal CK 3 is supplied, the transistor M 3 is turned on. At this time, since the transistor M 4 is set to the turn-on state, the voltage of the power line VHPL is supplied to the node NP 3 and the node NP 2 . In this case, the transistors M 6 and M 7 are stably maintained in the turn-off state.

The first stage ST 3 receives the output signal (that is, a scanning signal) of the first stage ST 1 so as to be synchronized with the first clock signal CK 3 . In this case, the first stage ST 3 outputs a first scan signal SS 3 of the turn-on level to the first scan line SL 3 so as to be synchronized with the first clock signal CK 1 . The first stages (ST 1 , ST 3 , . . . ) sequentially output the turn-on level scan signal to the first scan lines (SL 1 , SL 3 , . . . ) while repeating the above-described process.

The description of the first stages (ST 1 , ST 3 , . . . ) in FIG. 4 and FIG. 5 may be substantially equally applied to the second stages (ST 2 , ST 4 , . . . ). The stages and the driving method thereof of FIG. 4 and FIG. 5 are one example, and other conventional stages and driving methods may be used to configure embodiments of the present disclosure.

FIGS. 6, 7, 8, and 9 illustrate schematic views for explaining a first frame period and a second frame period according to an embodiment of the present disclosure.

The display device 10 may operate in a first display mode including a plurality of first frame periods FP 1 , or may operate in a second display mode including a plurality of second frame periods FP 2 . The second frame period FP 2 may be longer than the first frame period FP 1 . For example, the second frame period FP 2 may be an integer multiple of the first frame period FP 1 . For example, the second frame period FP 2 may be 2p times the first frame period FP 1 , and p may be an integer larger than 0. In the embodiment of FIG. 6 , the second frame period FP 2 is twice the first frame period FP 1 .

The first display mode is suitable for displaying a moving picture by displaying input images (frames) at a high frequency, and the second display mode is suitable for displaying a still image by displaying the input images at a low frequency. When a still image is detected while displaying a moving picture, the display device 10 may switch from the first display mode to the second display mode. In addition, when a moving picture is detected while displaying a still image, the display device 10 may switch from the second display mode to the first display mode.

Referring to FIG. 6 , for convenience of description, the j-th data line DLj and the pixels PX 1 j and PX 2 j will be mainly described. The example first pixel PX 1 j is connected to the j-th data line and the first scan line SL 1 . The first pixel PX 1 j is included in the first dot. The example second pixel PX 2 j is connected to the j-th data line and the second scan line SL 2 . The second pixel PX 2 j is included in the second dot.

In each first frame period FP 1 , the data driver 12 may sequentially apply data voltages corresponding to scan lines to data lines. For example, the data driver 12 may sequentially apply data voltages (DT 1 , DT 2 , . . . , DT(m−1), DTm) to the j-th data line DLj. Assuming that the first frame period FP 1 is 1/60 second, the first data voltage DT 1 may be supplied to the first pixel PX 1 j at 60 Hz. Accordingly, the first pixel PX 1 j emits light with a highest luminance at a time point at which the first data voltage DT 1 is applied, and then luminance may gradually decrease due to a leakage current. Referring to FIG. 6 , a luminance waveform of the first pixel PX 1 j corresponding to the plurality of first frame periods FP 1 is illustrated as an example.

Each second frame period FP 2 may include a first sub-frame period SFP 1 and a second sub-frame period SFP 2 . Lengths of the first sub-frame period SFP 1 and the second sub-frame period SFP 2 may be the same. For example, assuming that the second frame period FP 2 is 1/30 second, each of the first sub-frame period SFP 1 and the second sub-frame period SFP 2 may be 1/60 second.

In each first sub-frame period SFP 1 , the data driver 12 may sequentially apply data voltages corresponding to the first dots to data lines. For example, the data driver 12 may sequentially apply data voltages (DT 1 , DT 3 , . . . , DT(m−1)) to the j-th data line DLj. In each second sub-frame period SFP 2 , the data driver 12 may sequentially apply data voltages corresponding to the second dots to data lines. For example, the data driver 12 may sequentially apply data voltages (DT 2 , DT 4 , . . . , DTm) to the j-th data line DLj.

Accordingly, the first data voltage DT 1 may be supplied to the first pixel PX 1 j at 30 Hz. Accordingly, the first pixel PX 1 j emits light with a highest luminance at a time point at which the first data voltage DT 1 is applied, and then luminance may gradually decrease due to a leakage current. Referring to FIG. 6 , a luminance waveform of the first pixel PX 1 j corresponding to the plurality of second frame periods FP 2 is illustrated as an example. In addition, the second data voltage DT 2 may be applied to the second pixel PX 2 j at 30 Hz. Accordingly, the second pixel PX 2 j emits light with a highest luminance at a time point at which the second data voltage DT 2 is applied, and then luminance may gradually decrease due to a leakage current. Referring to FIG. 6 , a luminance waveform of the second pixel PX 2 j corresponding to the plurality of second frame periods FP 2 is illustrated as an example.

In this case, since the first pixel PX 1 j and the second pixel PX 2 j are positioned to be adjacent to each other, the first data voltage DT 1 and the second data voltage DT 2 in a typical input image may be substantially the same or similar.

Since a point of time at which the first pixel PX 1 j has the highest luminance and a point of time at which the second pixel PX 2 j has the highest luminance are alternately positioned, a user may recognize an average luminance waveform AVG of the first pixel PX 1 j and the second pixel PX 2 j as 60 Hz. Therefore, even when the first display mode and the second display mode are switched, it is possible to prevent a flicker due to a difference in the luminance waveform from being viewed.

Referring to FIG. 7 , control signals in the first frame period FP 1 are exemplarily illustrated.

During the first frame period FP 1 , the timing controller 11 may apply the first clock signals CK 1 and CK 3 of the turn-on level to the first clock lines CKL 1 and CKL 3 , and may apply the second clock signals CK 2 and CK 4 of the turn-on level to the second clock lines CKL 2 and CKL 4 . The first clock signals CK 1 and CK 3 and the second clock signals CK 2 and CK 4 may have different phases. For example, the clock signals CK 1 , CK 2 , CK 3 , and CK 4 of the turn-on level may be sequentially supplied in the order of the first clock line CKL 1 , the second clock line CKL 2 , the first clock line CKL 3 , and the second clock line CKL 4 . For example, each period of the clock signals CK 1 , CK 2 , CK 3 , and CK 4 of the turn-on level may be 4 horizontal periods.

In addition, the timing controller 11 may apply the scan start signal FLM of the turn-on level to the scan start line FLML. In this case, a length of the scan start signal FLM of the turn-on level may be set to overlap the first clock signal CK 1 of the turn-on level and the second clock signal CK 2 of the turn-on level. For example, the length of the scan start signal FLM of the turn-on level may be 2 horizontal periods.

During the first frame period FP 1 , the scan driver 13 may alternately apply the scan signals (SS 1 , SS 2 , SS 3 , SS 4 , . . . ) of the turn-on level to the first scan lines (SL 1 , SL 3 , . . . ) and the second scan lines (SL 2 , SL 4 , . . . ).

Referring to the driving method of FIG. 5 , the first scan signal SS 1 of the turn-on level may be generated corresponding to the first clock signal CK 3 of the turn-on level. In addition, the second scan signal SS 2 of the turn-on level may be generated corresponding to the second clock signal CK 4 of the turn-on level. Similarly, the first scan signal SS 3 of the turn-on level may be generated corresponding to the first clock signal CK 1 of the turn-on level. In addition, the second scan signal SS 4 of the turn-on level may be generated corresponding to the second clock signal CK 2 of the turn-on level.

The data driver 12 may supply data voltages to synchronize with respective scan signals (SS 1 , SS 2 , SS 3 , SS 4 , . . . ) of the turn-on level. For example, the data driver 12 may supply the data voltages in the current horizontal period corresponding to grays latched by a data enable signal DE of the logic high level of the previous horizontal period.

Referring to FIG. 8 , control signals in the first sub-frame period SFP 1 of the second frame period FP 2 are exemplarily shown.

During the first frame period SFP 1 , the timing controller 11 may apply the first clock signals CK 1 and CK 3 of the turn-on level to the first clock lines CKL 1 and CKL 3 , and may maintain the second clock signals CK 2 and CK 4 of the turn-off level to the second clock lines CKL 2 and CKL 4 . In the first frame period FP 1 and the first sub-frame period SFP 1 , periods of applying the first clock signals (CK 1 , CK 3 . . . ) of the turn-on level to the first clock lines (CKL 1 , CKL 3 . . . ) may be the same. For example, each period of the first clock signals CK 1 and CK 3 of the turn-on level may be 4 horizontal periods.

In addition, the timing controller 11 may apply the scan start signal FLM of the turn-on level to the scan start line FLML. In this case, a length of the scan start signal FLM of the turn-on level may be set to overlap the first clock signal CK 1 of the turn-on level. For example, the length of the scan start signal FLM of the turn-on level may be 2 horizontal periods as shown, but may be set to 1 horizontal period.

During the first sub-frame period SFP 1 , the scan driver 13 may apply the first scan signals (SS 1 , SS 3 , . . . ) of the turn-on level to the first scan lines (SL 1 , SL 3 , . . . ), and may maintain the second scan signals (SS 2 , SS 4 , . . . ) of the turn-off level to the second scan lines (SL 2 , SL 4 , . . . ). In the first frame period FP 1 and the first sub-frame period SFP 1 , periods of applying the first scan signals (SS 1 , SS 3 , . . . ) of the turn-on level to the first scan lines (SL 1 , SL 3 , . . . ) may be the same.

The data driver 12 may supply data voltages to synchronize with respective first scan signals (SS 1 , SS 3 , . . . ) of the turn-on level. In this case, since it is not necessary to supply data voltages to be synchronized with the second scan signals (SS 2 , SS 4 , . . . ), the period of the data enable signal DE of the turn-on level in the first sub-frame period SFP 1 may be longer than that of the data enable signal DE of the turn-on level in the first frame period FP 1 . Accordingly, since the period in which the data driver 12 changes the data voltages increases, there is an advantage that the dynamic power required by the data driver 12 decreases.

Referring to FIG. 9 , control signals in the second sub-frame period SFP 2 of the second frame period FP 2 are shown as an example.

During the second sub-frame period SFP 2 , the second clock signals CK 2 and CK 4 of the turn-on level may be applied to the second clock lines CKL 2 and CKL 4 and the first clock signals CK 1 and CK 3 of the turn-off level may be maintained to the first clock lines CKL 1 and CKL 3 . In the first frame period FP 1 and the second sub-frame period SFP 2 , periods of applying the second clock signals (CK 2 , CK 4 . . . ) of the turn-on level to the second clock lines (CKL 2 , CKL 4 . . . ) may be the same. For example, each period of the second clock signals CK 2 and CK 4 of the turn-on level may be 4 horizontal periods.

In addition, the timing controller 11 may apply the scan start signal FLM of the turn-on level to the scan start line FLML. In this case, a length of the scan start signal FLM of the turn-on level may be set to overlap the second clock signal CK 2 of the turn-on level. For example, the length of the scan start signal FLM of the turn-on level may be 2 horizontal periods as shown, but may be set to 1 horizontal period.

During the second sub-frame period SFP 2 , the scan driver 13 may apply the second scan signals (SS 2 , SS 4 , . . . ) of the turn-on level to the second scan lines (SL 2 , SL 4 , . . . ), and may maintain the first scan signals (SS 1 , SS 3 , . . . ) of the turn-off level to the first scan lines (SL 1 , SL 3 , . . . ). In the first frame period FP 1 and the second sub-frame period SFP 2 , periods of applying the second scan signals (SS 2 , SS 4 , . . . ) of the turn-on level to the second scan lines (SL 2 , SL 4 , . . . ) may be the same.

The data driver 12 may supply data voltages to synchronize with respective second scan signals (SS 2 , SS 4 , . . . ) of the turn-on level. In this case, since it is not necessary to supply data voltages to be synchronized with the first scan signals (SS 1 , SS 3 , . . . ), the period of the data enable signal DE of the turn-on level in the second sub-frame period SFP 2 may be longer than that of the data enable signal DE of the turn-on level in the first frame period FP 1 . Accordingly, since the period in which the data driver 12 changes the data voltages increases, there is an advantage that the dynamic power required by the data driver 12 decreases.

FIGS. 10, 11, 12, and 13 illustrate schematic views for explaining a first frame period and a second frame period according to another embodiment of the present disclosure.

In the embodiment of FIG. 10 , a luminance waveform and a driving method of the first pixel PX 1 j in the first frame period FP 1 are the same as those of FIG. 6 . In addition, in the embodiment of FIG. 10 , individual luminance waveforms and an average luminance waveform AVG of the first and second pixels PX 1 j and PX 2 j in a second frame period FP 2 ′ are substantially the same as those of FIG. 6 .

However, the driving method of the second frame period FP 2 ′ of the embodiment of FIG. 10 is different from that of the embodiment of FIG. 6 in that each of a first sub-frame period SFP 1 ′ and a second sub-frame period SFP 2 ′ includes a data blank period BPC. For example, a length of each of the first sub-frame period SFP 1 ′ and the second sub-frame period SFP 2 ′ may be the same as that of each of the first sub-frame period SFP 1 and the second sub-frame period SFP 2 , and the data driver 12 of the embodiment of FIG. 10 may supply data voltages with a shorter period than that of FIG. 6 . The data blank period BPC may be a remaining period after the data driver 12 completes supplying the data voltages in each of the first sub frame period SFP 1 ′ and the second sub frame period SFP 2 ′. During the data blank period BPC, all or at least a portion (a gamma amp or digital logic) of the data driver 12 is powered off, so that power consumption may be reduced.

Referring to FIG. 11 , control signals in the first sub-frame period SFP 1 ′ of the second frame period FP 2 ′ are exemplarily shown. Specifically, FIG. 11 shows control signals in a period excluding the data blank period BPC of the first sub-frame period SFP 1 ′.

During the first-sub frame period SFP 1 ′, the timing controller 11 may apply the first clock signals CK 1 and CK 3 of the turn-on level to the first clock lines CKL 1 and CKL 3 , and may maintain the second clock signals CK 2 and CK 4 of the turn-off level to the second clock lines CKL 2 and CKL 4 . In the present embodiment, a cycle of applying the first clock signals CK 1 and CK 3 of the turn-on level to the first clock lines CKL 1 and CKL 3 in the first sub-frame period SFP 1 ′ may be shorter than a cycle of applying the first clock signals CK 1 and CK 3 of the turn-on level in the first frame period FP 1 .

For example, each period of the first clock signals CK 1 and CK 3 of the turn-on level may be 2 horizontal periods.

The timing controller 11 may apply the scan start signal FLM of the turn-on level to the scan start line FLML. In this case, a length of the scan start signal FLM of the turn-on level may be set to overlap the first clock signal CK 1 of the turn-on level. For example, the length of the scan start signal FLM of the turn-on level may be set to 1 horizontal period.

During the first sub-frame period SFP 1 ′, the scan driver 13 may apply the first scan signals (SS 1 , SS 3 , . . . ) of the turn-on level to the first scan lines (SL 1 , SL 3 , . . . ), and may maintain the second scan signals (SS 2 , SS 4 , . . . ) of the turn-off level to the second scan lines (SL 2 , SL 4 , . . . ). A cycle of applying the first scan signals (SS 1 , SS 3 , . . . ) of the turn-on level to the first scan lines (SL 1 , SL 3 , . . . ) in the first sub-frame period SFP 1 ′ may be shorter than a cycle of applying the first scan signals (SS 1 , SS 3 , . . . ) of the turn-on level in the first frame period FP 1 .

The data driver 12 may supply data voltages to synchronize with respective first scan signals (SS 1 , SS 3 , . . . ) of the turn-on level.

Referring to FIG. 12 , control signals in the data blank period BPC of the second frame period FP 2 ′ are exemplarily shown. In the data blank period BPC, the clock signals CK 1 , CK 2 , CK 3 , and CK 4 of the turn-off level, the scan signals (SS 1 , SS 2 , SS 3 , SS 4 , . . . ) of the turn-off level, and the scan start signal FLM of the turn-off level may be maintained.

As described above, during the data blank period BPC, all or at least a portion (a gamma amp or digital logic) of the data driver 12 is powered off, so that power consumption may be reduced.

Referring to FIG. 13 , control signals in the second sub-frame period SFP 2 ′ of the second frame period FP 2 ′ are exemplarily shown. Specifically, FIG. 13 shows control signals in a period excluding the data blank period BPC of the second sub-frame period SFP 2 ′.

During the second sub-frame period SFP 2 ′, the second clock signals CK 2 and CK 4 of the turn-on level may be applied to the second clock lines CKL 2 and CKL 4 and the first clock signals CK 1 and CK 3 of the turn-off level may be maintained to the first clock lines CKL 1 and CKL 3 . A period of applying the first clock signals CK 2 and CK 4 of the turn-on level to the second clock lines CKL 2 and CKL 4 in the second sub-frame period SFP 2 ′ may be shorter than a period of applying the second clock signals CK 2 and CK 4 of the turn-on level in the first frame period FP 1 . For example, each period of the second clock signals CK 2 and CK 4 of the turn-on level may be 2 horizontal periods.

In addition, the timing controller 11 may apply the scan start signal FLM of the turn-on level to the scan start line FLML. In this case, a length of the scan start signal FLM of the turn-on level may be set to overlap the second clock signal CK 2 of the turn-on level. For example, the length of the scan start signal FLM of the turn-on level may be set to 1 horizontal period.

During the second sub-frame period SFP 2 ′, the scan driver 13 may apply the second scan signals (SS 2 , SS 4 , . . . ) of the turn-on level to the second scan lines (SL 2 , SL 4 , . . . ), and may maintain the first scan signals (SS 1 , SS 3 , . . . ) of the turn-off level to the first scan lines (SL 1 , SL 3 , . . . ). A period of applying the second scan signals (SS 2 , SS 4 , . . . ) of the turn-on level to the second scan lines (SL 2 , SL 4 , . . . ) in the second sub-frame period SFP 2 ′ may be shorter than a period of applying the second scan signals (SS 2 , SS 4 , . . . ) of the turn-on level in the first frame period FP 1 .

The data driver 12 may supply data voltages to synchronize with respective second scan signals (SS 2 , SS 4 , . . . ) of the turn-on level.

FIG. 14 illustrates a schematic view for explaining a first frame period and a second frame period according to another embodiment of the present disclosure.

In the embodiment of FIG. 14 , a luminance waveform and a driving method of the first pixel PX 1 j in the first frame period FP 1 are the same as those of FIG. 6 .

The driving method of the second frame period FP 2 ″ of FIG. 14 is similar to that of FIG. 10 , but they are different in that each second frame period FP 2 ″ includes four sub-frame periods SFP 1 ″, SFP 2 ″, SFP 3 ″, and SFP 4 ″. For example, the second frame period FP 2 ″ is four times the first frame period FP 1 , and thus may be 1/15 second. For example, each of the sub-frame periods SFP 1 ″, SFP 2 ″, SFP 3 ″, and SFP 4 ″ may be 1/60 second.

In the embodiment of FIG. 10 , two dots form a group, but in the embodiment of FIG. 14 , there is a difference in that four adjacent dots form one group. The first pixel PX 1 j in the first dot may receive a data voltage SF 1 D in the first sub-frame period SFP 1 ″, and may emit light with the highest luminance. The second pixel PX 2 j in the second dot may receive a data voltage SF 2 D in the second sub-frame period SFP 2 ″, and may emit light with the highest luminance. A third pixel PX 3 j in a third dot may receive a data voltage SF 3 D in the third sub-frame period SFP 3 ″, and may emit light with the highest luminance. A fourth pixel PX 4 j in a fourth dot may receive a data voltage SF 4 D in the fourth sub-frame period SFP 4 ″, and may emit light with the highest luminance. Accordingly, even if each of the pixels PX 1 j , PX 2 j , PX 3 j , and PX 4 j emit light at 15 Hz, an average luminance waveform AVG of a group of pixels PX 1 j , PX 2 j , PX 3 j , and PX 4 j may be recognized as 60 Hz.

Referring to FIG. 10 and FIG. 14 , the number of sub-frame periods SFP 1 ″, SFP 2 , SFP 3 , and SFP 4 ″ included in the second frame period FP 2 ″ may be variously set.

FIG. 15 illustrates a schematic view for explaining a scan driver according to another embodiment of the present disclosure.

A scan driver 13 ″ of FIG. 15 is one in which the scan driver 13 of FIG. 3 is partially modified in order to apply the driving method of FIG. 14 . Internal circuit configurations of stages ST 1 , ST 2 , ST 3 , and ST 4 of the scan driver 13 ″ and the scan driver 13 may be the same.

However, unlike the scan driver 13 of FIG. 3 divided into two stage groups (odd-numbered stages and even-numbered stages), the scan driver 13 ″ of FIG. 15 may be divided into four stage groups. For example, a first stage group includes (4q+1)-th stages (ST 1 , . . . ), and each of the stages (ST 1 , . . . ) may be alternately connected to the clock lines CKL 1 and CKL 5 . In this case, q may be an integer larger than or equal to 0. That is, the second input terminal 1002 of the first start stage ST 1 is connected to CKL 1 , and the third input terminal 1003 of the first start stage ST 1 is connected to CKL 5 . A second stage group includes (4q+2)-th stages (ST 2 , . . . ), and each of the stages (ST 2 , . . . ) may be alternately connected to clock lines CKL 2 and CKL 6 . That is, the second input terminal 1002 of the second start stage ST 2 is connected to CKL 2 , and the third input terminal 1003 of the second start stage ST 2 is connected to CKL 6 . A third stage group includes (4q+3)-th stages (ST 3 , . . . ), and each of the stages (ST 3 , . . . ) may be alternately connected to clock lines CKL 3 and CKL 7 . That is, the second input terminal 1002 of the third start stage ST 3 is connected to CKL 3 , and the third input terminal 1003 of the third start stage ST 3 is connected to CKL 7 . A fourth stage group includes (4q+4)-th stages (ST 4 , . . . ), and each of the stages (ST 4 , . . . ) may be alternately connected to clock lines CKL 4 and CKL 8 . That is, the second input terminal 1002 of the fourth start stage ST 4 is connected to CKL 4 , and the third input terminal 1003 of the fourth start stage ST 4 is connected to CKL 8 .

The first input terminal 1001 of each of the stages ST 1 , ST 2 , ST 3 , and ST 4 may be connected to the scan start line FLML. The driving method of the scan driver 13 ″ is similar to that of the scan driver 13 , so a repeated description will be omitted.

FIG. 16 illustrates a schematic view for explaining a pixel unit according to an embodiment of the present disclosure.

Referring to FIG. 16 , a pixel unit 14 having an RGB stripe structure is illustrated as an example.

Each of the dots (DT 11 , DT 12 , DT 13 , DT 14 , DT 21 , DT 22 , DT 23 , DT 24 , DT 31 , DT 32 , DT 33 , DT 34 , DT 41 , DT 42 , DT 43 , and DT 44 ) are a pixel of a first color, a pixel of a second color, and a pixel of a third color that are arranged in a first direction DR 1 . In this case, the first color, the second color, and the third color may be different from each other. For example, the first color may be red, the second color may be green, and the third color may be blue.

Here, the color of the pixel means the color when the light emitting diode LD of FIG. 2 emits light. In addition, the position of the pixel is described based on the position of the light emitting surface of the light emitting diode LD.

Each of the data lines (DL 1 , DL 2 , DL 3 , DL 4 , DL 5 , DL 6 , DL 7 , DL 8 , DL 9 , DL 10 , DL 11 , and DL 12 ) may be connected to pixels of a single color. For example, the data lines (DL 1 , DL 4 , DL 7 , and DL 10 ) may be respectively connected to red pixels (PX 11 , PX 21 , PX 31 , and PX 41 for DL 1 , PX 14 , PX 24 , PX 34 , and PX 44 for DL 4 , PX 17 , PX 27 , PX 37 , and PX 47 for DL 7 , and PX 110 , PX 210 , PX 310 , and PX 410 for DL 10 ). In addition, the data lines (DL 2 , DL 5 , DL 8 , and DL 11 ) may be respectively connected to green pixels (PX 12 , PX 22 , PX 32 , and PX 42 for DL 2 , PX 15 , PX 25 , PX 35 , and PX 45 for DL 5 , PX 18 , PX 28 , PX 38 , and PX 48 for DL 8 , and PX 111 , PX 211 , PX 311 , and PX 411 for DL 11 ). In addition, the data lines (DL 3 , DL 6 , DL 9 , and DL 12 ) may be respectively connected to blue pixels (PX 13 , PX 23 , PX 33 , and PX 43 for DL 3 , PX 16 , PX 26 , PX 36 , and PX 46 for DL 6 , PX 19 , PX 29 , PX 39 , and PX 49 for DL 9 , and PX 112 , PX 212 , PX 312 , and PX 412 for DL 12 ).

Dots (DT 11 to DT 14 and DT 31 to DT 34 ) connected to the first scan lines SL 1 and SL 3 alternate with dots (DT 21 to DT 24 and DT 41 to DT 44 ) connected to the second scan lines SL 2 and SL 4 in a second direction DR 2 . In the embodiment of FIG. 16 , the dots connected to the first scan lines SL 1 and SL 3 do not alternate with the dots connected to the second scan lines SL 2 and SL 4 in the first direction DR 1 . The first direction DR 1 and the second direction DR 2 may be orthogonal. However, in another embodiment, the first direction DR 1 and the second direction DR 2 may not be orthogonal.

Pixels connected to the same scan line may be referred to as one pixel row. For example, a first pixel row may indicate pixels PX 11 to PX 112 connected to the first scan line SL 1 along the first direction DR 1 , a second pixel row may indicate pixels PX 21 to PX 212 connected to the second scan line SL 2 along the first direction DR 1 , a third pixel row may indicate pixels PX 31 to PX 312 connected to the first scan line SL 3 along the first direction DR 1 , and a fourth pixel row may indicate pixels PX 41 to PX 412 connected to the second scan line SL 4 along the first direction DR 1 .

Each of the pixel rows may extend in the first direction DR 1 . In addition, odd numbered pixel rows (for example, the first pixel row and the third pixel row) and even numbered pixel rows (for example, the second pixel row and the fourth pixel row) may be alternately disposed in the second direction DR 2 . In addition, pixels included in each pixel row may be designated as a dot in two or more units. As described above, in the case of FIG. 16 , each dot includes three pixels.

An odd numbered pixel row and an even numbered pixel row that are adjacent to each other may be defined as one pair. The pair may mean a pixel row pair. For example, in the case of FIG. 16 , the first pixel row and the second pixel row may be defined as a first pair PRP 1 , and the third pixel row and the fourth pixel row may be defined as a second pair PRP 2 .

In another embodiment, the first pixel row and the second pixel row may be defined as a first pair, the second pixel row and the third pixel row may be defined as a second pair, and the third pixel row and the fourth pixel row may be defined as a third pair.

FIG. 17 illustrates a schematic view for explaining a display mode controller according to an embodiment of the present disclosure.

The display mode controller 15 according to an embodiment of the present disclosure may include a pattern determiner 151 , a static image determiner 152 , and a display mode determiner 153 .

The pattern determiner 151 may generate a pattern detection signal HSF based on grays IGY for at least one input image. For example, the pattern determiner 151 may generate the pattern detection signal HSF when there is a predetermined pattern of a predetermined size or more by referring to the grays IGY of one input image. For example, the pattern determiner 151 may generate the pattern detection signal HSF when there is a predetermined pattern of a predetermined size or more by referring to the grays IGY of one input image and when luminance of the pattern is larger than reference luminance. Here, the size may be an area of a plane defined as a reference with the first direction DR 1 and the second direction DR 2 referenced in FIG. 16 .

The still image determiner 152 may generate a still image detection signal STI when an input image is determined to be a still image based on the grays IGY of continuous input images. When it is determined that the grays IGY of the continuous input images are the same within a reference range, the still image determiner 152 may determine the continuous input images as a still image and generate the still image detection signal STI. When the grays IGY of the continuous input images are different from each other at the outside of the reference range, the still image determiner 152 may determine the continuous input images as a motion picture and generate a motion picture detection signal.

When both the still image detection signal STI and the pattern detection signal HSF are received, the display mode determiner 153 may generate a first display mode signal DM 1 . In this case, the display device 10 may operate in the first display mode described in FIGS. 6, 7, 8, 9, 10, 11, 12, 13, 14, and 15 . Therefore, even if a still image is detected, when it is determined that there is a worst pattern such as a horizontal stripe pattern, a flicker phenomenon may be prevented by displaying the input images at a high frequency. In this case, the scan driver 13 may alternately provide turn-on level scan signals to the odd numbered pixel rows and the even numbered pixel rows (see FIG. 7 ).

In addition, when the display mode determiner 153 receives the still image detection signal STI but does not receive the pattern detection signal HSF, the display mode determiner 153 may generate a second display mode signal DM 2 . In this case, the display device 10 may operate in the second display mode described in FIG. 6 to FIG. 15 . In this case, even if a still image is displayed at a low frequency, since no flicker occurs, power consumption may be reduced. In this case, the scan driver 13 may provide the turn-on level scan signals to the odd-numbered pixel rows during the first sub-frame period SFP 1 (see FIG. 8 ), and may provide the turn-on level scan signals to the even-numbered pixel rows during the second sub-frame period SFP 2 after the first sub-frame period SFP 1 (see FIG. 9 ).

FIGS. 18, 19, and 20 illustrate schematic views for explaining a pattern determiner according to an embodiment of the present disclosure.

Referring to FIG. 18 , the pattern determiner 151 according to an embodiment of the present disclosure may include a representative gray calculator 1511 , a gray difference calculator 1512 , an edge detector 1513 , and a first pattern detector 1514 .

When the display device 10 adopts the embodiment of FIG. 18 , the pattern detection signal HSF of FIG. 17 may be the same as a first pattern detection signal HSF 1 .

The representative gray calculator 1511 may calculate representative grays RGY of dots based on the grays IGY of the input image. Respective grays IGY correspond to respective pixels, and representative grays may correspond to respective dots. Accordingly, when a ratio of the pixels to the dots is 3:1, a ratio of the grays IGY to the representative grays RGY in one input image may also be 3:1.

In one embodiment, the representative gray calculator 1511 may generate the representative grays RGY by transforming the grays IGY into a color space in a dot unit. Accordingly, a component that is most easily viewed by a user may be set as a representative gray.

For example, the representative gray calculator 1511 may convert R, G, and B grays of one dot into a YCoCg color space to obtain a Y value, and may determine the obtained Y value (luminance value) as the representative gray of the corresponding dot. As another example, the representative gray calculator 1511 may convert R, G, and B grays of one dot into an HSV color space to obtain an value, and may determine the obtained value as the representative gray of the corresponding dot.

In another embodiment, the representative gray calculator 1511 may calculate an average value of the grays IGY in a dot unit, so that it may determines the average value as the representative gray of each dot. Meanwhile, the representative gray calculator 1511 may further apply a weight value for each color in calculating the average value.

The gray difference calculator 1512 may calculate a difference DGY between representative grays RGY of adjacent dots in the second direction DR 2 among dots of a p-th pair of the pixel rows. For example, the difference DGY of the representative grays RGY of a predetermined number of dots may be calculated based on q-th dots in the first direction DR 1 among the dots of the p-th pair. In this case, p and q may be integers larger than 0. The predetermined number of dots may mean dots within a mask range using the q-th dots as a reference.

The edge detector 1513 may increase an edge dot number when a first condition that the difference DGY between the representative grays RGY is larger than a first threshold value is satisfied.

In the edge detector 1513 , when the increased q-th dots are not the last dots of the p-th pair, according to a first route RT 1 , the edge detector 1513 may instruct so that according to a first route RT 1 , the gray difference calculator 1512 calculate the difference DGY of the representative grays RGY of dots of a predetermined number based on the q-th dots increased in the first direction DR 1 among the dots of the p-th pair.

In addition, when the increased q-th dots are the last dots of the p-th pair, the edge detector 1513 may instruct so that the first pattern detector 1514 operates according to a second root RT 2 .

The first pattern detector 1514 may increase the edge number when the edge dot number is larger than a second threshold value, and it may generate a first pattern detection signal HSF 1 when the edge number is larger than a third threshold value (fourth root RT 4 ).

Meanwhile, when the edge dot number is smaller than the second threshold value or when the edge number is smaller than the third threshold value, the first pattern detector 1514 may instruct so that according to the third route RT 4 , the gray difference calculator 1512 calculates the difference DGY between the representative grays RGY of the dots adjacent in the second direction DR 2 among the dots of a (p+1)-th pair of pixel rows.

Hereinafter, an operation of the pattern determiner 151 will be exemplarily described with reference to FIG. 16 and FIG. 19 .

The gray difference calculator 1512 may calculate the difference between the representative grays based on the q-th dots of the p-th pair of pixel rows, and may increase q by 1 (S 101 ). For example, it is assumed that p is 1 and q is 2. Assuming that the mask is 2 rows and 3 columns, the dots (DT 11 , DT 12 , DT 13 , DT 21 , DT 22 , and DT 23 ) may be calculated based on the second dots DT 12 and DT 22 of the first pair PRP 1 . For example, the gray difference calculator 1512 may calculate the first difference value of the target grays of the dots DT 11 and DT 21 , the second difference value of the target grays of the dots DT 12 and DT 22 , and the third difference value of the target grays of the dots DT 13 and DT 23 , and it may calculate an average value of the first to third difference values. This average value may be the difference between the representative grays. In this case, q increases to be 3.

In the case in which the algorithm of FIG. 19 is performed only with the difference between the target grays of the dots DT 12 and DT 22 , which are reference dots, without a mask, when a fine portion of the pattern is cut off (that is, it is not a perfect pattern), it may be determined that there is no pattern. Therefore, a mask is required, but a size of the mask may be determined empirically in consideration of computational complexity and effectiveness.

In addition to the first condition (S 102 ) that the difference between the representative grays is larger than the first threshold value, when the second condition that the edge number is 0 or the (p−1)-th pair is an edge is satisfied (S 103 and S 106 ), the edge detector 1513 may increase the edge dot number and register the p-th pair as an edge (S 104 ). For example, it is assumed that the above-described average value is larger than the first threshold value, the initial value of the edge number is 0, and the initial value of the edge dot number is 0. At the time point in determining the first pair PRP 1 , since the edge number has not yet been increased, the edge number is zero. Therefore, by increasing the edge dot number by 1, the edge dot number becomes 1. In addition, the first pair PRP 1 is registered as an edge. The first threshold value may be a minimum contrast value for luminance for allowing the odd numbered pixel row and the even numbered pixel row to configure the edge of the pattern. The first threshold value may be determined according to the specification of the display device 10 , or may be determined by experience.

Meanwhile, when at least one of the first condition (S 102 ) and the second condition (S 103 and S 106 ) is not satisfied, the edge detector 1513 may register the p-th pair as a non-edge, and may initialize the edge dot number (S 107 ). That is, in this case, the dots determined up to at least current time point are not considered as constituent elements of the pattern.

After the p-th pair is registered as an edge or non-edge, when the increased q-th dots are not the last dots of the p-th pair (S 105 ), the gray difference calculator 1512 may calculate a difference between representative grays of a predetermined number of dots based on the increased q-th dots (S 101 ). For example, the first pair PRP 1 is registered as an edge, but the third dots DT 13 and DT 23 are not the last dots of the first pair PRP 1 , so step S 101 may be again performed by using the third dots DT 13 and DT 23 as reference dots.

Meanwhile, after the p-th pair is registered as an edge or non-edge, the first pattern detector 1514 may operate only when the increased q-th dots are the last dots of the p-th pair (RT 2 ). Hereinafter, it is assumed that the sequentially increased q indicates the last dots of the first pair PRP 1 , and the first pattern detector 1514 operates.

When the edge dot number is smaller than the second threshold value (S 113 ), the first pattern detector 1514 may initialize the edge number (S 108 ). In this case, the first pattern detector 1514 may initialize q to 0. For example, that the edge dot number of the first pair PRP 1 is smaller than the second threshold value may mean that the edge dots configuring the edge of the first pair PRP 1 are insufficient. That is, the first pair PRP 1 may mean that one stripe of the horizontal stripe pattern may not be configured. The second threshold value may define the size of the first direction DR 1 of the pattern. The second threshold value may be an integer larger than 1.

Meanwhile, when the edge dot number is larger than the second threshold value, the first pattern detector 1514 may increase the edge number (S 108 and S 109 ). In this case, the first pattern detector 1514 may initialize q to 0. For example, that the edge dot number of the first pair PRP 1 is larger than the second threshold value may mean that the edge dots configuring the edge of the first pair PRP 1 are sufficient. That is, the first pair PRP 1 may mean that one stripe (equal to edge) of the horizontal stripe pattern may be configured.

Next, the first pattern detector 1514 may determine whether the edge number is larger than the third threshold value (S 110 ). Even if the first pair PRP 1 configures one edge, since the edge number is still 1, the edge number may be smaller than the third threshold value. The third threshold value may define the size of the second direction DR 2 of the pattern. For example, the third threshold value may be an integer larger than 1.

When the edge dot number is smaller than the second threshold value (S 108 ) or when the edge number is smaller than the third threshold value (S 110 ), the gray difference calculator 1512 may calculate a difference between representative grays of dots adjacent in the second direction DR 2 among the dots of the (p+1)-th pair of the pixel rows (S 111 and S 101 ). In this case, the edge dot number may be initialized to 0 (S 111 ). For example, the gray difference calculator 1512 may again perform step S 101 for the second pair PRP 2 .

Meanwhile, when the edge number is larger than the third threshold value (S 110 ), the first pattern detector 1514 may generate the first pattern detection signal (S 112 ). That is, when a pattern having a size larger than the second threshold value in the first direction DR 1 and larger than the third threshold value in the second direction DR 2 exists, the first pattern detector 1514 may provide the first pattern detection signal.

Referring to FIG. 20 , a graph in which a horizontal axis represents display frequencies (Hz) of input images, and a vertical axis represents sizes (for example, vertical or horizontal lengths in a case of a square) of the pattern is shown.

Referring to the graph of FIG. 20 , the higher the display frequency and the smaller the pattern size, the lower the possibility of flicker occurs when the display device 10 is driven in the second display mode (Flicker Free). Meanwhile, the lower the display frequency and the larger the pattern size, the higher the possibility of flicker occurring when the display device 10 is driven in the second display mode (Flicker Zone). However, FIG. 20 is an example graph, which is empirically illustrated, and other graphs may be derived according to the specifications of the display device 10 .

FIG. 21 and FIG. 22 illustrate schematic views for explaining a pattern determiner according to another embodiment of the present disclosure.

Referring to FIG. 21 , a pattern determiner 151 ′ according to an embodiment of the present disclosure may include a representative gray calculator 1511 , a gray difference calculator 1512 , an edge detector 1513 , a first pattern detector 1514 , a pattern luminance calculator 1515 , and a second pattern detector 1516 . The representative gray calculator 1511 , the gray difference calculator 1512 , the edge detector 1513 , and the first pattern detector 1514 are the same as those described with reference to FIGS. 18, 19, and 20 , so duplicate descriptions will be omitted.

When the display device 10 adopts the embodiment of FIG. 21 , the pattern detection signal HSF of FIG. 17 may be the same as a second pattern detection signal HSF 2 .

When the first pattern detection signal HSF 1 is generated, the first pattern detector 1514 may further generate pattern position information PTP for the detected pattern. For example, the pattern position information PTP may be information indicating dots configuring a pattern.

The pattern luminance calculator 1515 may calculate luminance of the pattern based on the pattern position information PTP and the representative grays RGY For example, the pattern luminance calculator 1515 may calculate an average value of the representative grays RGY of the dots indicated by the pattern position information PTP, and may determine the average value as the luminance of the pattern. In one embodiment, weight values according to the positions of the dots may be applied in the calculation of the average value.

The pattern luminance calculator 1515 may generate a pattern valid signal HSB when the luminance of the pattern is larger than the reference luminance. The pattern valid signal HSB may indicate that the luminance of the detected pattern is high enough to be able to be viewed by a user.

The second pattern detector 1516 may generate the second pattern detection signal HSF 2 only when it receives both the pattern valid signal HSB and the first pattern detection signal HSF 1 .

That is, according to the present embodiment, whether to enter the second display mode is determined by considering not only the size of the pattern but also the luminance of the pattern. Therefore, even if the size of the pattern is sufficiently large, when the luminance of the pattern is low and the possibility of being viewed by the user is low, the display device 10 may be driven in the second display mode to reduce power consumption.

Unlike FIG. 21 , in another embodiment, the pattern luminance calculator 1515 may generate the pattern valid signal HSB when the difference DGY between the representative grays RGY is larger than or equal to a specific value. In this case, the pattern luminance calculator 1515 may not directly receive the representative grays RGY In one embodiment, the pattern luminance calculator 1515 may not directly receive the pattern position information PTP.

Referring to FIG. 22 , a graph in which a horizontal axis represents display frequencies (Hz) of input images, and a vertical axis represents luminance (nit) of the pattern is shown.

Referring to the graph of FIG. 22 , the higher the display frequency and the smaller the pattern luminance, the lower the possibility of flicker occurs when the display device 10 is driven in the second display mode (Flicker Free). Meanwhile, the lower the display frequency and the larger the pattern luminance, the higher the possibility of flicker occurring when the display device 10 is driven in the second display mode (Flicker Zone). However, FIG. 22 is an example graph, which is empirically illustrated, and other graphs may be derived according to the specifications of the display device 10 .

While this disclosure has been described in connection with what is presently considered to be practical embodiments, it is to be understood that the disclosure is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims. Therefore, those skilled in the art will understand that various modifications and other equivalent embodiments of the present disclosure are possible. Consequently, the true technical protective scope of the present disclosure must be determined based on the technical spirit of the appended claims.