Zero-delay phase-locked loop frequency synthesizer based on multi-stage synchronization

The present application is a continuation of International Application No. PCT/CN2020/084245, filed on Apr. 10, 2020, which claims priority to Chinese Application No. 201910812883.9, filed on Oct. 30, 2019, the contents of both of which are incorporated herein by reference in their entireties.

The present disclosure relates to the technical field of integrated circuits, in particular to a zero-delay phase-locked loop frequency synthesizer based on multi-stage synchronization.

A phase-locked loop is a frequency control system, which is widely used in circuit design, including clock generation, clock recovery, jitter and noise reduction, frequency synthesis and the like. The operation of PLL is based on the phase difference between feedbacks of a reference clock signal and an output clock signal of a voltage control oscillator (VCO). A traditional PLL includes a phase frequency detector, a charge pump, a loop pass filter, a voltage control oscillator and a divider on a feedback loop. For an ideal circuit, the divider is triggered by the edge of the clock signal output by the voltage control oscillator, so the input and output clock signals should be edge aligned, while the feedback clock signal output by the voltage control oscillator through the divider and the reference clock signal are aligned through a loop, and finally the phases of the clock signal output by the voltage control oscillator and the reference clock signal are consistent. However, in an actual circuit, due to a large number of nonlinear delays in each module of the divider, even if the phase of the feedback clock signal is consistent with that of the reference clock signal, the accurate phase of the output clock signal of the voltage control oscillator cannot be determined.

In order to overcome this problem, zero-delay clock technology arose. The traditional zero-delay clock technology is to add an adjustable delay unit to a feedback loop, and obtain a zero-delay clock by automatic calibration of a digital circuit or artificial adjustment. But this obviously increases the complexity of the circuit greatly.

The purpose of the present disclosure is to provide an output clock signal with the same phase as the reference clock signal without increasing the circuit complexity. The present disclosure provides a zero-delay phase-locked loop frequency synthesizer based on multi-stage synchronization.

In order to achieve the above purpose, the present disclosure uses a multi-stage synchronization structure with a tree-like connection, which reduces the requirement of nonlinear delay of the whole circuit to a certain extent. The present disclosure is realized by the following technical solution: a zero-delay phase-locked loop frequency synthesizer based on multi-stage synchronization, comprising a phase frequency detector, a charge pump, a loop pass filter, a voltage control oscillator and a multi-stage synchronization divider, wherein an output OP end of the phase frequency detector is connected with an input IP end of the charge pump, an output ON end of the phase frequency detector is connected with an input IN end of the charge pump, an output end of the charge pump is connected with an input end of the loop pass filter, an output end of the loop pass filter is connected with an input end of the voltage control oscillator, an output end of the voltage control oscillator is connected with an input end of the multi-stage synchronous divider, and an output end of the multi-stage synchronous divider is connected with an input IN end of the phase frequency detector to form a feedback path.

Furthermore, the multi-stage synchronization divider adopts a PS counter structure, and specifically comprises a dual-modulus divider, a P counter, an S counter, a first clock synchronization module SYN 1 , a second clock synchronization module SYN 2 and a third clock synchronization module SYN 3 ; the output end of the voltage control oscillator is simultaneously connected with an input end a of the dual-modulus divider, an synchronization end c of the first clock synchronization module SYN 1 and an synchronization end c of the third clock synchronization module SYN 3 ; an output end b of the dual-modulus divider is connected with an input end a of the first clock synchronization module SYN 1 , and an output end b of the first clock synchronization module SYN 1 is simultaneously connected with an input end a of the S counter, an input end a of the P counter and an synchronization end c of the second clock synchronization module SYN 2 ; an output end b of the S counter is connected to a mode switch end c of the dual-modulus divider, and an output end b of the P counter is connected to an input end a of the second clock synchronization module SYN 2 , an output end b of the second clock synchronization module SYN 2 is connected to an input end a of the third clock synchronization module SYN 3 , and an output end b of the third clock synchronization module SYN 3 is connected to an input IN end of the phase frequency detector; an output signal CLK_VCO of the voltage control oscillator is further connected to the synchronization end c of the synchronization module SYN 1 and the synchronization end c of the synchronization module SYN 3 .

Furthermore, the output clock signal CLK_VCO of the voltage control oscillator is input to the multi-stage synchronization divider, and a clock signal CLK 1 obtained by frequency division by the dual-modulus divider is input to the first clock synchronization module SYN 1 ; the first clock synchronization module SYN 1 takes CLK_VCO as a trigger clock to obtain an output signal CLK 2 , which is input to the P counter and the S counter; the S counter outputs a MC signal, the P counter outputs a pulse signal CLK 3 ; the pulse signal CLK 3 is input to the second clock synchronization module SYN 2 to obtain an output signal CLK 4 ; the pulse signal CLK 4 is input to the third clock synchronization module SYN 3 to obtain CLK_DIV; the CLK_DIV is input into the phase frequency detector (PFD), and is compared with a reference clock CLK_REF in terms of phase.

Furthermore, a delay T syn1 of the first clock synchronization module SYN 1 , a delay T syn2 of the second clock synchronization module SYN 2 and a delay T CLK_VCO of the voltage control oscillator satisfy:

T syn1 +T syn2 <T CLK_VCO .

The beneficial effects of the present invention is that: the zero-delay phase-locked loop frequency synthesizer provided by the present disclosure uses a multi-stage synchronization divider structure to synchronize the output clock signal of the voltage control oscillator step by step, and finally controls the relative delay of the divider to Tsyn 3 , that is, a gate delay. At the same time, the phase consistency between the reference clock signal and the output clock signal of the voltage control oscillator is realized to the greatest extent without adding an additional adjustable delay unit, thus obtaining a zero-delay clock signal. Compared with the traditional technology, the circuit of the present disclosure is simpler, and it is not necessary to add a plurality of adjustable delay units in the phase-locked loop circuit to realize the phase alignment of the output signal and the reference signal, thereby reducing the circuit complexity and the system power consumption, and therefore the circuit can be applied to wider fields such as communication, phased arrays and the like.

FIG. 1 is a schematic diagram of a traditional phase-locked loop circuit;

FIG. 2 is a schematic diagram of a traditional zero-delay phase-locked loop frequency synthesizer;

FIG. 3 is a schematic diagram of a signal of each point of the traditional zero-delay phase-locked loop frequency synthesizer;

FIG. 4 is a schematic diagram of an improved zero-delay phase-locked loop frequency synthesizer;

FIG. 5 is a schematic diagram of a signal of each point of the improved zero-delay phase-locked loop frequency synthesizer of the present disclosure;

FIG. 6 shows the application of the present disclosure to a multi-channel transceiver system.

For an ideal divider, its input and output clock signals are naturally consistent in phase. However, in the actual circuit, any module will have a certain delay. In the present disclosure, the influence of this delay is minimized. In order to make the purpose and effect of the present disclosure clearer, the present disclosure will be further explained in detail with reference to the drawings. It should be appreciated that what is described herein is only for explaining the present disclosure, rather than to limit the present disclosure.

FIGS. 1-3 show the traditional zero-delay phase-locked loop frequency synthesizer circuit, which realizes the phase consistency between the output clock signal and the input reference clock signal through the adjustable delay unit, so as to achieve the purpose of zero delay.

FIG. 4 is a schematic diagram of an improved zero-delay phase-locked loop frequency synthesizer. Different from the traditional PLL system, the first clock synchronization module SYN 1 , the second clock synchronization module SYN 2 and the third clock synchronization module SYN 3 are added to the PLL frequency synthesizer. The PLL frequency synthesizer specifically includes a phase frequency detector, a charge pump, a loop pass filter, a voltage control oscillator and a multi-stage synchronization divider, wherein an output OP end of the phase frequency detector is connected with an input IP end of the charge pump, an output ON end of the phase frequency detector is connected with an input IN end of the charge pump, an output end of the charge pump is connected with an input end of the loop pass filter, an output end of the loop pass filter is connected with an input end of the voltage control oscillator, an output end of the voltage control oscillator is connected with an input end of the multi-stage synchronous divider, and an output end of the multi-stage synchronous divider is connected with an input IN end of the phase frequency detector to form a feedback path.

In the synthesizer, the multi-stage synchronization divider adopts a PS counter structure, and specifically comprises a dual-modulus divider, a P counter, an S counter, a first clock synchronization module SYN 1 , a second clock synchronization module SYN 2 and a third clock synchronization module SYN 3 ; the output end of the voltage control oscillator is simultaneously connected with an input end a of the dual-modulus divider, an synchronization end c of the first clock synchronization module SYN 1 and an synchronization end c of the third clock synchronization module SYN 3 ; an output end b of the dual-modulus divider is connected with an input end a of the first clock synchronization module SYN 1 , and an output end b of the first clock synchronization module SYN 1 is simultaneously connected with an input end a of the S counter, an input end a of the P counter and an synchronization end c of the second clock synchronization module SYN 2 ; an output end b of the S counter is connected to a mode switch end c of the dual-modulus divider, and an output end b of the P counter is connected to an input end a of the second clock synchronization module SYN 2 , an output end b of the second clock synchronization module SYN 2 is connected to an input end a of the third clock synchronization module SYN 3 , and an output end b of the third clock synchronization module SYN 3 is connected to an input IN end of the phase frequency detector; an output signal CLK_VCO of the voltage control oscillator is further connected to the synchronization end c of the synchronization module SYN 1 and the synchronization end c of the synchronization module SYN 3 .

Firstly, the output clock signal CLK_VCO of the voltage control oscillator is input into a multi-stage synchronization divider, and is divided by a dual-modulus divider, in which a large number of nonlinear delays are accumulated. The CLK_VCO input to the dual-modulus divider is divided to obtain a clock signal CLK 1 , which is then input to the first clock synchronization module SYN 1 ; the first clock synchronization module SYN 1 takes the CLK_VCO as a trigger clock to obtain an output signal CLK 2 , so that the output signal CLK 2 and CLK_VCO are edge-aligned. The CLK 2 is then input into a P counter and an S counter; when the S counter counts to a set value, it outputs a MC signal to the dual-modulus divider to change its frequency dividing ratio; the P counter continues counting until the P counter counts to the set value and outputs a pulse signal CLK 3 ; the pulse signal CLK 3 is input to the second clock synchronization module SYN 2 to obtain an output signal CLK 4 . The second clock synchronization module SYN 2 uses CLK 1 as a trigger clock, so that its output signal CLK 4 is edge-aligned with the output signal CLK 1 of the first clock synchronization module SYN 1 . The pulse signal CLK 4 is input to the third clock synchronization module SYN 3 to obtain CLK_DIV, and the third clock synchronization module SYN 3 uses the CLK_VCO as the trigger clock again, so that its output signal CLK_DIV and CLK_VCO are edge-aligned, that is, they are consistent in phase. The CLK_DIV is input into a phase frequency detector (PFD), and compared with a reference clock CLK_REF. After the loop is locked, the two are consistent in phase, and the CLK_VCO with the same phase as CLK_DIV is naturally consistent with CLK_REF in phase, thus realizing a zero-delay phase-locked loop frequency synthesizer.

FIG. 5 is a schematic signal diagram of the zero-delay phase-locked loop frequency synthesizer based on multi-stage synchronization according to the present disclosure. CLK_VCO will accumulate a certain delay T delay1 after passing through the dual-modulus divider, which makes CLK 1 and CLK_VCO have a certain phase difference. In the first clock synchronization module SYN 1 , after the synchronization of CLK_VCO, CLK 2 is aligned with CLK_VCO again. However, due to the non-ideality of the circuit, the first clock synchronization module SYN 1 itself also has a time delay, namely T syn1 , but it is obvious that T syn1 <<Tdelay1. When CLK 2 is input to the P counter again, a large amount of delay T delay2 will be accumulated there, so the delay between CLK 3 and CLK_VCO is T syn1 +T delay2 . In the second clock synchronization module SYN 2 , the CLK 4 is aligned with CLK 2 , so the delay between CLK 4 and CLK_VCO is reduced to T syn1 +T syn2 . Similarly, since T syn2 <<T delay2 , then T syn1 +T syn2 <<T syn1 +T delay2 . CLK 4 is synchronized with CLK_VCO in the third clock synchronization module SYN 3 , so that CLK 4 and CLK_VCO are aligned, and there is only a delay of T syn3 between the finally obtained CLK_DIV and CLK_VCO, while CLK_DIV and CLK_REF are aligned through the loop, finally making the phases of the CLK_VCO and CLK_REF aligned.

At the same time, it should be noted that the delay T syn1 of the first clock synchronization module SYN 1 , the delay T syn2 of the second clock synchronization module SYN 2 and the delay T CLK_VCO of the voltage control oscillator should satisfy: Tsyn1+Tsyn2<T CLK_VCO . That is, when the CLK_VCO samples CLK 3 , the delay between them should be less than T CLK_VCO . Otherwise, due to the non-ideal factors of the circuit, the sampling of CLK 3 by the CLK_VCO may occur at its rising edge, which leads to sampling failure, and then leads to logic confusion of the divider.

FIG. 6 is a diagram showing the application of the zero-delay phase-locked loop frequency synthesizer based on multi-level synchronization in a multi-channel transceiver system. The reference clock signal CLK_REF is provided from the same signal source to TXPLL and RXPLL. Due to the characteristics of the zero-delay phase-locked loop, its output clocks CLK_TX and CLK_RX are phase-aligned with the reference clock signal CLK_REF, while the consistency between the phases of the clock signals reaching each module is realized by adjusting signal paths from TXPLL and RXPLL to respective TX and RX modules, thereby finally realizing the synchronization of all TX and RX paths.