Transmission circuit and transmission system adopting reduced number of interfaces

This non-provisional application claims priority of Taiwan patent application No. 109133002, filed on 24 Sep. 2020, included herein by reference in its entirety.

1. Field of the Invention

The present invention relates to a transmission circuit, in particular, to a transmission circuit adopting a reduced number of interfaces.

2. Description of the Prior Art

In the art, a gigabit media independent interface (GMII) or a reduced gigabit media independent interface (RGMII) are typically used for data transmission between the physical layer and the data link layer. The gigabit media independent interface includes 2 clock interfaces, 8 data input interfaces, 8 data output interfaces, 2 output control signal interfaces and 2 input control signal interfaces. In each clock cycle, each data interface of the gigabit media independent interface may transmit or receive a one-bit signal. Due to the large number of interfaces adopted in the gigabit media independent interface, the internal wiring of the chip is complex, resulting in an increase in the overall circuit size, and leading to complex inflexible designs of external circuits.

In order to reduce the number of interfaces, the reduced gigabit media independent interface may transmit a 1-bit signal at the time upon each rising and falling edge of the clock. In this manner, when the number of data interfaces is halved, the reduced gigabit media independent interface may still operate at the same transmission frequency as the gigabit media independent interface. Nevertheless, the number of interfaces will be fixed regardless of a reduced gigabit media independent interface or a gigabit media independent interface being used, and the circuit design is inflexible even if an application adopts a lower transmission rate.

According to an embodiment of the invention, a transmission circuit includes a first data input interface, a first serial-to-parallel converter, an interface decoder, a first parallel-to-serial converter and a processor circuit. The first serial-to-parallel converter is electrically coupled to the first data input interface, and is used to convert at least a plurality of first data signals from the first data input interface into a set of first parallel data signals, the set of first parallel data signals including a plurality of bit signals transmitted in parallel. The interface decoder is electrically coupled to the first serial-to-parallel converter, and is used to decode the set of first parallel data signals to generate a set of decoded data signals for parallel transmission. The first parallel-to-serial converter is electrically coupled to the interface decoder, and is used to convert the set of decoded data signals into a plurality of input data signals for serial transmission. The processor circuit is electrically coupled to the first parallel-to-serial converter, and is used to receive and process the plurality of input data signals.

According another embodiment of the invention, a transmission system includes an upper-layer transmission circuit, a first lower-layer transmission circuit and a second lower-layer transmission circuit. The upper-layer transmission circuit includes a first upper-layer output interface and a second upper-layer output interface. The first lower-layer transmission circuit includes a first data input interface, a first serial-to-parallel converter, a first interface decoder, a first parallel-to-serial converter and a first processor circuit. The first data input interface is electrically coupled to the first upper-layer output interface of the upper-layer transmission circuit. The first serial-to-parallel converter is electrically coupled to the first data input interface, and is used to convert at least a plurality of first data signals from the first data input interface into a set of first parallel data signals, the set of first parallel data signals including a plurality of bit signals transmitted in parallel. The first interface decoder is electrically coupled to the first serial-to-parallel converter, and is used to decode the set of first parallel data signals to generate a set of first decoded data signals for parallel transmission. The first parallel-to-serial converter is electrically coupled to the first interface decoder, and is used to convert the set of first decoded data signals into a plurality of first input data signals for serial transmission. T first processor circuit is electrically coupled to the first parallel-to-serial converter, and is used to receive and process the plurality of first input data signals. The second lower-layer transmission circuit includes a second data input interface, a second serial-to-parallel converter, a second interface decoder, a second parallel-to-serial converter and a second processor circuit. The second data input interface is electrically coupled to the second upper-layer output interface of the upper-layer transmission circuit. The second serial-to-parallel converter is electrically coupled to the second data input interface, and is used to convert at least a plurality of second data signals from the second data input interface into a set of second parallel data signals, the set of second parallel data signals including a plurality of bit signals transmitted in parallel. The second interface decoder is electrically coupled to the second serial-to-parallel converter, and is used to decode the set of second parallel data signals to generate a set of second decoded data signals for parallel transmission. The second parallel-to-serial converter is electrically coupled to the second interface decoder, and is used to convert the set of second decoded data signals into a plurality of second input data signals for serial transmission. T second processor circuit is electrically coupled to the second parallel-to-serial converter, and is used to receive and process the plurality of second input data signals.

These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.

FIG. 1 is a schematic diagram of a transmission circuit according to an embodiment of the invention.

FIG. 2 is a schematic diagram of a transmission circuit according to another embodiment of the invention.

FIG. 3 is a schematic diagram of a transmission system according to an embodiment of the invention.

FIG. 4 is a schematic diagram of a transmission system according to another embodiment of the invention.

FIG. 1 is a schematic diagram of a transmission circuit 100 according to an embodiment of the invention. In FIG. 1 , the transmission circuit 100 may be electrically coupled to another transmission circuit TC 1 , and may perform data transmission with the transmission circuit TC 1 . In some embodiments, the transmission circuit 100 may be a physical layer transmission circuit, and the transmission circuit TC 1 may be a data link layer transmission circuit. In the related art, if a reduced gigabit media independent interface (RGMII) is used for data transmission between the transmission circuit for the physical layer and the transmission circuit for the data link layer, each of the two transmission circuits must include four uplink data transmission interfaces and four downlink data transmission interfaces, resulting in an inflexible design. In contrast, the transmission circuit 100 may perform uplink data transmission via a transmission interface and/or perform downlink data transmission via a transmission interface.

The data input interface RD 1 may sequentially receive a plurality of data signals DR 1 from a corresponding interface of the transmission circuit TC 1 . The serial-to-parallel converter 110 may be electrically coupled to the data input interface RD 1 , and may convert a plurality of data signals DR 1 from the data input interface RD 1 into a set of parallel data signals PDR 1 . The set of parallel data signals PDR 1 may include a plurality of bit signals for parallel transmission.

The interface decoder 120 may be electrically coupled to the serial-to-parallel converter 110 , and may decode the set of parallel data signals PDR 1 to generate a set of decoded data signals PDDR 1 for parallel transmission. In some embodiments, the interface decoder 120 may decode the set of parallel data signals PDR 1 according to the RGMII specification. In such a case, the set of parallel data signals PDR 1 may include 8 synchronously transmitted bit signals. Since the serial-to-parallel converter 110 may convert a plurality of data signals DR 1 for serial transmission into a set of parallel data signals PDR 1 for parallel transmission, the interface decoder 120 may use the decoding mechanism commonly used for reduced gigabit media independent interfaces to perform decoding without redesigning the circuit, thereby reducing complexity of the circuit design.

In addition, in the process of converting the plurality of data signals DR 1 into the set of parallel data signals PDR 1 for parallel transmission, it is necessary to wait for all bits of data in the set of parallel data signals PDR 1 to be received before they can be output together. Therefore, the interface decoder 120 may operate at a lower frequency and reduce power consumption. For example, if the frequency of the clock of the transmission circuit 100 is 125 MHz, the rate of data transmission between the transmission circuit 100 and the TC 1 may reach 250 Mbits per second if the transmission data is determined upon both the rising and falling edges. In such a case, if the set of parallel data signals PDR 1 includes 8 bits, the clock of the interface decoder 120 only needs to operate at 31.25 MHz to meet the target data transmission rate. In other words, the transmission circuit 100 may perform other functions that also adopt the reduced gigabit media independent interface by adjusting the operating frequency of the interface decoder 120 , so as to achieve circuit sharing.

The parallel-to-serial converter 130 may be electrically coupled to the interface decoder 120 and may convert the set of decoded data signals PDDR 1 into a plurality of input data signals DI 1 for serial transmission. The processor circuit 140 may be electrically coupled to the parallel-to-serial converter 130 , and may receive and process the plurality of input data signals DI 1 .

In FIG. 1 , the transmission circuit 100 may also transmit data to the transmission circuit TC 1 . For example, the processor circuit 140 may also generate a plurality of output data signals DO 1 for serial transmission. The transmission circuit 100 may further include a serial-to-parallel converter 150 , an interface encoder 160 , a parallel-to-serial converter 170 , and a data output interface TD 1 .

The serial-to-parallel converter 150 may be electrically coupled to the processor circuit 140 and may convert the plurality of output data signals DO 1 into a set of parallel data signals PDT 1 , and the set of parallel data signals PDT 1 may include a plurality of pieces of bit data transmitted in parallel.

The interface encoder 160 may be electrically coupled to the serial-to-parallel converter 150 , and may encode the set of parallel data signals PDT 1 to generate a set of encoded data signals PEDT 1 for parallel transmission. In some embodiments, the interface decoder 120 and the interface encoder 160 may be implemented by two separate circuits. In other embodiments, the interface decoder 120 and the interface encoder 160 may be integrated together, or may share a portion of functional blocks.

The parallel-to-serial converter 170 may be electrically coupled to the interface encoder 160 , and may convert the set of encoded data signals PEDT 1 into a plurality of data signals DT 1 for serial transmission, and the data output interface TD 1 may serially output the plurality of data signals DT 1 to the transmission circuit TC 1 .

Since the transmission circuit 100 may internally convert a serial data signal into parallel data signals, and then convert the parallel data signals back into a serial data signal, a single data input interface RD 1 may be used to receive data from the transmission circuit TC 1 , and a single data output interface TD 1 may be used to output data to the transmission circuit TC 1 . In some embodiments, the transmission circuit 100 may also use two or three data input interfaces to receive data from the transmission circuit TC 1 , and use two or three data output interfaces to output data to the transmission circuit TC 1 .

FIG. 2 is a schematic diagram of a transmission circuit 200 according to an embodiment of the invention. The transmission circuits 100 and 200 may be similar in structure and operate in similar principle. The transmission circuit 200 may further include a data input interface RD 2 and a data output interface TD 2 .

In such a case, the data input interfaces RD 2 and RD 1 may receive the data signal DR 1 together. In other words, in the case where the clock frequency is maintained at 125 MHz, the data signal may be received in parallel via the data input interfaces RD 1 and RD 2 to achieve a transmission rate of 250 Mbits per second. In such a case, the serial-to-parallel converter 210 may convert a plurality of data signals DR 1 received from the data input interfaces RD 1 and RD 2 into a set of parallel data signals PDR 1 . In this fashion, the transmission circuit 200 may also adopt the interface decoder 120 for decoding. In addition, in this embodiment, the operating frequency of the interface decoder 120 may be adjusted to 62.5 MHz to match the data rate at which the transmission circuit 200 receives the data signal DR 1 to maintain the transmission rate at 250 Mbits per second.

Next, the parallel-to-serial converter 230 may convert a set of decoded data signals PDDR 1 into a plurality of input data signals DI 1 for serial transmission, and the processor circuit 240 may receive and process the plurality of input data signals DI 1 .

Similarly, when the transmission circuit 200 is configured to transmit the data signal DT 1 to the transmission circuit TC 1 , the processor circuit 240 may generate a plurality of output data signals DO 1 for serial transmission, and the serial-to-parallel converter 250 may convert the plurality of output data signals DO 1 into a set of parallel data signals PDT 1 , and the interface encoder 160 may decode the same to generate a set of encoded data signals PEDT 1 . The parallel-to-serial converter 270 may then convert the set of encoded data signals PEDT 1 into a plurality of data signals DT 1 for serially transmission, and then output the plurality of serial data signals DT 1 in parallel to the transmission circuit TC 1 via the data output interface TD 1 and the data output interface TD 2 .

In other words, by adopting the serial-to-parallel conversion mechanism, the transmission circuit may select an appropriate number of data interfaces based on the transmission requirements to perform the data transmission of the reduced gigabit media independent interface, achieving a flexible circuit design.

Further, in FIGS. 1 and 2 , the transmission circuit 100 may include an output control interface TCTL 1 , an output clock interface TCLK 1 , an input control interface RCTL 1 and an input clock interface RCLK 1 . When the transmission circuit 100 outputs data using the data output interface TD 1 , the transmission circuit 100 may output a control signal via the output control interface TCTL 1 , and output a clock signal via the output clock interface TCLK 1 for the transmission circuit TC 1 to receive data properly. In contrast, when receiving the data using the data input interface RD 1 , the input control interface RCTL 1 may receive the control signal, and the input clock interface RCLK 1 may receive the clock signal for the transmission circuit 100 to receive the data properly.

In some embodiments, the transmission circuits may perform transmissions based on a single-input multiple-output approach. For example, an upper-layer transmission circuit associated with the data link layer may be electrically coupled to a plurality of lower-layer transmission circuits associated with the physical layer to perform data transmission. In such a case, the plurality of lower-layer transmission circuits may be commonly electrically coupled to the control interface and the clock interface of the upper-layer transmission circuit to reduce the wiring between transmission circuits associated with the two layers.

FIG. 3 is a schematic diagram of a transmission system 10 according to an embodiment of the invention. In FIG. 3 , the transmission system 10 may include lower-layer transmission circuits 100 A, 100 B, 100 C, and 100 D, and an upper-layer transmission circuit UC 1 . In some embodiments, the lower-layer transmission circuits 100 A, 100 B, 100 C, and 100 D and the transmission circuit 100 may have identical structures, and may operate in identical principles, and the upper-layer transmission circuit UC 1 and the transmission circuit TC 1 may have identical structures and may operate in identical principles. For example, the upper-layer transmission circuit UC 1 may be a transmission circuit corresponding to the data link layer, and the lower-layer transmission circuits 100 A, 100 B, 100 C, and 100 D may be a transmission circuit corresponding to the physical layer.

In FIG. 3 , the upper-layer transmission circuit UC 1 may include upper-layer output interfaces UTD 1 , UTD 2 , UTD 3 and UTD 4 , upper-layer input interfaces URD 1 , URD 2 , URD 3 and URD 4 , an upper-layer output control interface UTCTL 1 , an upper-layer output clock interface UTCLK 1 , an upper-layer input control interface URCTL 1 and an upper-layer input clock interface URCLK 1 .

In such a case, the data input interface RD 1 A of the lower-layer transmission circuit 100 A may be electrically coupled to the upper-layer output interface UTD 1 , and the data output interface TD 1 A of the lower-layer transmission circuit 100 A may be electrically coupled to the upper-layer input interface URD 1 . The data input interface RD 1 B of the lower-layer transmission circuit 100 B may be electrically coupled to the upper-layer output interface UTD 2 , and the data output interface TD 1 B of the lower-layer transmission circuit 100 B may be electrically coupled to the upper-layer input interface URD 2 . The data input interface RD 1 C of the lower-layer transmission circuit 100 C may be electrically coupled to the upper-layer output interface UTD 3 , and the data output interface TD 1 C of the lower-layer transmission circuit 100 C may be electrically coupled to the upper-layer input interface URD 3 . The data input interface RD 1 D of the lower-layer transmission circuit 100 D may be electrically coupled to the upper-layer output interface UTD 4 , and the data output interface TD 1 D of the lower-layer transmission circuit 100 D may be electrically coupled to the upper-layer input interface URD 4 .

In addition, the input control interfaces RCTLA, RCTLB, RCTLC, and RCTLD of the lower-layer transmission circuits 100 A, 100 B, 100 C, and 100 D may all be electrically coupled to the upper-layer output control interface UTCTL 1 , and the input clock interfaces RCLKA, RCLKB, RCLKC and RCLKD of the lower-layer transmission circuits 100 A, 100 B, 100 C, and 100 D may all be electrically coupled to the upper-layer output clock interface UTCLK 1 . The output control interfaces TCTLA, TCTLB, TCTLC, and TCTLD of the lower-layer transmission circuits 100 A, 100 B, 100 C, and 100 D may all be electrically coupled to the upper-layer input control interface URCTL 1 , and the output clock interfaces TCLKA, TCLKB, TCLKC and TCLKD of the lower-layer transmission circuits 100 A, 100 B, 100 C, and 100 D may all be electrically coupled to the upper-layer input clock interface URCLK 1 . That is, in the transmission system 10 , the upper-layer transmission circuit UC 1 may control the lower-layer transmission circuits 100 A, 100 B, 100 C, and 100 D via the same input/output control interfaces and input/output clock interfaces.

In the transmission system 10 , each of the lower-layer transmission circuits 100 A, 100 B, 100 C, and 100 D may include only one data output interface and one data input interface. However, in some embodiments, the lower-layer transmission circuits 100 A to 100 D may include two or three data input/output interfaces.

FIG. 4 is a schematic diagram of a transmission system 20 according to an embodiment of the invention. The transmission system 20 may include lower-layer transmission circuits 200 A and 200 B and an upper-layer transmission circuit UC 1 . The lower-layer transmission circuits 200 A and 200 B may have the same structure as the transmission circuit 200 . The lower-layer transmission circuit 200 A may include data input interfaces RD 1 A and RD 2 A, and data output interfaces TD 1 A and TD 2 A. The data input interfaces RD 1 A and RD 2 A may be electrically coupled to the upper-layer output interfaces UTD 1 and UTD 3 , respectively, and the data output interfaces TD 1 A and TD 2 A may be electrically coupled to the upper-layer input interfaces URD 1 and URD 3 , respectively. Similarly, the lower-layer transmission circuit 200 B may include data input interfaces RD 1 B and RD 2 B and data output interfaces TD 1 B and TD 2 B. The data input interfaces RD 1 B and RD 2 B may be electrically coupled to the upper-layer output interfaces UTD 2 and UTD 4 , respectively, and the data output interfaces TD 1 B and TD 2 B may be electrically coupled to the upper-layer input interfaces URD 2 and URD 4 , respectively.

In other words, the lower-layer transmission circuit 200 A may simultaneously receive data from the upper-layer output interfaces UTD 1 and UTD 3 via the data input interfaces RD 1 A and RD 2 A, and may simultaneously output data to the upper-layer input interfaces URD 1 and URD 3 via the data output interfaces TD 1 A and TD 2 A.

Further, in FIG. 4 , the transmission system 20 may include a management control circuit MC 1 . The management control circuit MC 1 may direct control signals and clock signals to a corresponding transmission circuit among the lower-layer transmission circuits 200 A, 200 B and the upper-layer transmission circuit UC 1 . In some embodiments, the management control circuit MC 1 and the lower-layer transmission circuits 200 A and 200 B may be disposed on the same chip, and may be collectively regarded as a multi-physical layer circuit CS 1 .

In some embodiments, the management control circuit MC 1 may be electrically coupled to the upper-layer output control interface UTCTL 1 , the upper-layer output clock interface UTCLK 1 , the upper-layer input control interface URCTL 1 , the upper-layer input clock interface URCLK 1 and the lower-layer transmission circuits 200 A and 200 B. In other words, the management control circuit MC 1 may enable the lower-layer transmission circuits 200 A, 200 B and the upper-layer transmission circuit UC 1 to receive or transmit corresponding control signals and clock signals based on transmission requirements. By managing the control circuit MC 1 , the wiring between the upper-layer transmission circuit UC 1 and the lower-layer transmission circuits 200 A and 200 B may be further simplified, delivering a flexible design of the transmission system 20 .

The transmission circuit and transmission system provided by the embodiments of the present invention may include converters adopting serial signals and parallel signals, and therefore, when adopting the reduced gigabit media independent interface to transmit data between circuits, the transmission circuit may use one to three data input interfaces and one to three data output interfaces to perform data transmissions. In this fashion, the design of the transmission circuit and the wiring between each other may be simplified, thereby reducing the overall circuit area.

Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.