Analog-to-digital converter and method of operating same

This non-provisional application claims priority of Taiwan patent application No. 110112713, filed on 8 Apr. 2021, included herein by reference in its entirety.

1. Field of the Invention

The present invention relates to electronic circuits, in particular, to an analog-to-digital converter and an operating method thereof.

2. Description of the Prior Art

An analog-to-digital converter (ADC) is a device for converting a continuous signal in analog form into a discrete signal in digital form. Analog-to-digital converters have been widely adopted in audio systems, video systems, communication systems, and various digital signal processing systems. A successive approximation register (SAR) analog-to-digital converter employs capacitor arrays for analog-to-digital conversion, being low in power consumption and suitable for mobile devices and portable devices. However, the mismatch between the capacitances in the capacitor arrays of the SAR ADC will give rise to nonlinearity errors of the SAR ADC and reduce the accuracy of the SAR ADC.

According to an embodiment of the invention, an analog-to-digital converter includes a first capacitor array, a first selection circuit, a second capacitor array, a second selection circuit and a control logic circuit. The first capacitor array includes a plurality of sets of capacitors, each set of capacitors of the first capacitor array comprising a first capacitor and a second capacitor. The second capacitor array includes a plurality of sets of capacitors, each set of capacitors of the second capacitor array comprising a first capacitor and a second capacitor. The first selection circuit is coupled to the first capacitor array. The second selection circuit is coupled to the second capacitor array. The control logic circuit is coupled to the first selection circuit and the second selection circuit. A method of operating an analog-to-digital converter includes in a first sampling stage, switching a switching signal to a first level for the first selection circuit to output a first reference voltage to the first capacitor in each set of capacitors of the first capacitor array and output a second reference voltage to the second capacitor in each set of capacitors of the first capacitor array, and for the second selection circuit to output the first reference voltage to the first capacitor in each set of capacitors of the second capacitor array and output the second reference voltage to the second capacitor in each set of capacitors of the second capacitor array. The method further includes in a second sampling stage, switching a switching signal to a second level for the first selection circuit to output the second reference voltage to the first capacitor in each set of capacitors of the first capacitor array and output the first reference voltage to the second capacitor in each set of capacitors of the first capacitor array, and for the second selection circuit to output the second reference voltage to the first capacitor in each set of capacitors of the second capacitor array and output the first reference voltage to the second capacitor in each set of capacitors of the second capacitor array. The control logic circuit switches the switching signal between the first level and the second level according to a uniform sequence during a plurality of sampling stages. The first level and the second level are different from each other.

According to another embodiment of the invention, an analog-to-digital converter includes a first selection circuit, a second selection circuit, a first capacitor array, a second capacitor array, a comparator and a control logic circuit. The first capacitor array is coupled to the first selection circuit, and includes a plurality of capacitors, each capacitor of the first capacitor array including a first capacitor and a second capacitor. The second capacitor array is coupled to the second selection circuit, and includes a plurality of capacitors, each capacitor of the second capacitor array including a first capacitor and a second capacitor. The comparator comprising a first input terminal coupled to the first capacitor array, a second input terminal coupled to the second capacitor array, and an output terminal. The control logic circuit is coupled to the output terminal of the comparator, the first selection circuit and the second selection circuit. In a first sampling stage, the control logic circuit is configured to switch a switching signal to a first level for the first selection circuit to output a first reference voltage to the first capacitor in each set of capacitors of the first capacitor array and output a second reference voltage to the second capacitor in each set of capacitors of the first capacitor array, and for the second selection circuit to output the first reference voltage to the first capacitor in each set of capacitors of the second capacitor array and output the second reference voltage to the second capacitor in each set of capacitors of the second capacitor array. In a second sampling stage, the control logic circuit is configured to switch a switching signal to a second level for the first selection circuit to output the second reference voltage to the first capacitor in each set of capacitors of the first capacitor array and output the first reference voltage to the second capacitor in each set of capacitors of the first capacitor array, and for the second selection circuit to output the second reference voltage to the first capacitor in each set of capacitors of the second capacitor array and output the first reference voltage to the second capacitor in each set of capacitors of the second capacitor array. The control logic circuit is configured to switch the switching signal between the first level and the second level according to a uniform sequence during a plurality of sampling stages, and the first level and the second level are different from each other.

These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.

FIG. 1A is a circuit schematic of an analog-to-digital converter according to an embodiment of the invention.

FIG. 1B is a circuit schematic of the first selection circuit and/or the second selection circuit in FIG. 1A .

FIG. 2 is a flowchart of a method of operating the analog-to-digital converter in FIG. 1A .

FIG. 3A is a circuit schematic of an analog-to-digital converter according to another embodiment of the present invention.

FIG. 3B is a circuit schematic of the first selection circuit and/or the second selection circuit in FIG. 3A .

FIGS. 4A and 4B show a flowchart of a method of operating the analog-to-digital converter in FIG. 3A .

FIG. 1A is a circuit schematic of an analog-to-digital converter 1 according to an embodiment of the invention. The analog-to-digital converter 1 is a 3-bit split-capacitor type successive approximation register (SAR) analog-to-digital converter (ADC), and can be used to convert differential input voltages Vip, Vin into digital output data Dout according to a successive approximation method such as a binary search method. The differential input voltages Vip, Vin may be provided by a first signal source and a second signal source, respectively. The digital output data Dout may include 3 bits. The analog-to-digital converter 1 may generate a set of digital output data Dout in each operation cycle. Each operation cycle may include a sampling stage (or referred to as an acquisition stage) and a quantization stage (or referred to as a conversion stage). The analog-to-digital converter 1 may sample the differential input voltages Vip, Vin in the sampling stage to generate a pair of sampled signals, and quantize the pair of sampled signals in the quantization stage to generate the digital output data Dout. The quantization stage may include multiple (3) conversions to sequentially generate multiple (3) bits of the digital output data Dout. In a plurality of sampling stages, the analog-to-digital converter 1 may be reset according to two voltage settings, thereby reducing a voltage error owing to a mismatch between capacitive components, reducing an integral nonlinearity (INL) error and a differential nonlinearity (DNL) error, while providing a high-speed analog-to-digital conversion.

The analog-to-digital converter 1 may include a switch SW 1 and a switch SW 2 , a first capacitor array 141 , a first selection circuit 121 , a second capacitor array 142 , a second selection circuit 122 , a comparator 16 and a control logic circuit 18 . The first selection circuit 121 and the switch SW 1 are coupled to the first capacitor array 141 . The second selection circuit 122 and the switch SW 2 are coupled to the second capacitor array 142 . The comparator 16 may include a first input terminal coupled to the first capacitor array 141 , a second input terminal coupled to the second capacitor array 142 , and an output terminal coupled to the control logic circuit 18 . The control logic circuit 18 is coupled to the first selection circuit 121 and the second selection circuit 122 .

The first capacitor array 141 may include 3 sets of capacitors. The capacitances of the 3 sets of capacitors may be different. Each set of capacitors includes a first capacitor and a second capacitor, and the first capacitor and the second capacitor have substantially equal capacitances. The first set of capacitors of the first capacitor array 141 may include a first capacitor C 1 pa and a second capacitor C 1 pb , the second set of capacitors may include a first capacitor C 2 pa and a second capacitor C 2 pb , and the third set of capacitors may include a first capacitor C 3 pa and a second capacitor C 3 pb . The first set of capacitors, the second set of capacitors, and the third set of capacitors of the first capacitor array 141 may respectively correspond to the most significant bit (MSB) to the least significant bit (LSB) of the digital output data Dout. Each of the first capacitor C 1 pa and the second capacitor C 1 pb may have substantially equal capacitances of 3 C, and the first set of capacitors of the first capacitor array 141 may have a capacitance of 6 C. Each of the first capacitor C 2 pa and the second capacitor C 2 pb may have substantial equal capacitances of 2 C, and the second set of capacitors of the first capacitor array 141 may have a capacitance of 4 C. Each of the first capacitor C 1 pa and the second capacitor C 1 pb may have substantially equal capacitances of C, respectively, and the third set of capacitors of the first capacitor array 141 may have a capacitance of 2 C. Each of the capacitors C 1 pa , C 1 pb , C 2 pa , C 2 pb , C 3 pa , C 3 pb may include an upper plate and a lower plate. The upper plates of the capacitors C 1 pa , C 1 pb , C 2 pa , C 2 pb , C 3 pa , C 3 pb may be coupled to the switch SW 1 .

Similarly, the second capacitor array 142 may include 3 sets of capacitors. The capacitances of the 3 sets of capacitors may be different. Each set of capacitors includes a first capacitor and a second capacitor, and the first capacitor and the second capacitor have substantially equal capacitances. The first set of capacitors of the second capacitor array 142 may include a first capacitor C 1 na and a second capacitor C 1 nb , the second set of capacitors may include a first capacitor C 2 na and a second capacitor C 2 nb , and the third set of capacitors may include a first capacitor C 3 na and a second capacitor C 3 nb . The first set of capacitors, the second set of capacitors, and the third set of capacitors of the second capacitor array 142 may respectively correspond to the most significant bit to the least significant bit of the digital output data Dout. Each of the first capacitor C 1 na and the second capacitor C 1 nb may have substantially equal capacitances of 3 C, and the first set of capacitors of the second capacitor array 142 may have a capacitance of 6 C. Each of the first capacitor C 2 na and the second capacitor C 2 nb may have substantial equal capacitances of 2 C, and the second set of capacitors of the second capacitor array 142 may have a capacitance of 4 C. Each of the first capacitor C 1 pa and the second capacitor C 1 pb may have substantially equal capacitances of C, and the third set of capacitors of the second capacitor array 142 may have a capacitance of 2 C. Each of the capacitors C 1 na , C 1 nb , C 2 na , C 2 nb , C 3 na , C 3 nb may include an upper plate and a lower plate. The upper plates of the capacitors C 1 na , C 1 nb , C 2 na , C 2 nb , C 3 na , C 3 nb may be coupled to the switch SW 2 .

The first selection circuit 121 may receive the first reference voltage V 1 and the second reference voltage V 2 to configure the 3 sets of capacitors of the first capacitor array 141 , and the second selection circuit 122 may receive the first reference voltage V 1 and the second reference voltage V 2 to configure the 3 sets of capacitors of the second capacitor array 142 . In some embodiments, the first reference voltage V 1 may be a supply voltage such as 1.8V, and the second reference voltage V 2 may be a ground voltage such as 0V. In other embodiments, the first reference voltage V 1 may be a ground voltage, and the second reference voltage V 2 may be a supply voltage. The first selection circuit 121 may be coupled to the lower plates of the capacitors C 1 pa , Clpb, C 2 pa , C 2 pb , C 3 pa , and C 3 pb . The second selection circuit 122 may be coupled to the lower plates of the capacitors C 1 na , C 1 nb , C 2 na , C 2 nb , C 3 na , and C 3 nb.

The first selection circuit 121 and the second selection circuit 122 may be implemented by one or more switches coupled to the reference voltages V 1 , V 2 and one or more multiplexers, but are not limited thereto. FIG. 1B is a schematic circuit diagram of an embodiment of the first selection circuit 121 or the second selection circuit 122 . Explanation will be made with reference to the first selection circuit 121 as follows. The second selection circuit 122 may be configured and operated according to a principle similar to the first selection circuit 121 . The first selection circuit 121 may include inverters 1 a , 1 b , 2 a , 2 b , 3 a , 3 b , multiplexers M 1 a , M 1 b , M 2 a , M 2 b , M 3 a , M 3 b , and switch circuits S 1 a , S 1 b , S 2 a , S 2 b , S 3 a , S 3 b . The inverters 1 a , 1 b , 2 a , 2 b , 3 a , 3 b may be coupled to the control logic circuit 18 and may be coupled to the multiplexers M 1 a , M 1 b , M 2 a , M 2 b , M 3 a , M 3 b , respectively. The multiplexers M 1 a , M 1 b , M 2 a , M 2 b , M 3 a , and M 3 b may be coupled to the control logic circuit 18 and may be coupled to the switch circuits S 1 a , S 1 b , S 2 a , S 2 b , S 3 a , and S 3 b , respectively. The switch circuits S 1 a , S 1 b , S 2 a , S 2 b , S 3 a , and S 3 b may be coupled to the lower plates of the capacitors C 1 pa , Clpb, C 2 pa , C 2 pb , C 3 pa , and C 3 pb of the first capacitor array 141 , respectively.

The inverters 1 a , 1 b , 2 a , 2 b , 3 a , and 3 b may receive corresponding selection signals from the control logic circuit 18 , respectively. The multiplexers M 1 a , M 1 b , M 2 a , M 2 b , M 3 a , and M 3 b may receive the corresponding selection signals from the control logic circuit 18 and the inverses of the corresponding selection signals from the inverters 1 a , 1 b , 2 a , 2 b , 3 a , and 3 b , and select ones of the corresponding selection signals and the inverses thereof according to the switching signal Sswp to serve as corresponding multiplexer output signals, and output the corresponding multiplexer output signals to the switch circuits S 1 a , S 1 b , S 2 a , S 2 b , S 3 a , and S 3 b . Each of the switch circuits S 1 a , S 1 b , S 2 a , S 2 b , S 3 a , and S 3 b includes switches SV 1 and SV 2 . The switch SV 1 may receive the second reference voltage V 2 , and the switch SV 2 may receive the first reference voltage V 1 . Each of the switch circuits S 1 a , S 1 b , S 2 a , S 2 b , S 3 a , S 3 b may be controlled by the corresponding multiplexer output signal of the multiplexer M 1 a , M 1 b , M 2 a , M 2 b , M 3 a , M 3 b to output the first reference voltage V 1 or the second reference Voltage V 2 .

Referring to FIG. 1A , during the sampling stage, the switch SW 1 and the switch SW 2 may be turned on, and the first capacitor array 141 and the second capacitor array 142 may sample the differential input voltages Vip, Vin, respectively. The control logic circuit 18 may generate the switching signal Sswp, and may switch the switching signal Sswp between the first level and the second level according to a uniform sequence during the plurality of sampling stages, and the first level and the second level are different from each other. The first level may be a logic “0”, and the second level may be a logic “1”. The uniform sequence may be an alternating sequence, a random sequence, or other predetermined sequences. When the uniform sequence is an alternating sequence, the control logic circuit 18 may switch the switching signal Sswp between the first level and the second level alternately. When the uniform sequence is a random sequence, the control logic circuit 18 may randomly switch the switching signal Sswp between the first level and the second level, and the probabilities of switching the signal Sswp to the first level or the second level are substantially equal. The other predetermined sequences may be non-alternating or non-random sequences. For example, the predetermined sequence may include switching the switching signal Sswp to the first level for N sampling stages, and then switching the switching signal Sswp to the second level for subsequent N sampling stages. In other embodiments, the switching signal Sswp may be switched to the first level or the second level according to pre-sampled information, so as to generate the predetermined sequence. In the sampling stage, the first selection circuit 121 and the second selection circuit 122 may output the voltages in the first voltage setting or the second voltage setting to the capacitors C 1 pa , Clpb, C 2 pa , C 2 pb , C 3 pa , C 3 pb and the capacitors C 1 na , C 1 nb , C 2 na , C 2 nb , C 3 na , C 3 nb . Tables 1 and 2 show the first voltage setting and the second voltage setting, respectively:

When the switching signal Sswp is set to the first level during sampling, the first selection circuit 121 may output the corresponding voltages in the first voltage setting to the lower plates of the capacitors C 1 pa , Clpb, C 2 pa , C 2 pb , C 3 pa , C 3 pb , and the switch SW 1 may be turned on to transmit the differential input voltage Vip to the upper plates of the capacitors C 1 pa , Clpb, C 2 pa , C 2 pb , C 3 pa , C 3 pb , so as to establish a voltage Vp at the first input terminal of the comparator 16 ; the second selection circuit 122 may output the corresponding voltage in the first voltage setting to the lower plates of the capacitors C 1 na , C 1 nb , C 2 na , C 2 nb , C 3 na , C 3 nb , and the switch SW 2 may be turned on to transmit the differential input voltage Vin to the upper plates of the capacitors C 1 na , C 1 nb , C 2 na , C 2 nb , C 3 na , C 3 nb , so as to establish a voltage Vn at the second input terminal of the comparator 16 . When the switching signal Sswp is set to the second level during sampling, the first selection circuit 121 may output the corresponding voltages in the second voltage setting to the lower plates of the capacitors C 1 pa , Clpb, C 2 pa , C 2 pb , C 3 pa , C 3 pb , and the switch SW 1 may be turned on to transmit the differential input voltage Vip to the upper plates of the capacitors C 1 pa , Clpb, C 2 pa , C 2 pb , C 3 pa , C 3 pb , so as to establish a voltage Vp; the second selection circuit 122 may output the corresponding voltage in the second voltage setting to the lower plates of the capacitors C 1 na , C 1 nb , C 2 na , C 2 nb , C 3 na , C 3 nb , and the switch SW 2 may be turned on to transmit the differential input voltage Vin to the upper plates of the capacitors C 1 na , C 1 nb , C 2 na , C 2 nb , C 3 na , C 3 nb , so as to establish a voltage Vn.

In other embodiments, when the switching signal Sswp is set at the first level, the first selection circuit 121 may output the corresponding voltages in the second voltage setting to the lower plates of the capacitors C 1 pa , Clpb, C 2 pa , C 2 pb , C 3 pa , C 3 pb , and switch SW 1 may be turned on to transmit the differential input voltage Vip to the upper plates of the capacitors C 1 pa , Clpb, C 2 pa , C 2 pb , C 3 pa , C 3 pb , so as to establish a voltage Vp; the second selection circuit 122 may output the corresponding voltage in the second voltage setting to the lower plates of the capacitors C 1 na , C 1 nb , C 2 na , C 2 nb , C 3 na , C 3 nb , and the switch SW 2 may be turned on to transmit the differential input voltage Vin to the upper plates of the capacitors C 1 na , C 1 nb , C 2 na , C 2 nb , C 3 na , C 3 nb , so as to establish a voltage Vn. When the switching signal Sswp is set at the second level, the first selection circuit 121 may output the corresponding voltages in the first voltage setting to the lower plates of the capacitors C 1 pa , Clpb, C 2 pa , C 2 pb , C 3 pa , C 3 pb , and switch SW 1 may be turned on to transmit the differential input voltage Vip to the upper plates of the capacitors C 1 pa , Clpb, C 2 pa , C 2 pb , C 3 pa , C 3 pb , so as to establish a voltage Vp; the second selection circuit 122 may output the corresponding voltage in the first voltage setting to the lower plates of the capacitors C 1 na , C 1 nb , C 2 na , C 2 nb , C 3 na , C 3 nb , and the switch SW 2 may be turned on to transmit the differential input voltage Vin to the upper plates of the capacitors C 1 na , C 1 nb , C 2 na , C 2 nb , C 3 na , C 3 nb , so as to establish a voltage Vn.

In the quantization stage, the analog-to-digital converter 1 may perform 3 conversions to generate the 3 bits of the digital output data Dout. The comparator 16 may compare the voltages Vp and Vn to generate 3 comparison results, and the control logic circuit 18 may store each comparison result as one bit of the digital output data Dout, and generate selection signals according to each comparison result, so as to set the multiplexers M 1 pa , M 1 pb and the multiplexers M 1 na , M 1 nb to update the voltages Vp and Vn. The comparison result may be binary “0” or binary “1”. For example, when converting the most significant bit, if the voltage Vp is higher than the voltage Vn, the comparator 16 may generate a binary “1” as the comparison result, and the control logic circuit 18 may store the binary “1” as the most significant bit and generate selection signals to set the first capacitor array 141 to output the ground voltage to the lower plates of the capacitor C 1 pa , Clpb, so as to pull down the voltage Vp, and generate selection signals to set the second capacitor array 142 to output the supply voltage to the lower plates of the capacitors C 1 na and C 1 nb , so as to pull up the voltage Vn. The updated voltage Vp will be less than the previous voltage Vp, and the updated voltage Vn will be higher than the previous voltage Vn. If the voltage Vp is less than the voltage Vn, the comparator 16 may generate a binary “0” as the comparison result, and the control logic circuit 18 may store the binary “0” as the most significant bit and generate a selection signal to set the first capacitor array 141 to output the supply voltage to the lower plates of the capacitor C 1 pa , Clpb, so as to pull up the voltage Vp, and generate a selection signal to set the second capacitor array 142 to output the ground voltage to the lower plates of the capacitors C 1 na and C 1 nb , so as to pull down the voltage Vn. The updated voltage Vp will be higher than the previous voltage Vp, and the updated voltage Vn will be less than the previous voltage Vn. The analog-to-digital converter 1 may sequentially compare and update the voltages Vp and Vn to generate 3 bits of the digital output data Dout, and output the digital output data Dout for the subsequent use.

FIG. 2 is a flowchart of a method 200 of operating the analog-to-digital converter 1 . The method 200 includes Steps S 202 and S 204 for resetting the first capacitor array 141 and the second capacitor array 142 using the two voltage settings during a plurality of sampling stages. Any reasonable Step change or adjustment is within the scope of the disclosure. Steps S 202 and S 204 are detailed as follows:

Step S 202 : In a first sampling stage, switch the switching signal Sswp to the first level for the first selection circuit 121 to output the first reference voltage V 1 to the first capacitor in each set of capacitors of the first capacitor array 141 and output the second reference voltage V 2 to the second capacitor in each set of capacitors of the first capacitor array 141 , and for the second selection circuit 122 to output the first reference voltage V 1 to the first capacitor in each set of capacitors of the second capacitor array 142 and output the second reference voltage V 2 to the second capacitor in each set of capacitors of the second capacitor array 142 ;

Step S 204 : In a second sampling stage, switch the switching signal Sswp to the second level for the first selection circuit 121 to output the second reference voltage V 2 to the first capacitor in each set of capacitors of the first capacitor array 141 and output the first reference voltage V 1 to the second capacitor in each set of capacitors of the first capacitor array 141 , and for the second selection circuit 122 to output the second reference voltage V 2 to the first capacitor in each set of capacitors of the second capacitor array 142 and output the first reference voltage V 1 to the second capacitor in each set of capacitors of the second capacitor array 142 .

The second sampling stage may be the sampling stage directly after the first sampling stage, or may be separated from the first sampling stage by several sampling stages. The method 200 is explained below with reference to the analog-to-digital converter 1 .

In the first sampling stage, the control logic circuit 18 switches the switching signal Sswp to the first level, and the first selection circuit 121 outputs the first reference voltage V 1 to the first capacitor C 1 pa of the first set of capacitors, the first capacitor C 2 pa of the second set of capacitors and the first capacitor C 3 pa of the third set of capacitors of the first capacitor array 141 , and outputs the second reference voltage V 2 to the second capacitor C 1 pb of the first set of capacitors, the second capacitor C 2 pb of the second set of capacitors and the second capacitor C 3 pb of the third set of capacitors of the first capacitor array 141 , and the second selection circuit 122 outputs the first reference voltage V 1 to the first capacitor C 1 na of the first set of capacitors, the first capacitor C 2 na of the second set of capacitors and the first capacitor C 3 na of the third set of capacitors of the second capacitor array 142 , and outputs the second reference voltage V 2 to the second capacitor C 1 nb of the first set of capacitors, the capacitor C 2 nb of the second set of capacitors and the second capacitor C 3 nb of the third set of capacitors of the second capacitor array 142 , as indicated in the first voltage setting in Table 1 (Step S 202 ).

In the second sampling stage, the control logic circuit 18 switches the switching signal Sswp to the second level, and the first selection circuit 121 outputs the second reference voltage V 2 to the first capacitor C 1 pa of the first set of capacitors, the first capacitor C 2 pa of the second set of capacitors and the first capacitor C 3 pa of the third set of capacitors of the first capacitor array 141 , and outputs the first reference voltage V 1 to the second capacitor C 1 pb of the first set of capacitors, the second capacitor C 2 pb of the second set of capacitors and the second capacitor C 3 pb of the third set of capacitors of the first capacitor array 141 , and the second selection circuit 122 outputs the second reference voltage V 2 to the first capacitor C 1 na of the first set of the capacitors, the first capacitor C 2 na of the second set of capacitors and the first capacitor C 3 na of the third set of capacitors of the second capacitor array 142 , and outputs the first reference voltage V 1 to the second capacitor C 1 nb of the first set of capacitors, the second capacitor C 2 nb of the second set of capacitors and the second capacitor C 3 nb of the third set of capacitors of the second capacitor array 142 , as indicated in the second voltage setting in Table 2 (Step S 204 ).

FIG. 3A is a circuit schematic of an analog-to-digital converter 3 according to another embodiment of the present invention. The difference between the analog-to-digital converter 3 and the analog-to-digital converter 1 lies in that the first capacitor C 1 pa of the first set of capacitors of the first capacitor array 341 of the analog-to-digital converter 3 is further split into a first capacitor portion C 1 pa 1 and a second capacitor portion C 1 pa 2 , the first capacitor C 1 na of the first set of capacitors of the second capacitor array 342 of the first selection circuit 321 is further split into a first capacitor portion C 1 na 1 and a second capacitor portion C 1 na 2 .

The first selection circuit 321 and the second selection circuit 322 may be implemented by one or more switches coupled to the reference voltages V 1 , V 2 and one or more multiplexers, but are not limited thereto. FIG. 3B is a schematic circuit diagram of an embodiment of the first selection circuit 321 or the second selection circuit 322 . Explanation below will be made with reference to the first selection circuit 321 . The second selection circuit 322 may be configured and operated according to a principle similar to the first selection circuit 321 . The first selection circuit 321 may include inverters 1 a 1 , 1 a 2 , 1 b 1 , 1 b 2 , 2 a , 2 b , 3 a , 3 b , multiplexers M 1 a 1 , M 1 a 2 , M 1 b 1 , M 1 b 2 , M 2 a , M 2 b , M 3 a , M 3 b , and switch circuits S 1 a 1 , S 1 a 2 , S 1 b 1 , S 1 b 2 , S 2 a , S 2 b , S 3 a , S 3 b . The inverters 1 a 1 , 1 a 2 , 1 b 1 , 1 b 2 , 2 a , 2 b , 3 a , 3 b may be coupled to the control logic circuit 18 and may be coupled to the multiplexers M 1 a 1 , M 1 a 2 , M 1 b 1 , M 1 b 2 , M 2 a , M 2 b , M 3 a , M 3 b , respectively. The multiplexers M 1 a 1 , M 1 a 2 , M 1 b 1 , M 1 b 2 , M 2 a , M 2 b , M 3 a , M 3 b may be coupled to the control logic circuit 18 and may be coupled to the switch circuits S 1 a 1 , S 1 a 2 , S 1 b 1 , S 1 b 2 , S 2 a , S 2 b , S 3 a , S 3 b , respectively. The switch circuits S 1 a 1 , S 1 a 2 , S 1 b 1 , S 1 b 2 , S 2 a , S 2 b , S 3 a , S 3 b may be coupled to the lower plates of the capacitors C 1 pa 1 , C 1 pa 2 , C 1 pb 1 , C 1 pb 2 , C 2 pa , C 2 pb , C 3 pa , C 3 pb of the first capacitor array 341 , respectively.

The inverters 1 a 1 , 1 a 2 , 1 b 1 , 1 b 2 , 2 a , 2 b , 3 a , 3 b may receive corresponding selection signals from the control logic circuit 18 , respectively. The multiplexers M 1 a 1 , M 1 a 2 , M 1 b 1 , M 1 b 2 , M 2 a , M 2 b , M 3 a , M 3 b may receive the corresponding selection signals from the control logic circuit 18 and inverses of the corresponding selection signals from the inverters 1 a 1 , 1 a 2 , 1 b 1 , 1 b 2 , 2 a , 2 b , 3 a , 3 b , and select ones of the corresponding selection signals and the inverses of the corresponding selection signal according to the switching signal Sswp to serve as corresponding multiplexer output signals, and output the corresponding multiplexer output signals to the switch circuits S 1 a 1 , S 1 a 2 , S 1 b 1 , S 1 b 2 , S 2 a , S 2 b , S 3 a , S 3 b . Each of the switch circuits S 1 a 1 , S 1 a 2 , S 1 b 1 , S 1 b 2 , S 2 a , S 2 b , S 3 a , S 3 b includes switches SV 1 and SV 2 . The switch SV 1 may receive the second reference voltage V 2 , and the switch SV 2 may receive the first reference voltage V 1 . Each of the switch circuits S 1 a 1 , S 1 a 2 , S 1 b 1 , S 1 b 2 , S 2 a , S 2 b , S 3 a , S 3 b may be controlled by the corresponding multiplexer output signals of the multiplexer M 1 a 1 , M 1 a 2 , M 1 b 1 , M 1 b 2 , M 2 a , M 2 b , M 3 a , M 3 b to output the first reference voltage V 1 or the second reference voltage V 2 .

The capacitance of the first capacitor portion of the first capacitor of a set of larger capacitors of the first capacitor array 341 may be substantially equal to a capacitance of the first capacitor of a set of smaller capacitors of the first capacitor array 341 ; and the capacitance of the first capacitor portion of the second capacitor of the set of larger capacitors of the first capacitor array 341 may be substantially equal to the capacitance of the first capacitor of the set of smaller capacitors of the first capacitor array 341 . For example, the capacitance of the first capacitor portion C 1 pa 1 of the first capacitor C 1 pa of the first set of capacitors of the first capacitor array 341 may be substantially equal to the capacitance “ 2 C” of the first capacitor C 2 pa of the second set of capacitors of the first capacitor array 341 ; and the capacitance of the first capacitor portion C 1 pb 1 of a second capacitor C 1 pb of the first set of capacitors of the first capacitor array 341 may be substantially equal to the capacitance “ 2 C” of the first capacitor C 2 pa of the second set of capacitors of the first capacitor array 341 . The capacitance of the second capacitor portion of the first capacitor of the set of larger capacitors of the first capacitor array 341 may be equal to the remaining capacitance of the first capacitor of the set of larger capacitors except for the first capacitor portion. For example, the capacitance of the second capacitor portion C 1 pa 2 of the first capacitor C 1 pa of the first capacitor array 341 may be equal to 1 C.

The capacitance of the first capacitor portion of the first capacitor of a set of larger capacitors of the second capacitor array 342 may be substantially equal to a capacitance of the first capacitor of a set of smaller capacitors of the second capacitor array 342 ; and the capacitance of the first capacitor portion of the second capacitor of the set of larger capacitors of the second capacitor array 342 may be substantially equal to the capacitance of the first capacitor of the set of smaller capacitors of the second capacitor array 342 . For example, the capacitance of the first capacitor portion C 1 na 1 of the first capacitor C 1 na of the first set of capacitors of the second capacitor array 342 may be substantially equal to the capacitance “ 2 C” of a first capacitor C 2 na of the second set of capacitors of the second capacitor array 342 ; and the capacitance of the first capacitor portion C 1 nb 1 of a second capacitor C 1 nb of the first set of capacitors of the second capacitor array 342 may be substantially equal to the capacitance “ 2 C” of the first capacitor C 2 na of the second set of capacitors of the second capacitor array 342 . The capacitance of the second capacitor portion of the first capacitor of the set of larger capacitors of the second capacitor array 342 may be equal to the remaining capacitance of the first capacitor of the set of larger capacitors except for the first capacitor portion. For example, the capacitance of the second capacitor portion C 1 na 2 of the first capacitor C 1 na of the second capacitor array 342 may be equal to 1 C.

The differences between the analog-to-digital converter 3 and the analog-to-digital converter 1 are explained as follows.

In the sampling stage, the first selection circuit 321 and the second selection circuit 322 may output the voltage in the first voltage setting or the second voltage setting to the capacitors C 1 pa 1 , C 1 pa 2 , C 1 pb 1 , C 1 pb 2 , C 2 pa , C 2 pb , C 3 pa , C 3 pb and capacitors C 1 na 1 , C 1 na 2 , C 1 nb 1 , C 1 nb 2 , C 2 na , C 2 nb , C 3 na , C 3 nb according to the switching signal Sswp. Table 3 and Table 4 respectively show the first voltage setting and the second voltage setting:

The analog-to-digital converter 3 may also be adopted in the method 200 . In the first sampling stage, the control logic circuit 18 switches the switching signal Sswp to the first level, and the first selection circuit 121 outputs the first reference voltage V 1 to the first capacitor portion C 1 pa 1 and the second capacitor portion C 1 pa 2 of the first capacitor C 1 pa , the first capacitor C 2 pa of the second set of capacitors and the first capacitor C 3 pa of the third set of capacitors of the first set of capacitors of the first capacitor array 341 , and outputs the second reference voltage V 2 to the first capacitor portion C 1 pb 1 and the second capacitor portion C 1 pb 2 of the second capacitor C 1 pb of the first set of capacitors, the second capacitor C 2 pb of the second set of capacitors and the second capacitor C 3 pb of the third set of capacitors of the first capacitor array 341 , the second selection circuit 122 outputs the first reference voltage V 1 to the first capacitor portion C 1 na 1 and the second capacitor portion C 1 na 2 of the first capacitor C 1 na of the first set of capacitors, the first capacitor C 2 na of the second set of capacitors and the first capacitor C 3 na of the third set of capacitors of the second capacitor array 342 , and outputs the second reference voltage V 2 to the first capacitor portion C 1 nb 1 and the second capacitor portion C 1 nb 2 of the second capacitor C 1 nb of the first set of capacitors, the capacitor C 2 nb of the second set of capacitors and the second capacitor C 3 nb of the third set of capacitors of the second capacitor array 342 (Step S 202 ).

In the second sampling stage, the control logic circuit 18 switches the switching signal Sswp to the second level, and the first selection circuit 121 outputs the second reference voltage V 2 to the first capacitor portion C 1 pa 1 and the second capacitor portion C 1 pa 2 of the first capacitor C 1 pa of the first set of capacitors, the first capacitor C 2 pa of the second set of capacitors and the first capacitor C 3 pa of the third set of capacitors of the first capacitor array 341 , and outputs the first reference voltage V 1 to the first capacitor portion C 1 pb 1 and the second capacitor portion C 1 pb 2 of the second capacitor C 1 pb of the first set of capacitors, the second capacitor C 2 pb of the second set of capacitors and the second capacitor C 3 pb of the third set of capacitors of the first capacitor array 341 , and the second selection circuit 122 outputs the second reference voltage V 2 to the first capacitor portion C 1 na 1 and the second capacitor portion C 1 na 2 of the first capacitor C 1 na of the first set of the capacitors, the first capacitor C 2 na of the second set of capacitors and the first capacitor C 3 na of the third set of capacitors of the second capacitor array 342 , and outputs the first reference voltage V 1 to the first capacitor portion C 1 nb 1 and the second capacitor portion C 1 nb 2 of the second capacitor C 1 nb of the first set of capacitors, the second capacitor C 2 nb of the second set of capacitors and the second capacitor C 3 nb of the third set of capacitors of the second capacitor array 342 (Step S 204 ).

Since the analog-to-digital converters 1 , 3 and the operation method 200 use the first voltage setting and the second voltage setting in a uniform manner to reset the first capacitor arrays 141 , 341 and the second capacitor arrays 142 , 342 in a plurality of sampling stages, the transfer curve of the analog-to-digital converter is uniformly switched between the two settings, canceling out the average nonlinearity error in the digital output data Dout, and reducing the differential nonlinearity error and the integral nonlinearity error owing to the capacitance mismatch.

FIGS. 4A and 4B show a flowchart of a method 400 of operating the analog-to-digital converter 3 . The method 400 includes Steps S 402 to S 428 , and may be used after Step S 204 of the method 200 . That is, the first capacitor array 341 and the second capacitor array 342 are reset during the second sampling stage according to the second voltage setting as indicated in Table 4. Steps S 402 , S 412 , and S 422 are used to set the first capacitor array 341 and the second capacitor array 342 in the first conversion period. Steps S 414 to S 418 and S 424 to S 428 are used to set the first capacitor array 341 and the second capacitor array 342 in the second conversion period. Any reasonable Step change or adjustment is within the scope of the disclosure. Steps S 402 to S 428 are detailed as follows:

Step S 402 : Determine whether the voltage Vp is higher than the voltage Vn; if so, go to Step S 412 ; if not, go to Step S 422 ;

Step S 412 : In a first conversion period, the first selection circuit 321 outputs the second reference voltage V 2 to the second capacitor C 1 pb of the set of larger capacitor of the first capacitor array 341 , the second selection circuit 322 outputs the first reference voltage V 1 to the first capacitor C 1 na of the set of larger capacitors of the second capacitor array 342 ;

Step S 414 : Determine whether the voltage Vp is less than the voltage Vn; if so, go to Step S 416 ; if not, go to Step S 418 ;

Step S 416 : In a second conversion period, the first selection circuit 321 outputs the first reference voltage V 1 to the first capacitor portion C 1 pa 1 of the first capacitor C 1 pa of the set of larger capacitors of the first capacitor array 341 or the first capacitor portion C 1 pb 1 of the second capacitor C 1 pb of the set of larger capacitors of the first capacitor array 341 , and the second selection circuit 322 outputs the second reference voltage V 2 to the first capacitor portion C 1 na 1 of the first capacitor C 1 na of the set of larger capacitors of the second capacitor array 342 or the first capacitor portion C 1 nb 1 of the second capacitor C 1 nb of the set of larger capacitors of the second capacitor array 342 .

Step S 418 : In a second conversion period, the first selection circuit 321 outputs the second reference voltage V 2 to the second capacitor C 1 pb of the set of smaller capacitor of the first capacitor array 341 , the second selection circuit 322 outputs the first reference voltage V 1 to the first capacitor C 1 na of the set of smaller capacitors of the second capacitor array 342 .

Step S 422 : In a first conversion period, the first selection circuit 321 outputs the first reference voltage V 1 to the first capacitor C 1 pa of the set of larger capacitor of the first capacitor array 341 , the second selection circuit 322 outputs the second reference voltage V 2 to the second capacitor C 1 nb of the set of larger capacitors of the second capacitor array 342 ;

Step S 424 : Determine whether the voltage Vp is higher than the voltage Vn; if so, go to Step S 426 ; if not, go to Step S 428 ;

Step S 426 : In a second conversion period, the first selection circuit 321 outputs the second reference voltage V 2 to the first capacitor portion C 1 pa 1 of the first capacitor C 1 pa of the set of larger capacitors of the first capacitor array 341 or the first capacitor portion C 1 pb 1 of the second capacitor C 1 pb of the set of larger capacitors of the first capacitor array 341 , and the second selection circuit 322 outputs the first reference voltage V 1 to the first capacitor portion C 1 na 1 of the first capacitor C 1 na of the set of larger capacitors of the second capacitor array 342 or the first capacitor portion C 1 nb 1 of the second capacitor C 1 nb of the set of larger capacitors of the second capacitor array 342 .

Step S 428 : In a second conversion period, the first selection circuit 321 outputs the first reference voltage V 1 to the first capacitor C 2 pa of the set of smaller capacitor of the first capacitor array 341 , and the second selection circuit 322 outputs the second reference voltage V 2 to the second capacitor C 2 nb of the set of smaller capacitors of the second capacitor array 342 .

The method 400 is explained as follows with reference to the analog-to-digital converter 3 . The first selection circuit 321 and the second selection circuit 322 may output the voltages in the second voltage setting to the capacitors C 1 pa 1 , C 1 pa 2 , C 1 pb 1 , C 1 pb 2 , C 2 pa , C 2 pb , C 3 pa , C 3 pb and capacitors C 1 na 1 , C 1 na 2 , C 1 nb 1 , C 1 nb 2 , C 2 na , C 2 nb , C 3 na , C 3 nb in the sampling stage, as indicated in Table 4. The first reference voltage V 1 may be the supply voltage and the second reference voltage V 2 may be the ground voltage. After the quantization stage starts, during the first conversion period, the comparator 16 determines whether the voltage Vp is higher than the voltage Vn (Step S 402 ).

If the voltage Vp is higher than the voltage Vn, the first selection circuit 321 outputs the second reference voltage V 2 to the first capacitor portion C 1 pb 1 and the second capacitor portion C 1 pb 2 of the second capacitor C 1 pb of the first set of capacitors of the first capacitor array 341 , and the second selection circuit 322 outputs the first reference voltage V 1 to the first capacitor portion C 1 na 1 and the second capacitor portion C 1 na 2 of the first capacitor C 1 na of the first set of capacitors of the second capacitor array 342 , as indicated in Table 5 (Step S 412 ):

During the second conversion period, the comparator 16 determines whether the voltage Vp is less than the voltage Vn (Step S 414 ). If the voltage Vp is less than the voltage Vn, the first selection circuit 321 outputs the first reference voltage V 1 to the first capacitor portion C 1 pa 1 of the first capacitor C 1 pa of the first set of capacitors in the capacitor array 341 or the first capacitor portion C 1 pb 1 of the second capacitor C 1 pb of the first set of capacitors of the first capacitor array 341 , the second selection circuit 322 outputs the second reference voltage V 2 to the first capacitor portion C 1 na 1 of the first capacitor C 1 na of the first set of capacitors of the second capacitor array 342 or the first capacitor portion C 1 nb 1 of the second capacitor C 1 nb of the first set of capacitors of the second capacitor array 342 (Step S 416 ).

In some embodiments, the first selection circuit 321 outputs the first reference voltage V 1 to the first capacitor portion C 1 pb 1 and the second capacitor portion C 1 pa 1 of the first capacitor C 1 pa of the first set of capacitors of the first capacitor array 341 , and the second selection circuit 322 outputs the second reference voltage V 2 to the first capacitor portion C 1 na 1 and the second capacitor portion C 1 nb 1 of the second capacitor C 1 nb of the first set of capacitors of the second capacitor array 342 , as indicated in Table 6:

In other embodiments, the first selection circuit 321 may output the first reference voltage V 1 to the first capacitor portion C 1 pb 1 and the second capacitor portion V 1 of the second capacitor C 1 pb of the first set of capacitors of the first capacitor array 341 , so as to switch the first capacitor portion C 1 pb 1 back to the reset value thereof (V 1 ), and the second selection circuit 322 may output the second reference voltage V 2 to the first capacitor portion C 1 na 1 and the second capacitor portion C 1 na 1 of the first capacitor C 1 na of the first set of capacitors of the second capacitor array 342 , so as to switch the second capacitor portion C 1 na 1 back to the reset value thereof (V 2 ), as indicated in Table 7 (Step S 412 ):

In other embodiments, the first selection circuit 321 and the second selection circuit 322 may respectively output the voltages of the voltage settings as indicated in Table 7 and Table 6 to the first capacitor array 341 and the second capacitor array 342 according to a uniform sequence. The uniform order may be an alternating order or a random order. When the uniform sequence is an alternating sequence, the first selection circuit 321 and the second selection circuit 322 may respectively output the voltage settings in Table 7 and Table 6 to the first capacitor array 341 and the second capacitor array 342 during a plurality of conversion periods. When the uniform sequence is a random sequence, the first selection circuit 321 and the second selection circuit 322 may randomly output the voltage settings in Table 7 and Table 6 to the first capacitor array 341 and the second capacitor array 342 during a plurality of conversion periods, respectively. The probabilities of employing the voltage settings in Table 7 and Table 6 are substantially equal to each other.

In Step S 414 , if the comparator 16 determines that the voltage Vp is not less than the voltage Vn, the first selection circuit 321 outputs the second reference voltage V 2 to the second capacitor C 2 pb of the second set of capacitors of the first capacitor array 341 , and the second selection circuit 322 outputs the first reference voltage V 1 to the first capacitor C 2 na of the second set of capacitors of the second capacitor array 342 , as indicated in Table 8 (Step S 418 ).

In Step S 402 , if the voltage Vp is not higher than the voltage Vn, the first selection circuit 321 outputs the first reference voltage V 1 to the first capacitor portion C 1 pa 1 and the second capacitor portion C 1 pa 2 of the first capacitor C 1 pa of the first set of capacitors of the first capacitor array 341 , and the second selection circuit 322 outputs the second reference voltage V 2 to the first capacitor portion C 1 nb 1 and the second capacitor portion C 1 nb 2 of the second capacitor C 1 nb of the first set of capacitors of the second capacitor array 342 , as indicated in Table 9 (Step S 422 ):

During the second conversion period, the comparator 16 determines whether the voltage Vp is higher than the voltage Vn (Step S 424 ). If the voltage Vp is higher than the voltage Vn, the first selection circuit 321 outputs the second reference voltage V 2 to the first capacitor portion C 1 pa 1 of the first capacitor C 1 pa of the first set of capacitors in the capacitor array 341 or the first capacitor portion C 1 pb 1 of the second capacitor C 1 pb of the first set of capacitors of the first capacitor array 341 , the second selection circuit 322 outputs the first reference voltage V 1 to the first capacitor portion C 1 na 1 of the first capacitor C 1 na of the first set of capacitors of the second capacitor array 342 or the first capacitor portion C 1 nb 1 of the second capacitor C 1 nb of the first set of capacitors of the second capacitor array 342 (Step S 426 ). In some embodiments, the first selection circuit 321 may output the second reference voltage V 2 to the first capacitor portion C 1 pa 1 and the second capacitor portion V 1 of the first capacitor C 1 pa of the first set of capacitors of the first capacitor array 341 , so as to switch the first capacitor portion C 1 pa 1 back to the reset value thereof (V 1 ), and the second selection circuit 322 may output the first reference voltage V 1 to the first capacitor portion C 1 nb 1 and the second capacitor portion C 1 nb 1 of the second capacitor C 1 nb of the first set of capacitors of the second capacitor array 342 , so as to switch the second capacitor portion C 1 na 1 back to the reset value thereof (V 2 ), as indicated in Table 10:

In other embodiments, the first selection circuit 321 outputs the second reference voltage V 2 to the first capacitor portion C 1 pb 1 of the second capacitor C 1 pb of the first set of capacitors of the first capacitor array 341 , and the second selection circuit 322 outputs the first reference voltage V 1 to the first capacitor portion C 1 na 1 of the first capacitor C 1 na of the first set of capacitors of the second capacitor array 342 , as indicated in Table 11:

In other embodiments, the first selection circuit 321 and the second selection circuit 322 may respectively output the voltages of the voltage settings as indicated in Table 10 and Table 11 to the first capacitor array 341 and the second capacitor array 342 according to a uniform sequence. The uniform order may be an alternating order or a random order. When the uniform sequence is an alternating sequence, the first selection circuit 321 and the second selection circuit 322 may respectively output the voltage settings in Table 10 and Table 11 to the first capacitor array 341 and the second capacitor array 342 during a plurality of conversion periods. When the uniform sequence is a random sequence, the first selection circuit 321 and the second selection circuit 322 may randomly output the voltage settings in Table 10 and Table 11 to the first capacitor array 341 and the second capacitor array 342 during a plurality of conversion periods, respectively. The probabilities of employing the voltage settings in Table 10 and Table 11 are substantially equal to each other.

In Step S 424 , if the comparator 16 determines that the voltage Vp is no higher than the voltage Vn, the first selection circuit 321 outputs the first reference voltage V 1 to the first capacitor C 2 pa of the second set of capacitors of the first capacitor array 341 , and the second selection circuit 322 outputs the second reference voltage V 2 to the second capacitor C 2 nb of the second set of capacitors of the second capacitor array 342 , as indicated in Table 12 (Step S 418 ).

In other embodiments, the first selection circuit 321 and the second selection circuit 322 use a second voltage setting during the sampling stage to reset the capacitors C 1 pa 1 , C 1 pa 2 , C 1 pb 1 , C 1 pb 2 , C 2 pa , C 2 pb , C 3 pa , C 3 pb and capacitors C 1 na 1 , C 1 na 2 , C 1 nb 1 , C 1 nb 2 , C 2 na , C 2 nb , C 3 na , C 3 nb , as indicated in Table 3. The first reference voltage V 1 may be the supply voltage and the second reference voltage V 2 may be the ground voltage. After the quantization stage starts, during the first conversion period, the comparator 16 determines whether the voltage Vp is higher than the voltage Vn (Step S 402 ).

In the embodiment of the method 400 , the second conversion period is not limited to be immediately after or immediately subsequent to the first conversion period. In some embodiments, the second conversion period may be immediately subsequent to the first conversion period. In other embodiments, the second conversion period and the first conversion period may be separated by a time interval. In some embodiments, if the capacitor arrays are configured into a larger number of bits (e.g., 10-bits), the first capacitor and the second capacitor of a larger set of capacitors may be split into a plurality of capacitor portions, respectively. The respective capacitances are substantially equal to the capacitances of one or more of smaller capacitors, and the method 400 may be used to perform an analog-to-digital conversion.

The method 400 may be used with the method 200 or the sampling method in the related art. When the method 400 is used in conjunction with the sampling method in the related art, the method 400 may reduce the differential nonlinearity error and integral non-linearity error of the first capacitor array 341 and the second capacitor array 342 owing to the capacitor mismatch between different sets of capacitors. When the method 400 is used in conjunction with the method 200 , the method 200 serves to reduce the nonlinearity error owing to the capacitance mismatch in the same set of capacitors, and the method 400 serves to reduce the nonlinearity error owing to the capacitance mismatch between different sets of capacitors. Therefore, the overall differential nonlinearity error and integral nonlinearity error are reduced. In one example, the first capacitor array 341 and the second capacitor array 342 both include 10-bit capacitors, each set of capacitors has a capacitance with a standard deviation of 2% tolerance, the first capacitor and the second capacitor of each set of capacitors are operated in a uniform sequence in several sampling stages by the method 200 and the method 400 , and a capacitor portion of a set of larger capacitors is switched back to the reset value in a non-MSB conversion upon satisfying the condition set in the method 400 . In such a case, the maximum differential nonlinearity error will be reduced from 0.37LSB to 0.22LSB, and the maximum integral nonlinearity error will be reduced from 0.8LSB to 0.48LSB.

The present invention is not limited to the 3-bit SAR ADC, and those skilled in the art may also apply the methods 200 , 400 to other sizes of SAR ADCs according to the principle of the present invention. The analog-to-digital converters 1 , 3 and the operation method 200 reset the first capacitor arrays 141 , 341 and the second capacitor arrays 142 , 342 in a uniformly manner during a plurality of sampling stages using the first voltage setting and the second voltage setting. The converter 3 and the operation method 400 employ the switch-back technique to switch the first capacitor array 341 and the second capacitor array 342 , so as to reduce the differential non-linearity error and integral non-linearity owing to the capacitance mismatch between the same set of capacitors or different sets of capacitors, significantly enhancing the linearity of the SAR ADC.

Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.