Three dimension memory device and ternary content addressable memory cell thereof

The disclosure relates to a three dimension memory device and a ternary content addressable memory cell thereof. Particularly, the disclosure relates to a three dimension memory device and a ternary content addressable memory cell thereof, in which power consumption in a search operation can be relatively saved.

In electronic devices, in order to provide a highly expressive look-up table, ternary content addressable memory cells with a high density and a high speed have become an important architecture.

It is a common choice to construct the ternary content addressable memory cells by utilizing non-volatile memory. However, electrical properties, such as the bit error rate, of the non-volatile memory are an important parameter to be considered.

In the conventional technical field, it is common that the ternary content addressable memory cells are constructed by utilizing an NOR type flash memory. However, with the limitation of the circuit structure of the NOR type flash memory, it may be difficult to a certain extent to configure a ternary content addressable memory cell array with a sufficiently high density by utilizing the NOR type flash memory.

The disclosure provides a three dimension memory device and a ternary content addressable memory cell thereof, in which power consumption required for a search operation can be reduced.

The ternary content addressable memory cell of the disclosure includes a first memory cell, a second memory cell, a first search switch, and a second search switch. The first memory cell is disposed in a first AND type flash memory line. The second memory cell is disposed in a second AND type flash memory line. The first search switch is coupled between a first bit line corresponding to the first AND type flash memory line and a match line, and is controlled by a first search signal to be turned on or cut off. The second search switch is coupled between a second bit line corresponding to the second AND type flash memory line and the match line, and is controlled by a second search signal to be turned on or cut off.

The three dimension memory device of the disclosure includes an AND type flash memory bank and at least one ternary content addressable memory cell. The AND type flash memory bank includes at least one memory cell array tile. The ternary content addressable memory cell includes a first memory cell, a second memory cell, a first search switch, and a second search switch. The first memory cell is disposed in a first AND type flash memory line. The second memory cell is disposed in a second AND type flash memory line. The first search switch is coupled between a first bit line corresponding to the first AND type flash memory line and a match line, and is controlled by a first search signal to be turned on or cut off. The second search switch is coupled between a second bit line corresponding to the second AND type flash memory line and the match line, and is controlled by a second search signal to be turned on or cut off.

Based on the foregoing, in the three dimension memory device of the disclosure, two memory cells in different AND type flash memory lines are combined with each other and accompanied with the corresponding bit line switches to form the ternary content addressable memory cell. The bit line switches are taken as the search switches that reduce the power consumption required in the search operation of the ternary content addressable memory cell. Moreover, with the bit line switches taken as the search switches, not only may the layout area be saved, but the reliability may also be increased, effectively improving the overall performance of the ternary content addressable memory cell.

To make the aforementioned more comprehensible, several embodiments accompanied with drawings are described in detail as follows.

The accompanying drawings are included to provide a further understanding of the disclosure, and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the disclosure and, together with the description, serve to explain the principles of the disclosure.

FIG. 1 is a schematic diagram illustrating a ternary content addressable memory cell according to an embodiment of the disclosure.

FIG. 2 is a schematic diagram illustrating an equivalent circuit of the ternary content addressable memory cell 100 in the embodiment of FIG. 1 of the disclosure.

FIG. 3A to FIG. 5C are respectively schematic diagrams illustrating implementations of search operations of ternary content addressable memory cells according to embodiments of the disclosure.

FIG. 6A and FIG. 6B are schematic diagrams illustrating different configurations of search switches of a three dimension memory device and a ternary content addressable memory cell according to embodiments of the disclosure.

FIG. 7 is a schematic diagram illustrating a different configuration of a three dimension memory device and a ternary content addressable memory cell according to an embodiment of the disclosure.

Reference may be made to FIG. 1 , which is a schematic diagram illustrating a ternary content addressable memory cell according to an embodiment of the disclosure. A ternary content addressable memory cell 100 is disposed in an AND type flash memory device. The ternary content addressable memory cell 100 includes memory cells MC 1 , MC 2 , search switches BLT 1 , BLT 2 , and source line switches SLT 1 , SLT 2 . In this embodiment, the search switches BLT 1 , BLT 2 and the source line switches SLT 1 , SLT 2 may each be constructed by applying a transistor, for example, an N-type transistor. The memory cells MC 1 , MC 2 may be flash memory cells.

The memory cells MC 1 , MC 2 are respectively disposed in different AND type flash memory lines 110 and 120 . The search switch BLT 1 is coupled between a bit line LBL 1 corresponding to the AND type flash memory line 110 and a match line ML. The search switch BLT 2 is coupled between a bit line LBL 2 corresponding to the AND type flash memory line 120 and the match line ML. In this embodiment, the search switches BLT 1 , BLT 2 are bit line switches of the AND type flash memory device, and the match line ML may be a global bit line. The search switch BLT 1 is controlled by a search signal SL to be turned on or cut off, and the search switch BLT 2 is controlled by a search signal SLB to be turned on or cut off. Based on different search conditions, the search signal SL and the search signal SLB may be different voltage combinations. For example, during a search operation of a first logic state (e.g., logic 1), the search signals SL and SLB may respectively be a logic high voltage and a logic low voltage; during a search operation of a second logic state (e.g., logic 0), the search signals SL and SLB may respectively be a logic low voltage and a logic high voltage; and during a search operation of a third logic state (e.g., don't care), the search signals SL and SLB may each be a logic low voltage.

In addition, the source line switch SLT 1 is coupled between a source line LSL 1 corresponding to the AND type flash memory line 110 and a reference ground voltage VSS. The source line switch SLT 2 is coupled between a source line LSL 2 corresponding to the AND type flash memory line 120 and the reference ground voltage VSS. The source line switches SLT 1 , SLT 2 are respectively controlled by control signals CT 1 , CT 2 . During the search operation of the ternary content addressable memory cell 100 , the source line switches SLT 1 , SLT 2 may be turned on according to the control signals CT 1 , CT 2 . The source line switches SLT 1 , SLT 2 may be coupled to a common source line, and may receive the reference ground voltage VSS through the common source line.

In this embodiment, the memory cells MC 1 , MC 2 are coupled to the same word line WL 0 . In other embodiments of the disclosure, the memory cells MC 1 , MC 2 may also be respectively coupled to different word lines, which is not particularly limited.

In the following, reference may be made to FIG. 2 , which is a schematic diagram illustrating an equivalent circuit of the ternary content addressable memory cell 100 in the embodiment of FIG. 1 of the disclosure. During the search operation, on the basis that the source line switches SLT 1 , SLT 2 are each turned on, the memory cells MC 1 , MC 2 may each receive the reference ground voltage VSS at one end. The memory cells MC 1 , MC 2 are respectively coupled to the search switches BLT 1 , BLT 2 at the other end. The search switches BLT 1 , BLT 2 are coupled between the memory cells MC 1 , MC 2 and the match line ML. The search switches BLT 1 and BLT 2 are respectively controlled by the search signals SL and SLB.

For the detailed actions of the search operation, reference may be made to FIG. 3A to FIG. 5C , which are respectively schematic diagrams illustrating implementations of search operations of ternary content addressable memory cells according to embodiments of the disclosure. In FIG. 3A to FIG. 3C , a ternary content addressable memory cell 300 records data in the first logic state, the memory cell MC 1 is in a programmed state, and the memory cell MC 2 is in an erased state. In an initial time interval before the search operation of the first logic state, a match signal on the match line ML may be pre-charged to a reference voltage, where the reference voltage is greater than the reference ground voltage VSS.

In FIG. 3A , during the search operation of the first logic state, the search signal SL is a logic high voltage, and the search signal SLB is a logic low voltage. At this time, on the basis that the memory cell MC 1 is cut off, and the search switch BLT 2 is also cut off, no conductive path is present between the match line ML and the reference ground voltage VSS. Therefore, the match signal on the match line ML may be substantially maintained at the level of the reference voltage without change. At this time, it may be determined that the search result of the search operation of the first logic state is matched.

In FIG. 3B , during the search operation of the second logic state, the search signal SL is a logic low voltage, and the search signal SLB is a logic high voltage. At this time, on the basis that the memory cell MC 2 and the search switch BLT 2 are each turned on, the memory cell MC 2 and the search switch BLT 2 form a conductive path between the match line ML and the reference ground voltage VSS. Therefore, the match signal on the match line ML may drop to be equal to the reference ground voltage VSS. At this time, it may be determined that the search result of the search operation of the second logic state is un-matched.

In FIG. 3C , during the search operation of the third logic state, the search signal SL is a logic low voltage, and the search signal SLB is also a logic low voltage. At this time, on the basis that the memory cell MC 1 and the search switches BLT 2 , BLT 1 are each cut off, no conductive path is present between the match line ML and the reference ground voltage VSS. Therefore, the match signal on the match line ML may be substantially maintained at the level of the reference voltage without change. At this time, it may be determined that the search result of the search operation of the third logic state is matched.

In FIG. 4A to FIG. 4C , a ternary content addressable memory cell 400 records data in the second logic state, the memory cell MC 2 is the programmed state, and the memory cell MC 1 is the erased state. In an initial time interval before the search operation of the first logic state, the match signal on the match line ML may be pre-charged to a reference voltage, where the reference voltage is greater than the reference ground voltage VSS.

In FIG. 4A , during the search operation of the first logic state, the search signal SL is a logic high voltage, and the search signal SLB is a logic low voltage. At this time, on the basis that the memory cell MC 1 and the search switch BLT 1 are each turned on, the memory cell MC 1 and the search switch BLT 1 form a conductive path between the match line ML and the reference ground voltage VSS. Therefore, the match signal on the match line ML may drop to be equal to the reference ground voltage VSS. At this time, it may be determined that the search result of the search operation of the second logic state is un-matched.

In FIG. 4B , during the search operation of the second logic state, the search signal SL is a logic low voltage, and the search signal SLB is a logic high voltage. At this time, on the basis that the memory cell MC 2 and the search switch BLT 1 are each cut off, no conductive path is present between the match line ML and the reference ground voltage VSS. Therefore, the match signal on the match line ML may be maintained equal to the reference voltage without change. At this time, it may be determined that the search result of the search operation of the second logic state is matched.

In FIG. 4C , during the search operation of the third logic state, the search signal SL is a logic low voltage, and the search signal SLB is also a logic low voltage. At this time, on the basis that the memory cell MC 2 and the search switch BLT 2 , BLT 1 are each cut off, no conductive path is present between the match line ML and the reference ground voltage VSS. Therefore, the match signal on the match line ML may be substantially maintained at the level of the reference voltage without change. At this time, it may be determined that the search result of the search operation of the third logic state is matched.

In FIG. 5A to FIG. 5C , a ternary content addressable memory cell 500 records data in the third logic state, and the memory cells MC 1 , MC 2 are each in a programmed state. In an initial time interval before the search operation of the third logic state, the match signal on the match line ML may be pre-charged to a reference voltage, where the reference voltage is greater than the reference ground voltage VSS.

In FIG. 5A , during the search operation of the first logic state, the search signal SL is a logic high voltage, and the search signal SLB is a logic low voltage. At this time, on the basis that the memory cells MC 1 , MC 2 are each cut off, and the search switch BLT 2 is also cut off, no conductive path is present between the match line ML and the reference ground voltage VSS. Therefore, the match signal on the match line ML may be substantially maintained at the level of the reference voltage without change. At this time, it may be determined that the search result of the search operation of the first logic state is matched.

In FIG. 5B , during the search operation of the second logic state, the search signal SL is a logic low voltage, and the search signal SLB is a logic high voltage. At this time, on the basis that the memory cells MC 1 , MC 2 and the search switch BLT 1 are each cut off, no conductive path is present between the match line ML and the reference ground voltage VSS. Therefore, the match signal on the match line ML may be substantially maintained at the level of the reference voltage without change. At this time, it may be determined that the search result of the search operation of the third logic state is matched.

In FIG. 5C , during the search operation of the third logic state, the search signal SL is a logic low voltage, and the search signal SLB is also a logic low voltage. At this time, on the basis that the memory cells MC 1 , MC 2 and the search switches BLT 2 , BLT 1 are each cut off, no conductive path is present between the match line ML and the reference ground voltage VSS. Therefore, the match signal on the match line ML may be substantially maintained at the level of the reference voltage without change. At this time, it may be determined that the search result of the search operation of the third logic state is matched.

It is worth noting that, in the embodiments of FIG. 3A to FIG. 5C , the first logic state is complementary to the second logic state, and the third logic state is don't care. To be specific, the first logic state may be logic 1 (or logic 0), and the second logic state may be logic 0 (or logic 1).

In addition, in other embodiments of the disclosure, during the search operations of the various states, the configuration of the voltage values of the search signals SL and SLB may be different from the above description. In other embodiments of the disclosure, in the search operation of the first logic state, the search signals SL and SLB may respectively be a logic low voltage and a logic high voltage; in the search operation of the second logic state, the search signals SL and SLB may respectively be a logic high voltage and a logic low voltage; and in the search operation of the third logic state, the search signals SL and SLB may each be a logic high voltage. Moreover, when the ternary content addressable memory cell records data in the third logic state, the memory cells MC 1 , MC 2 are each in an erased state. Under such conditions, in the search operations of the logic states, when the match signal on the match line ML is maintained equal to the reference voltage, it means that the search result is un-matched; and when the match signal on the match line ML drops to the reference ground voltage, it means that the search result is matched.

In the following, reference may be made to FIG. 6A and FIG. 6B , which are schematic diagrams illustrating different configurations of search switches of a three dimension memory device and a ternary content addressable memory cell according to embodiments of the disclosure. In FIG. 6A , a three dimension memory device 600 has a memory bank, and the memory bank includes a plurality of memory cell array tiles TL 1 , TL 2 . The memory cell array tiles TL 1 , TL 2 respectively have corresponding bit line switch areas 610 , 620 . Bit line switches BLT 5 to BLT 8 are in the bit line switch area 610 , and bit line switches BLT 1 to BLT 4 are in the bit line switch area 620 .

One or more ternary content addressable memory cells may be disposed in the three dimension memory device 600 . In this embodiment, corresponding to one of the ternary content addressable memory cells, the bit line switches BLT 1 , BLT 2 may serve as two search switches of the ternary content addressable memory cell. In other words, two search switches corresponding to the same ternary content addressable memory cell may be disposed in the same memory cell array tile TL 2 . The bit line switches BLT 1 and BLT 2 are respectively controlled by the search signals SL and SLB.

It is worth noting that, in this embodiment, the bit line switches BLT 1 to BLT 4 and the bit line switches BLT 5 to BLT 8 may be commonly coupled to a global bit line GBL.

In FIG. 6B , the two search switches corresponding to one ternary content addressable memory cell may be the bit line switches BLT 1 and BLT 5 . In other words, the two search switches corresponding to the same ternary content addressable memory cell may also be respectively disposed in the different memory cell array tiles TL 1 , TL 2 . The bit line switches BLT 1 and BLT 5 are respectively controlled by the search signals SL and SLB.

In the following, reference may be made to FIG. 7 , which is a schematic diagram illustrating a different configuration of a three dimension memory device and a ternary content addressable memory cell according to an embodiment of the disclosure. In FIG. 7 , a three dimension memory device 700 has a memory bank, and the memory bank includes a plurality of memory cell array tiles TL 1 , TL 2 . The memory cell array tiles TL 1 and TL 2 respectively have corresponding bit line switch areas 710 and 720 . Bit line switches BLT 51 to BLT 81 and BLT 52 to BLT 82 are in the bit line switch area 710 , and bit line switches BLT 11 to BLT 41 and BLT 12 to BLT 42 are in the bit line switch area 720 .

In this embodiment, a plurality of ternary content addressable memory cells may be disposed in the three dimension memory device 700 . A first ternary content addressable memory cell includes the memory cells MC 1 , MC 2 . The memory cells MC 1 , MC 2 are disposed in the same memory cell array tile TL 2 . Moreover, the memory cells MC 1 , MC 2 are arranged in pairs in two adjacent memory lines. Corresponding to the memory cells MC 1 and MC 2 , the bit line switches BT 21 and BT 31 may serve as search switches. The bit line switches BT 21 and BT 31 are commonly coupled to the global bit line GBL. The global bit line GBL may serve as a match line of the ternary content addressable memory cell.

Furthermore, a second ternary content addressable memory cell includes memory cells MC 3 , MC 4 . The memory cells MC 3 , MC 4 are respectively disposed in the different memory cell array tiles TL 1 , TL 2 . Corresponding to the memory cells MC 3 and MC 4 , the bit line switches BT 12 and BT 52 may serve as the search switches. It is worth noting that the bit line switches BT 12 and BT 52 are commonly coupled to the global bit line GBL. The global bit line GBL may serve as a match line of the ternary content addressable memory cell.

It is worth noting that, in the embodiments of the disclosure, one or more ternary content addressable memory cells may be disposed in the three dimension memory device. The three dimension memory device may have a plurality of memory cell array tiles. The ternary content addressable memory cells may each be disposed in a single memory cell array tile, or may as well be scattered in a plurality of different memory cell array tiles, which is not particularly limited.

In summary of the foregoing, the ternary content addressable memory cell of the disclosure is disposed in the AND type flash memory device. The bit line switches is taken as the search switches, and the global bit line is taken as the match line. Accordingly, the voltages of the search signals received by the search switches may be less than the voltages on the corresponding word lines, saving the required power consumption. In addition, a single bit line switch may be constructed by utilizing a single transistor. Moreover, under the premise that it is not required to increase the voltages of the search signals, the configuration of the level shifter circuit may be omitted, effectively reducing the circuit area. Furthermore, in the search operations, the search switches provide at most one current path through the corresponding bit line, effectively increasing the reliability of the circuit.

It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed embodiments without departing from the scope or spirit of the disclosure. In view of the foregoing, it is intended that the disclosure covers modifications and variations provided that they fall within the scope of the following claims and their equivalents.