Low intermediate frequency transmitter

Multiple input multiple output (MIMO) transceivers often support wide transmitter bandwidths for 32 or 64 antenna systems. The transmitter bandwidth can be, for example, two to three times wider than the receiver bandwidth to account for digital predistortion which compensates for non-linearities in power amplifiers in the transmitter signal chain. In radio frequency (RF) sampling transmitters, transmitting a signal in a particular frequency band creates an image, that is, an undesired signal, in a nearby frequency band. For example, an RF sampling digital-to-analog converter (DAC) with a sampling rate of six giga-samples per second transmitting in a 2.6 gigaHertz (GHz) band generates an image in the 3.4 GHz band. A sharp bandpass filter is required to attenuate the signal in the image band while retaining the signal of interest, which increases the area, power consumption, and cost of the transmitter. Traditional zero intermediate frequency architectures, sometimes called direct conversion or homodyne architectures, use a local oscillator set at the desired carrier frequency to directly down convert the received signal to the baseband. These traditional zero intermediate frequency architectures do not require a sharp bandpass filter but require multiple clock signals as well as image reject filters. Such filters also increase the area and power consumption of the system.

A radio frequency (RF) transmitter includes an upconverter, a digital timing offset circuit, a first digital-to-analog converter (DAC), a second DAC, an analog timing offset removal circuit, a first pulse-shaper, a second pulse-shaper, and an adder. The upconverter outputs an in-phase (I) signal and a quadrature (Q) signal. The digital timing offset circuit introduces a time offset between the I signal and the Q signal. The first DAC has a first clock signal and outputs an analog I signal based on the I signal. The second DAC has a second clock signal and outputs an analog Q signal based on the Q signal. The first and second clock signals have a same frequency and are offset relative to each other by the time offset. The analog timing offset removal circuit removes the time offset between the analog I signal and the analog Q signal. The first pulse shaper receives the analog I signal and outputs a pulse-shaped I signal. The second pulse shaper receives the analog Q signal and outputs a pulse-shaped Q signal. The adder receives the pulse-shaped I and Q signals and outputs an intermediate frequency signal.

In some examples, the digital timing offset circuit is a delay circuit that introduces a delay of the time offset into the I signal. The analog timing offset removal circuit is an advance circuit that advances the analog I signal by the time offset. In other examples, the digital timing offset circuit is an advance circuit that introduces an advance of the time offset into the Q signal. The analog timing offset removal circuit is a delay circuit that delays the analog Q signal by the time offset. The RF transmitter can further include a delay circuit that delays the I signal by a first length of time equal to a number N times a period T of the I signal. The advance circuit introduces the advance of the time offset into the Q signal by delaying the Q signal by a second length of time equal to (N−1)T plus T minus the time offset. The RF transmitter includes a digital step attenuator and a power amplifier in some implementations. The time offset can be equal to one fourth a period T, one eighth a period T, or a period T divided by four times a number N.

For a detailed description of various examples, reference will now be made to the accompanying drawings in which:

FIGS. 1 A- 1 B show block diagrams of a radio frequency sampling transmitter according to two examples.

FIG. 2 A is a circuit including two return-to-zero digital-to-analog converters and a time advance circuit for use in the radio frequency sampling transmitter shown in FIG. 1 A .

FIG. 2 B shows a set of waveforms of control signals and in-phase and quadrature data signals in the digital-to-analog converters shown in FIG. 2 A .

FIG. 3 A is a circuit including two non-return-to-zero digital-to-analog converters and a time advance circuit for use in the radio frequency sampling transmitter shown in FIG. 1 A .

FIG. 3 B shows a set of waveforms of control signals and in-phase and quadrature data signals in the digital-to-analog converters shown in FIG. 3 A .

FIG. 4 shows a frequency spectrum of an example input signal for a digital-to-analog converter included in the radio frequency sampling transmitter shown in FIGS. 1 A and 1 B .

FIG. 5 shows a frequency spectrum of an example transmitted signal output by the radio frequency sampling transmitter shown in FIGS. 1 A and 1 B .

FIG. 6 shows a graph of signal power for the output signal from a conventional radio frequency sampling transmitter and the output signal from the radio frequency sampling transmitter shown in FIGS. 1 A and 1 B .

The same reference numerals and other reference designators are used in the drawings to designate the same or similar (by function and/or structure) features.

The disclosed radio frequency (RF) sampling transmitters (TXs) include a digital time advance circuit, two digital-to-analog converters (DACs) operating at the same clock frequency with an offset of one-fourth a period T (e.g. 90 degrees out of phase), and an analog delay circuit. An in-phase (I) signal is directly input to the first DAC, and the time advance circuit introduces a time advance into a quadrature (Q) signal before it is input to the second DAC. The analog delay circuit delays the analog Q signal output from the second DAC such that the time advance introduced by the time advance circuit is cancelled out. The I and Q signals may be data signals.

The analog in-phase I signal and the delayed analog Q signal are input into a first pulse shaper and a second pulse shaper, respectively, before being added together to generate an intermediate frequency signal. The offset of T/4 between the DAC clocks as well as the time advance and delay introduced into the Q signal can reduce the magnitude of image artifacts in frequencies adjacent to the signal of interest without a local oscillator or image reject filters, thereby reducing the area and power used by the RF sampling TX.

FIG. 1 A shows a block diagram of an RF sampling transmitter 100 A, which includes a digital TX 105 , two return-to-zero (RZ) DACs 140 A and 140 B, a delay circuit 160 , two pulse shapers 170 A and 1706 , an adder 180 , a digital step attenuator (DSA) 188 , and a power amplifier (PA) 195 . The digital TX 105 includes a TX digital upconverter (DUC) 110 , a delay circuit 120 , and an advance circuit 130 . TX DUC 110 has an input 107 , a first output 112 and a second output 114 . TX DUC 110 receives a signal to be transmitted at input 107 and converts the signal 107 into its I and Q components. The first output 112 is for the I data signal 125 A, and the second output 114 is for the Q data signal 125 B. The delay circuit 120 and the advance circuit 130 are digital timing offset circuits that adjust the I data signal 125 A and the Q data signal 125 B, respectively, such that the time-advanced Q data signal 125 C has a time advancement relative to the delayed I signal 125 D. The delay circuit 160 is an analog timing offset removal circuit.

The delay circuit 120 has an input 116 coupled to the output 112 of the TX DUC 110 . The delay circuit 120 has an output 118 for the delayed I data signal 125 D. The advance circuit 130 has an input 132 coupled to the output 114 of the TX DUC 110 . The advance circuit 130 has an output 136 for the time-advanced Q data signal 125 C. In this example implementation, the delay circuit 120 introduces a larger delay of a number N times the period T (N*T), and the advance circuit 130 introduces a smaller delay 135 of

( ( N - 1 ) ⁢ T + ( 3 ⁢ T 4 ) ) .

That is, the delay circuit 120 introduces a larger delay into the I data signal than the smaller delay that advance circuit 130 introduces into the Q data signal, such that the time-advanced Q data signal 125 C is one-fourth of T advanced relative to the N*T delayed I data signal 125 D.

Any appropriate technique for advancing the Q data signal 125 B relative to the I data signal 125 A can be used. For example, the delay circuit 120 can introduce a delay of the period T times the sum of a number N plus one-fourth, and the advance circuit 130 can introduce a smaller delay of N times T. The length of the time advancement can be set (e.g. to one-fourth of T) to reduce the magnitude of image artifacts at odd harmonics of a sampling frequency fs of RZ DACs 140 A and 140 B. Alternatively, the length of the time advancement can be set to one-eighth of T as shown in FIG. 1 B to reduce the magnitude of image artifacts at even harmonics of the sampling frequency fs. The delayed I data signal 125 D is provided to the input 142 A of the RZ DAC 140 A, and the time-advanced Q data signal 125 C is provided to the input 142 B of the RZ DAC 140 B.

RZ DACs 140 A and 140 B operate at a sampling frequency fs equal to the digital data rate. As illustrated in offset 145 A, the RZ DACs 140 A and 140 B operate based on clock signals DAC CLKs 150 A and 150 B, respectively. RZ DAC 140 A receives the clock signal DAC CLK 150 A at an input 147 A, and RZ DAC 140 B receives the clock signal DAC CLK 150 B at an input 147 B. The clock signals DAC CLKs 150 A and 150 B are offset by one-fourth the period T of the clock signal relative to each other. The T/4 offset between DAC CLKs 150 A and 150 B matches the T/4 offset between the delayed I data signal 125 D and the time-advanced Q data signal 125 C and removes the need for a fractional phase locked loop acting as a shared local oscillator for the I and Q data signals, thereby reducing the area and power used by RF sampling transmitter 100 A. In addition, removing the need for a local oscillator also removes the need for image-reject filters to reduce the magnitude of images introduced by the local oscillator.

RZ DAC 140 A outputs the analog I signal 155 A through output 144 A, which is coupled to an input 172 A of the pulse shaper 170 A. RZ DAC 140 B outputs the analog Q signal 155 B through output 144 B, which is coupled to the input 162 of the T/4 delay circuit 160 . The delay circuit 160 cancels out the time advance (e.g. the T/4 or T/8 time advance as discussed above) introduced by advance circuit 130 and outputs the delayed Q signal 155 C through output 164 , which is coupled to the input 172 B of the pulse shaper 170 B. Any appropriate pulse shape may be used to boost the desired frequency content for a particular implementation. The pulse shaper 170 A outputs the pulse-shaped I signal 175 A through output 174 A, which is coupled to an input 177 A of the adder 180 . The pulse shaper 170 B outputs the pulse-shaped Q signal 175 B through output 174 B, which is coupled to an input 177 B of the adder 180 .

The pulse-shaped I signal 175 A and the pulse-shaped Q signal 175 B are combined together by adder 180 to generate an intermediate frequency (IF) signal 184 , which is output through an output 182 of the adder 180 . Adder 180 adds the I signal 175 A and Q signal 175 B to reduce above-band image artifacts, or subtracts the Q signal 175 B from the I signal 175 A to reduce below-band image artifacts. Adder 180 can be programmed by the user to perform the add operation or the subtract operation based on the desired performance of the RF sampling transmitter 100 A. An input 186 of the DSA 188 is coupled to the output 182 of the adder 180 . The DSA 188 performs an amplitude control operation on the signal received at input 186 and provides the amplitude-controlled signal to the output 190 of DSA 188 , which is coupled to an input 192 of the PA 194 . PA 194 generates a transmitter OUT signal 198 for output through the output 196 of the PA 194 .

FIG. 1 B shows a block diagram of an RF sampling transmitter 100 B that is similar to the RF sampling transmitter 100 A shown in FIG. 1 A , but includes a delay and an advance in the I signal chain, instead of an advance and a delay in the Q signal chain, and illustrates a T/8 offset to reduce the magnitude of image artifacts at even harmonics of fs. TX DUC 110 outputs an I data signal 125 A through output 112 and a Q data signal 125 B through output 114 . The delay circuits 120 and 130 are digital timing offset circuits and the advance circuit 160 is an analog timing offset removal circuit. In this implementation, the delay circuit 120 introduces a delay 135 of

( N ⁢ T + ( T 8 ) )

into I data signal 125 A, such that the delayed I signal 125 D is T/8 delayed relative to the NT delayed Q data signal 125 C.

Any appropriate technique for advancing the Q signal 125 C relative to the delayed I data signal 125 D can be used. For example, the delay circuit 120 can introduce a delay 135 of a number N times the period T, and the advance circuit 130 can introduce a smaller delay of

( ( N - 1 ) ⁢ T + ( 7 ⁢ T 8 ) ) .

The length of the time advancement can be set to one-eighth of T to reduce the magnitude of image artifacts at even harmonics of fs. Alternatively, the length of the time advancement can be set to one-fourth of T to reduce the magnitude of image artifacts at odd harmonics of a sampling frequency fs of RZ DACs 140 A and 140 B as discussed previously herein with respect to FIG. 1 A . The delayed I data signal 125 D is provided to the input 142 A of the RZ DAC 140 A, and the Q signal 125 C is provided to the input 142 B of the RZ DAC 140 B.

The RZ DACs 140 A and 140 B operate at an fs equal to the digital data rate. As illustrated in offset 145 B, the RZ DACs 140 A and 140 B operate based on clock signals DAC CLKs 150 A and 1506 , respectively, which are offset by one eighth the period T of the clock signal relative to each other to match the T/8 offset between the delayed I data signal 125 D and the Q data signal 125 C. Clock signals 150 A and 1506 are provided to RZ DAC 140 A and RZ DAC 140 B by inputs 147 A and 147 B, respectively. RZ DAC 140 A outputs an analog I signal 155 A through an output 144 A, which is coupled to the input 162 of the T/8 advance circuit 160 . The advance circuit 160 cancels out the T/8 delay introduced by delay circuit 120 . The advanced I signal 155 C is output from the output 164 of the advance circuit 160 , which is coupled to the input 172 A of the pulse shaper 170 A. The RZ DAC 140 B outputs an analog Q signal 155 B from the output 144 B of the RZ DAC 140 B, which is coupled to the input 172 B of the pulse shaper 170 B. The pulse shapers 170 A and 170 B, adder 180 , DSA 188 , and PA 194 operate as described herein with respect to RF sampling transmitter 100 A shown in FIG. 1 A .

Although FIGS. 1 A and 1 B illustrate distinct systems for reducing image artifacts in even and odd harmonics, a single system can reduce image artifacts in either even or odd harmonics. For example to reduce image artifacts in a harmonic of a number N times fs where N is any integer either even or odd, an RF sampling transmitter can introduce an offset

T 4 ⁢ N

between the I data signal 125 A and the Q data signal 125 B and the clock signals DAC CLKs 150 A and 150 B. The RF sampling transmitter can implement either a time advance in the Q signal chain as shown in FIG. 1 A or a time delay in the I signal chain shown as shown in FIG. 1 B to introduce the offset

T 4 ⁢ N

between the I data signal 125 A and the Q data signal 125 B.

FIG. 2 A shows an example circuit diagram 200 for the RZ DACs 140 A and 140 B, the delay circuit 160 , and pulse shapers 170 A-B shown in FIG. 1 A . In some example embodiments, RZ DAC 140 A and RZ DAC 140 B are each 14-bit DACs and each includes additional circuitry (not shown). RZ DAC 140 A receives I data 125 D at an input 142 A and includes a current source 215 A and switches 220 A and 225 A. Current source 215 A is coupled to a supply voltage rail Vdd 205 (e.g., 3.3 Volts). Switch 220 A is coupled to current source 215 A and to node 230 A, and switch 225 A is coupled to current source 215 A and to node 235 A. Switch 240 A is coupled to node 230 A and to common potential (e.g. ground) 210 . Switch 245 A is coupled to node 235 A and to ground 210 . Switches 220 A and 225 A are configured to open and close based on DAC CLK signal 150 A from input 147 A, and switches 240 A and 245 A are configured to open and close based on a control signal ϕ 5 which has a frequency that is approximately twice the sampling frequency fs.

RZ DAC 140 B is similar to RZ DAC 140 A and receives time-advanced Q data 125 C. RZ DAC 140 B includes a current source 215 B and switches 220 B and 225 B. Current source 215 B is coupled to a supply voltage rail Vdd 205 . Switch 220 B is coupled to current source 215 B and to node 230 B. Switch 225 B is coupled to current source 215 B and to node 235 B. Switch 240 B is coupled to node 230 B and to ground 210 . Switch 245 B is coupled to node 235 B and to ground 210 . Switches 220 B and 225 B are configured to open and close based on DAC CLK signal 150 B from input 147 B, and switches 240 B and 245 B are configured to open and close based on a control signal ϕ 6 which is approximately twice the sampling frequency fs.

Pulse shaper 170 A includes a switching bank with switches 250 A, 252 A, 254 A, and 256 A. Switch 250 A is coupled to node 230 A and node 260 . Switch 256 A is coupled to node 235 A and node 265 . Switches 250 A and 256 A are configured to open and close based on control signal ϕ 1 . Switch 252 A is coupled to node 235 A and node 260 . Switch 254 A is coupled to node 230 A and to node 265 . Switches 252 A and 254 A are configured to open and close based on control signal ϕ 2 .

Pulse shaper 170 B is similar to pulse shaper 170 A and includes a switching bank with switches 250 B, 252 B, 254 B, and 256 B. Switch 250 B is coupled to node 230 B and node 260 . Switch 256 B is coupled to node 235 B and node 265 . Switches 250 B and 256 B are configured to open and close based on control signal ϕ 3 . Switch 252 B is coupled to node 235 B and node 260 . Switch 254 B is coupled to node 230 B and to node 265 . Switches 252 B and 254 B are configured to open and close based on control signal ϕ 4 . A resistor 270 is coupled to node 260 and to ground 210 . A resistor 275 is coupled to node 265 and to ground 210 . Control signals ϕ 1 -ϕ 4 are described further herein with reference to FIG. 2 B . Node 260 is coupled to the pulse shaper output 174 A of pulse shaper 170 A, and node 265 is coupled to the pulse shaper output 174 B of pulse shaper 170 B.

FIG. 2 B shows a set of waveforms 290 of control signals ϕ 1 - 6 and I data signal 125 D and time-advanced Q data signal 125 C, shown in FIG. 2 A . Time-advanced Q data signal 125 C is offset from I data signal 125 D by T/4, and a T/4 time advance is introduced by advance circuit 130 in digital transmitter 105 shown in FIG. 1 A to compensate. In RF sampling transmitter 100 A, advance circuit 130 introduces a time advance of T/4 to reduce the magnitude of image artifacts at odd harmonics of fs, but in other implementations advance circuit 130 introduces a time advance of T/8 to reduce the magnitude of image artifacts at even harmonics of fs.

The DAC CLK signals 150 A and 150 B are offset by T/4. At time t 0 , the DAC CLK signal 150 A causes switches 220 A and 225 A to be closed, and the control signal ϕ 5 causes switches 240 A and 245 A to be closed, such that current source 215 A is coupled to pulse shaper 170 A and ground 210 . The DAC CLK signal 150 B causes switches 220 B and 225 B to be open, and the control signal ϕ 6 causes switches 240 B and 245 B to be open, such that current source 215 B is disconnected from ground 210 and pulse shaper 170 B. At time t 1 , the DAC CLK signal 150 A and the control signal ϕ 5 cause switches 220 A, 225 A, 240 A, and 245 A to be open such that current source 215 A is disconnected from pulse shaper 170 A and ground 210 . The DAC CLK signal 150 B and the control signal ϕ 6 causes switches 220 B, 225 B, 240 B, and 245 B to be closed such that current source 215 B is coupled to ground 210 and pulse shaper 170 B.

Control signals ϕ 1 and ϕ 2 have a frequency approximately equal to the sampling frequency fs. In this example, only one of ϕ 1 or ϕ 2 is high at a time. Accordingly, ϕ 1 and ϕ 2 alternate which is logic high while the DAC CLK signal 150 A and control signal ϕ 5 cause switches 220 A, 225 A, 240 A and 245 A to be open. For example, at t 1 , ϕ 2 transitions logic high, causing switches 252 A and 254 A to close such that node 230 A is coupled to node 265 and resistor 275 and node 235 A is coupled to node 260 and resistor 270 . At t 3 , ϕ 1 transitions logic high, causing switches 250 A and 256 A to close such that node 230 A is coupled to node 260 and resistor 270 and node 235 A is coupled to node 265 and resistor 275 .

Control signals ϕ 3 and ϕ 4 have a frequency approximately equal to the sampling frequency fs and also alternate which is logic high while the DAC CLK signal 150 B and control signal ϕ 6 cause switches 220 B, 225 B, 240 B, and 245 B to be open. For example, at t 2 , ϕ 4 goes logic high, causing switches 252 B and 254 B to close such that node 230 B is coupled to node 265 and resistor 275 and node 235 B is coupled to node 260 and resistor 270 . At t 4 , ϕ 3 transitions logic high, causing switches 250 B and 256 B to close such that node 230 B is coupled to node 260 and resistor 270 and node 235 B is coupled to node 265 and resistor 275 .

Alternating data samples from I data 125 D and time-advanced Q data 125 C are shaped by the switching banks in pulse shapers 170 A-B and resistors 270 and 275 . I data 125 D and time-advanced Q data 125 C input to DACs 140 A-B have frequencies approximately equal to the desired center frequency fc minus fs, since pulse shapers 170 A-B up-convert the signals by fs. As discussed previously herein with respect to FIG. 1 A , the T/4 offset for DAC CLKs 150 A and 150 B and the time advance and delay introduced by advance circuit 130 and delay circuit 160 , respectively, enables rejection of images at frequencies adjacent to fc without a fractional local oscillator or image-reject filters.

FIG. 3 A shows an example circuit diagram 300 for the delay circuit 160 and pulse shapers 170 A and 170 B shown in FIG. 1 A , as well as non-return to zero (NRZ) DACs used in place of the RZ DACs 140 A and 140 B to illustrate that both RZ and NRZ DACs can be used in the systems 100 A and 100 B. The circuit diagram 300 is similar to the circuit diagram 200 shown in FIG. 2 A , but includes current buffers 305 , 310 , 315 , and 320 and omits switches 240 A- 240 B and 245 A- 245 B. The switches 240 A- 240 B and 245 A- 245 B in RZ DACs 140 A and 140 B, described herein with reference to FIG. 2 A , couple the DACs 140 A and 140 B to ground based on the control signals ϕ 5 and ϕ 6 , causing the DAC output signals 155 A and 155 B to return to zero between data samples. Current buffer 305 is coupled between switches 254 A and 256 A and node 265 . Current buffer 310 is coupled between switches 250 A and 252 A and node 260 . A resistor 270 is coupled to node 260 and to supply voltage rail Vdd 205 . Current buffer 315 is coupled between switches 250 B and 254 B and node 265 . Current buffer 315 is coupled between switches 252 B and 256 B and node 260 . A resistor 275 is coupled to node 265 and to supply voltage rail Vdd 205 . Control signals ϕ 1 -ϕ 4 are described further herein with reference to FIG. 3 B .

FIG. 3 B shows a set of waveforms 390 of control signals ϕ 1 -ϕ 4 and I data signal 125 D and time-advanced Q data signal 125 C, described in FIG. 3 A . Time-advanced Q signal 125 C is offset from I data signal 125 D by T/4, and a T/4 time advance is introduced by advance circuit 130 in digital transmitter 105 shown in FIG. 1 A to compensate. In RF sampling transmitter 100 A, advance circuit 130 introduces a time advance of T/4 to reduce the magnitude of image artifacts at odd harmonics of fs, but in other implementations advance circuit 130 introduces a time advance of T/8 to reduce the magnitude of image artifacts at even harmonics of fs.

Control signals ϕ 1 and ϕ 2 have a frequency approximately equal to the sampling frequency fs and alternate which is logic high. For example, at t 0 ϕ 2 goes logic high, causing switch 254 A to close such that node 230 A is coupled to current buffer 305 and resistor 275 , and causing switch 252 A to close such that node 235 A is coupled to buffer 310 and resistor 270 . At t 2 , ϕ 1 transitions logic high, causing switch 250 A to close such that node 230 A is coupled to current buffer 310 and resistor 270 , and causing switch 256 A to close such that node 235 A is coupled to current buffer 305 and resistor 275 .

Control signals ϕ 3 and ϕ 4 have a frequency approximately equal to the frequency of I signal 120 A and time-advanced Q signal 120 C and alternate which is logic high. For example, at t 1 , ϕ 4 transitions logic high, causing switch 252 B to close such that node 235 B is coupled to current buffer 320 and resistor 270 , and causing switch 254 B to close such that node 230 B is coupled to current buffer 315 and resistor 275 . At t 3 , ϕ 3 transitions logic high, causing switch 250 B to close such that node 235 B is coupled to current buffer 315 and resistor 275 , and causing switch 256 B to close such that node 230 B is coupled to current buffer 320 and resistor 270 .

FIG. 4 shows a frequency spectrum 400 of an example input signal to a DAC 140 A or 140 B in RF sampling transmitter 100 A shown in FIG. 1 A or RF sampling transmitter 100 B shown in 1 B. FIG. 4 is not drawn to scale, so the relative magnitudes may be the same or different than shown in FIG. 4 . The example input signal can be the I data signal 125 D input to DAC 140 A in RF sampling transmitter 100 A, the delayed Q data signal 125 C input to DAC 140 B in RF sampling transmitter 100 A, the delayed I data signal 125 D input to DAC 140 A in RF sampling transmitter 100 B, or the Q data signal 125 C input to DAC 140 B in RF sampling transmitter 100 B.

The example input signal is an impulse train with a frequency component 410 at −fs−f1, a frequency component 420 at −fs+f1, a frequency component 430 at −f1, a frequency component 440 at f1, a frequency component 450 at fs−f1, and a frequency component 460 at fs+f1, where the RF signal 107 to be transmitted is within the frequency band of plus or minus the frequency f1. For example, the signal 107 may be at the frequency f1 and an image is at the frequency of negative f1. Conversely, the signal 107 may be at the frequency of negative f1 and an image is at the frequency f1. The DAC 140 A or 140 B converts the digital impulses 410 , 420 , 430 , 440 , 450 , and 460 to an analog signal. The pulse shape imposed by the pulse shaper 170 A or 170 B, respectively, boosts the frequency component 430 at −f1 and attenuates the remaining frequency components at 410 , 420 , 440 , 450 , and 460 or boosts the frequency component 440 at f1 and attenuates the remaining frequency components at 410 , 420 , 430 , 450 , and 460 .

FIG. 5 shows a frequency spectrum 500 of the transmitted signal OUT 198 from RF sampling transmitter 100 A shown in FIG. 1 A or from RF sampling transmitter 100 B shown in FIG. 1 B . FIG. 5 is not drawn to scale, so the relative magnitude of the signals is much more pronounced than depicted in FIG. 5 . The frequency of OUT 198 is at fc−f1, where the RF sampling transmitter 100 transmits OUT 198 in the frequency band of plus or minus a frequency f1 around the center frequency fc. That is, the frequency bandwidth of OUT 198 is between fc−f1 and fc+f1. For example, fc is three gigaHertz (GHz), fs is 3 GHz, and f1 is 0.4 GHz. OUT 198 has a magnitude of −0.9 decibels relative to full scale (dBFS). The image 510 at fc+f1, 3.4 GHz, is greatly reduced by the T/4 time advance and delay. The image 520 is at fc+fs−f1, 5.6 GHz, and the image 530 is at fc+fs+f1, 6.4 GHz. The image 540 is at fc−fs+f1, 0.4 GHz. Images 520 , 530 , and 540 have very small magnitudes relative to OUT 198 . The relatively low magnitudes and distant frequencies from OUT 198 relax the bandpass filtering requirements to capture OUT 198 and omit the images 520 , 530 , and 540 .

FIG. 6 shows a graph 600 of signal power for the output signal from a conventional RF sampling transmitter and the output signal OUT 198 from the RF sampling transmitter shown in FIGS. 1 A and 1 B . At the 2.6 GHz band indicated by callout 630 , the output signal 610 from a conventional RF sampling transmitter with a 6 GSPS fs is approximately −2.9 dBFS, while the output signal 620 from the RF sampling transmitter 100 with a 3 GSPS fs is approximately −0.9 dBFS. At the 4.9 GHz band indicated by callout 660 , the output signal 640 from a conventional RF sampling transmitter with a 12 GSPS fs is approximately −2.5 dBFS, while the output signal 650 from the RF sampling transmitter 100 with a 6 GSPS fs is approximately −1.0 dBFS. The callouts 630 and 660 illustrate the improved TX output power of RF sampling transmitter 100 relative to the conventional RF sampling transmitter while operating at half the sampling frequency.

In this description, the term “couple” may cover connections, communications, or signal paths that enable a functional relationship consistent with this description. For example, if device A generates a signal to control device B to perform an action: (a) in a first example, device A is coupled to device B by direct connection; or (b) in a second example, device A is coupled to device B through intervening component C if intervening component C does not alter the functional relationship between device A and device B, such that device B is controlled by device A via the control signal generated by device A.

A device that is “configured to” perform a task or function may be configured (e.g., programmed and/or hardwired) at a time of manufacturing by a manufacturer to perform the function and/or may be configurable (or re-configurable) by a user after manufacturing to perform the function and/or other additional or alternative functions. The configuring may be through firmware and/or software programming of the device, through a construction and/or layout of hardware components and interconnections of the device, or a combination thereof.

As used herein, the terms “terminal”, “node”, “interconnection”, “pin” and “lead” are used interchangeably. Unless specifically stated to the contrary, these terms are generally used to mean an interconnection between or a terminus of a device element, a circuit element, an integrated circuit, a device or other electronics or semiconductor component.

A circuit or device that is described herein as including certain components may instead be adapted to be coupled to those components to form the described circuitry or device. For example, a structure described as including one or more semiconductor elements (such as transistors), one or more passive elements (such as resistors, capacitors, and/or inductors), and/or one or more sources (such as voltage and/or current sources) may instead include only the semiconductor elements within a single physical device (e.g., a semiconductor die and/or integrated circuit (IC) package) and may be adapted to be coupled to at least some of the passive elements and/or the sources to form the described structure either at a time of manufacture or after a time of manufacture, for example, by an end-user and/or a third-party.

Circuits described herein are reconfigurable to include additional or different components to provide functionality at least partially similar to functionality available prior to the component replacement. Components shown as resistors, unless otherwise stated, are generally representative of any one or more elements coupled in series and/or parallel to provide an amount of impedance represented by the resistor shown. For example, a resistor or capacitor shown and described herein as a single component may instead be multiple resistors or capacitors, respectively, coupled in parallel between the same nodes. For example, a resistor or capacitor shown and described herein as a single component may instead be multiple resistors or capacitors, respectively, coupled in series between the same two nodes as the single resistor or capacitor.

Uses of the phrase “ground” in the foregoing description include a chassis ground, an Earth ground, a floating ground, a virtual ground, a digital ground, a common ground, and/or any other form of ground connection applicable to, or suitable for, the teachings of this description. Unless otherwise stated, “about,” “approximately,” or “substantially” preceding a value means +/−10 percent of the stated value. Modifications are possible in the described examples, and other examples are possible within the scope of the claims.

Modifications are possible in the described embodiments, and other embodiments are possible, within the scope of the claims.