Error management system for system-on-chip

The present disclosure relates generally to electronic circuits, and, more particularly, to an error management system.

In a system-on-chip (SoC), various functional circuits (e.g., memories, math accelerators, digital signal processors, or the like) output functional signals to execute various operations associated therewith. Such functional signals may include functional errors that disrupt functional operations of the SoC. To manage such functional errors, the SoC includes an error management system. When the error management system detects a functional error in the functional signal, a corresponding reaction (e.g., one of reset, interrupt, or the like) is instantly executed by the error management system.

The error management system may further detect an intentional test error that is injected into a functional signal to test the SoC. A conventional error management system instantly executes a reaction for both an injected test error and another reaction for a functional error. As the detection of each test error is followed by an instant reaction, the number of processing cycles of the SoC required to execute the reaction is same for the injected test error and the functional error. Further, the functional circuits remain unavailable to execute functional operations during the execution of the reactions, thereby reducing the overall availability of the SoC to execute the functional operations. Therefore, there exists a need for a technical solution that solves the aforementioned problems of conventional error management systems.

In an embodiment of the present disclosure, an error management system is disclosed. The error management system can include a sampling circuit, an error tracking circuit, and a reaction circuit. The sampling circuit can be configured to receive a plurality of error signals that are generated when a plurality of test errors are injected in a plurality of functional signals. The error tracking circuit can comprise first and second register sets associated with a first error reaction. Further, the plurality of test errors can be injected in the plurality of functional signals based on activation of a first plurality of bits in the first register set. A second plurality of bits in the second register set are activated based on the reception of the plurality of error signals by the sampling circuit. Further, the error tracking circuit can be configured to generate an indication signal such that the indication signal is activated when a first number of the activated first plurality of bits matches a second number of the activated second plurality of bits. The reaction circuit can be coupled with the error tracking circuit and configured to receive the indication signal and generate a reaction signal indicative of the first error reaction when the indication signal is activated.

In another embodiment of the present disclosure, an error management system is disclosed. The error management system can include a sampling circuit, an error tracking circuit, and a reaction circuit. The sampling circuit can be configured to receive first and second sets of error signals and a plurality of injection signals and output, based on the plurality of injection signals, at least one of a set of activation signals and a set of functional error signals. The first and second sets of error signals can be generated based on first and second sets of functional signals. The error tracking circuit can comprise first and second register sets associated with a first error reaction. Further, the error tracking circuit can be configured to receive the set of activation signals when the first set of error signals is generated based on a set of test errors, and generate an indication signal. The set of test errors can be injected in the first set of functional signals, based on activation of a first set of bits in the first register set. The sampling circuit can be further configured to activate in the second register set, a second set of bits by way of the set of activation signals. The error tracking circuit can be further configured to activate the indication signal when a first number of the activated first set of bits matches a second number of the activated second set of bits. The reaction circuit can be configured to at least one of receive the indication signal from the error tracking circuit and a first reaction signal when the indication signal is activated. The reaction circuit can be further configured to receive the set of functional error signals from the sampling circuit when the second set of error signals is generated based on presence of a set of functional errors in the second set of functional signals. The reaction circuit can be further configured to generate a corresponding reaction signal of a second set of reaction signals when a corresponding error signal of the set of functional error signals is received.

In yet another embodiment of the present disclosure, a system-on-chip (SoC) is disclosed. The SoC can include error detection circuitry and an error management system. The error detection circuitry can be configured to receive first and second sets of functional signals and generate first and second sets of error signals and first and second sets of injection signals, respectively. The first set of error signals can be generated based on injection of a set of test errors in the first set of functional signals and the second set of error signals can be generated based on presence of a set of functional errors in the second set of functional signals. The error management system can include first and second register sets associated with a first error reaction. The error management system can be configured to receive the first and second sets of error signals. The error management system can be further configured to at least one of generate an indication signal when a first number of activated bits in the first register set matches a second number of activated bits in the second register set. The error management system can be further configured to generate a first reaction signal associated with the first error reaction when the indication signal is activated, and generate a corresponding reaction signal of a second set of reaction signals when a corresponding error signal of the second set of error signals is received.

In some embodiments, the error tracking circuit can be further configured to receive a first programming signal. The first plurality of bits can be activated by way of the first programming signal.

In some embodiments, the error tracking circuit can further comprise a processing circuit that is coupled with the reaction circuit and the first and second register sets. The processing circuit can be configured to generate first and second tracking signals and track an activation status of each of the first and second pluralities of bits by way of the first and second tracking signals, respectively.

In some embodiments, the error tracking circuit can further comprise a third register set. The third register set can be configured to receive a second programming signal. Further, a third bit in the third register set can be activated by way of the second programming signal. The third bit can be associated with the first error reaction. Further, the plurality of test errors can be injected when the first plurality of bits in the first register set and the third bit are activated in the third register set.

In some embodiments, the processing circuit can be further configured to generate the indication signal. Further, the processing circuit can deactivate the indication signal when the first number of the activated first plurality of bits does not match the second number of the activated second plurality of bits.

In some embodiments, the sampling circuit can be further configured to output a plurality of activation signals when the plurality of error signals are received by the sampling circuit. Further, the sampling circuit can activate the second plurality of bits in the second register set by way of the plurality of activation signals.

In some embodiments, the sampling circuit can be further configured to receive a plurality of injection signals that indicate injection of the plurality of test errors in the plurality of functional signals. Further, each injection signal of the plurality of injection signals can be associated with a corresponding error signal of the plurality of error signals. The plurality of activation signals can be outputted based on the indication by the plurality of injection signals.

In some embodiments, when a first set of injection signals of the plurality of injection signals indicate that the first set of error signals can be generated based on the injection of the set of test errors in the first set of functional signals, the sampling circuit outputs the set of activation signals. Further, when a second set of injection signals of the plurality of injection signals indicate that the second set of error signals can be generated based on the presence of the set of functional errors in the second set of functional signals, the sampling circuit outputs the set of functional error signals.

In some embodiments, the SoC can further include injection circuitry. The injection circuitry can be configured to receive a first programming signal and inject the set of test errors in the first set of functional signals.

In some embodiments, the SoC can further include a core circuit. The core circuit can be configured to output the first programming signal and second and third programming signals and provide the first through third programming signals to the injection circuitry, the first register set, and the third register set, respectively. Further, the first number of bits in the first register set and the bit in the third register set can be activated when the second and third programming signals are provided to the first and third register sets, respectively.

Various embodiments of the present disclosure disclose an error management system that is configured to output a reaction signal in response to multiple test errors such that the reaction signal is indicative of a common error reaction associated with each of the test errors. The error management system further outputs another set of reaction signals in response to multiple functional errors. The error management system can include a sampling circuit, an error tracking circuit, and a reaction circuit. The sampling circuit can be configured to receive multiple error signals that are generated when multiple test errors are injected in multiple functional signals such that each test error is injected in a corresponding functional signal. The sampling circuit can be further configured to output multiple activation signals when the error signals are received by the sampling circuit. The error tracking circuit can include two register sets associated with the error reaction. Further, the test errors can be injected based on activation of a first plurality of bits in one register set whereas a second plurality of bits in the other register set are activated by way of the activation signals. The error tracking circuit further generates an indication signal such that the indication signal is activated when a number of the activated first plurality of bits matches a number of the activated second plurality of bits. The reaction circuit receives the indication signal and generates the reaction signal indicative of the error reaction when the indication signal is activated.

The error management system of the present disclosure differentiates the injected test errors from the functional errors. In addition, the error management system generates a single reaction in response to multiple test errors associated with the same error reaction. Thus, the number of processing cycles of the SoC is reduced since a single reaction signal is generated by grouping errors associated with the same reaction as compared to generating a reaction signal each time a functional signal injected with a test error is received by conventional error management systems. A reduction in the number of processing cycles leads to an increase in the availability of the functional circuits to execute functional operations.

The following detailed description of the preferred embodiments of the present disclosure will be better understood when read in conjunction with the appended drawings. The present disclosure is illustrated by way of example, and not limited by the accompanying figures, in which like references indicate similar elements.

FIG. 1 illustrates a schematic block diagram of a system-on-chip (SoC) in accordance with an embodiment of the present disclosure; and

FIG. 2 illustrates a schematic block diagram of an error management system of the SoC in FIG. 1 in accordance with an embodiment of the present disclosure.

The detailed description of the appended drawings is intended as a description of the currently preferred embodiments of the present disclosure, and is not intended to represent the only form in which the present disclosure may be practiced. It is to be understood that the same or equivalent functions may be accomplished by different embodiments that are intended to be encompassed within the spirit and scope of the present disclosure.

FIG. 1 illustrates a schematic block diagram of a system-on-chip (SoC) 100 in accordance with an embodiment of the present disclosure. The SoC 100 can include a plurality of functional circuits of which first through fifth functional circuits 102 a - 102 e are shown. Examples of the plurality of functional circuits can include but are not limited to, a memory, a math accelerator, a motor controller, or the like. The SoC 100 can further include injection circuitry 104 and an error detection circuitry 106 . The error detection circuitry 106 includes first through fifth error detection circuits 106 a - 106 e . The SoC 100 can further include a core circuit 108 , an error management system 110 , and a plurality of receiving circuits of which first and second receiving circuits 112 a and 112 b are shown. The SoC 100 may be utilized in a driver override system, a future battery management application, a mobile device, or the like.

The first through fifth functional circuits 102 a - 102 e may include suitable circuitry that can be configured to perform one or more operations. The first through fifth functional circuits 102 a - 102 e can be configured to output and provide first through fifth functional signals FS 1 -FS 5 , respectively, to various circuitries of the SoC 100 . The various circuitries can further carry out operations, based on a reception of a corresponding functional signal of the first through fifth functional signals FS 1 -FS 5 . In an embodiment, the first through fifth functional signals FS 1 -FS 5 are binary signals. It will be apparent to a person skilled in the art that the SoC 100 can include more than five functional circuits (i.e., more than the first through fifth functional circuits 102 a - 102 e ).

The injection circuitry 104 may include suitable circuitry that can be configured to perform one or more operations. For example, the injection circuitry 104 can be configured to receive a first programming signal PS 1 and inject first through third test errors TE 1 -TE 3 in the first through third functional signals FS 1 -FS 3 , respectively. In an example, injecting the first through third test errors TE 1 -TE 3 in the first through third functional signals FS 1 -FS 3 reverses a corresponding bit of a set of bits in each of the first through third functional signals FS 1 -FS 3 , respectively. The first programming signal PSI may be a single-bit or multi-bit signal. In an embodiment, the injection circuitry 104 can include a plurality of injection circuits (not shown) such that each injection circuit can inject a corresponding test error, i.e., one of the first through third test errors TE 1 -TE 3 . Although it is described that a single test error is injected in each of the first through third functional signals FS 1 -FS 3 , the scope of the present disclosure is not limited to it. In an alternate embodiment, multiple test errors can be injected in each of the first through third functional signals FS 1 -FS 3 by the injection circuitry 104 without deviating from the scope of the present disclosure.

As the first through third test errors TE 1 -TE 3 are injected in the first through third functional signals FS 1 -FS 3 to check an operation of the SoC 100 , the first through third test errors TE 1 -TE 3 may not require an instant reaction to be implemented in the SoC 100 , respectively. Further, the injection of the first through third test errors TE 1 -TE 3 in the first through third functional signals FS 1 -FS 3 , respectively, may occur during a start-up of the SoC 100 , a shut-down of the SoC 100 , and periodically during an operation of the SoC 100 . Therefore, the first through third test errors TE 1 -TE 3 or different test errors may be injected in the first through third functional signals FS 1 -FS 3 multiple times to occasionally test the SoC 100 . The first and second test errors TE 1 and TE 2 are associated with the first error reaction, and the third test error TE 3 is associated with a second error reaction.

The error detection circuitry 106 can be coupled with the first through fifth functional circuits 102 a - 102 e . Further, the error detection circuitry 106 can be configured to receive the first through third functional signals FS 1 -FS 3 injected with the first through third test errors TE 1 -TE 3 , respectively. The error detection circuitry 106 can be configured to receive fourth and fifth functional signals FS 4 and FS 5 with the presence of first and second functional errors, respectively. The first and second functional errors can be present in the fourth and fifth functional signals FS 4 and FS 5 . In an example, the presence of the first and second functional errors in the fourth and fifth functional signals FS 4 and FS 5 may indicate an error in an operation of the fourth and fifth functional circuits 102 d and 102 e, respectively. In various other examples, the presence of the first and second functional errors in the fourth and fifth functional signals FS 4 and FS 5 may be due to reception of erroneous input signals (not shown) by the fourth and fifth functional circuits 102 d and 102 e thereby generating the first and second functional errors in each of the fourth and fifth functional signals FS 4 and FS 5 , respectively. Examples of the error detection circuitry 106 can include but are not limited to, error correction code checker and parity checker.

The error detection circuitry 106 can be further configured to generate first through fifth error signals ES 1 -ES 5 and first through fifth injection signals IJ 1 -IJ 5 . The first through fifth error signals ES 1 -ES 5 and the first through fifth injection signals IJ 1 -IJ 5 are generated based on the first through fifth functional signals FS 1 -FS 5 , respectively. The first through fifth injection signals IJ 1 -IJ 5 correspond to the first through fifth error signals ES 1 -ES 5 , respectively. The first through fifth error signals ES 1 -ES 5 are indicative of whether an error is present in the first through fifth functional signals FS 1 -FS 5 , respectively. Further, the first through fifth injection signals IJ 1 -IJ 5 are indicative of whether the error indicated by the first through fifth error signals ES 1 -ES 5 , respectively, are test errors.

When an error is detected in a functional signal by the error detection circuitry 106 , the corresponding error signal is activated. In an embodiment of the present disclosure, the corresponding error signal is generated at a logic high state. For example, when the first through third functional signals FS 1 -FS 3 are injected with the first through third test errors TE 1 -TE 3 and the fourth and fifth functional signals FS 4 and FS 5 have the first and second functional errors present in them, the first through fifth error signals ES 1 -ES 5 are activated (i.e., are at a logic high state), respectively. In the presently preferred embodiment, the error detection circuitry 106 generates an injection signal associated with the corresponding error signal at a logic high state when the corresponding detected error is an injected error, and an injection signal associated with the error signal at a logic low state when the corresponding detected error is a functional error. In an example, as the first through third functional signals FS 1 -FS 3 are injected with the first through third test errors TE 1 -TE 3 , the first through third injection signals U 1 -U 3 are activated (i.e., are at a logic high state). In addition, as the first and second functional errors are present in the fourth and fifth functional signals FS 4 and FS 5 , the fourth and fifth injection signals IJ 4 and IJ 5 are deactivated (i.e., generated at a logic low state).

The first and second functional errors can be associated with third and fourth error reactions, respectively. For example, when the first and second functional errors are detected by the error detection circuitry 106 , third and fourth error reactions can be executed. The error reactions associated with the first and second functional errors may be the same or different as the error reactions associated with the first through third test errors TE 1 -TE 3 . In a presently preferred embodiment, the first through fifth functional signals FS 1 -FS 5 are provided to the error detection circuitry 106 , sequentially.

The error detection circuitry 106 can further include the first through fifth error detection circuits 106 a - 106 e. The first through fifth error detection circuits 106 a - 106 e can be coupled with the first through fifth functional circuits 102 a - 102 e, respectively. Further, the first through third error detection circuits 106 a - 106 c can be configured to receive the first through third functional signals FS 1 -FS 3 injected with the first through third test errors TE 1 -TE 3 , respectively. Similarly, the fourth and fifth error detection circuits 106 d and 106 e can be configured to receive the fourth and fifth functional signals FS 4 and FS 5 with the presence of the first and second functional errors, respectively. Further, each of the first through fifth error detection circuits 106 a - 106 e can be configured to detect at least one of a presence of a functional error or test error in the first through fifth functional signals FS 1 -FS 5 , respectively.

The first through third error detection circuits 106 a - 106 c can be further configured to generate activated first through third error signals ES 1 -ES 3 and activated first through third injection signals U 1 -U 3 as the first through third functional signals FS 1 -FS 3 are injected with the first through third test errors TE 1 -TE 3 , respectively. Further, the fourth and fifth error detection circuits 106 d and 106 e can be configured to generate activated fourth and fifth error signals ES 4 and ES 5 and deactivated fourth and fifth injection signals IJ 4 and IJ 5 , as the first and second functional errors are present in the fourth and fifth functional signals FS 4 and FS 5 , respectively. Further, the first through fifth error detection circuits 106 a - 106 e can be configured to provide the first through fifth error signals ES 1 -ES 5 and the first through fifth injection signals IJ 1 -IJ 5 to the error management system 110 . It will be apparent to a person skilled in the art, that when the SoC 100 includes more than five functional circuits (i.e., more than the first through fifth functional circuits 102 a - 102 e ), the error detection circuitry 106 may include more than five error detection circuits (i.e., more than the first through fifth error detection circuits 106 a - 106 e ). In another embodiment, the error detection circuitry 106 is a single error detection circuit that detects the first through third test errors TE 1 -TE 3 and the first and second functional errors FS 4 and FS 5 in the first through fifth functional signals FS 1 -FS 5 , respectively. Further, the activated first through fifth error signals ES 1 -ES 5 , the activated first through third injection signals IJ 1 -IJ 3 , and the deactivated fourth and fifth injection signals IJ 4 and IJ 5 can be provided to the error management system 110 .

The core circuit 108 can be coupled with the injection circuitry 104 . The core circuit 108 includes suitable circuitry that can be configured to perform one or more operations. For example, the core circuit 108 can be configured to output and provide the first programming signal PS 1 to the injection circuitry 104 and second and third programming signals PS 2 and PS 3 to the error management system 110 . Although in the present embodiment, the second and third programming signals PS 2 and PS 3 are one-bit signals, it will be apparent to a person skilled in the art that the second and third programming signals PS 2 and PS 3 can be multi-bit signals. Further, the core circuit 108 can output the first programming signal PS 1 after providing both the second and third programming signals PS 2 and PS 3 to the error management system 110 . The core circuit 108 provides the second and third programming signals PS 2 and PS 3 to the error management system 110 to activate an error injection phase at the error management system 110 to test the SoC 100 . The SoC 100 may be tested occasionally during its operation. Based on the second and third programming signals PS 2 and PS 3 , the core circuit 108 outputs and provides the first programming signal PSI to the injection circuitry 104 to inject the first through third test errors TE 1 -TE 3 .

The error management system 110 can be coupled with the error detection circuitry 106 (i.e., the first through fifth error detection circuits 106 a - 106 e ). The error management system 110 can be configured to receive the first through fifth error signals ES 1 -ES 5 and the first through fifth injection signals IJ 1 -IJ 5 . The first and second test errors TE 1 and TE 2 are associated with the first error reaction, and the third test error TE 3 is associated with the second error reaction. In other words, when the first and second test errors TE 1 and TE 2 are detected by the error detection circuitry 106 , a first reaction signal RS 1 indicative of the first error reaction can be executed by the error management system 110 . Similarly, when the third test error TE 3 is detected by the error detection circuitry 106 , a second reaction signal RS 2 indicative of the second error reaction can be executed by the error management system 110 . The first and second test errors TE 1 and TE 2 can be of the same type of error or different types of errors that require the same reaction. In an example, the first and second test errors TE 1 and TE 2 are parity errors that require the first error reaction. In another example, the first and second test errors TE 1 and TE 2 can be a parity error and a lockstep error, respectively, that require the first error reaction. Further, examples of the first and second error reactions can include but are not limited to, reset, interrupt, non-maskable interrupt, error out, or the like.

The error management system 110 can be further coupled with the core circuit 108 . The error management system 110 can be configured to receive the second and third programming signals PS 2 and PS 3 . The error management system 110 can be further configured to generate a plurality of reaction signals that include first through fourth reaction signals RS 1 -RS 4 , based on the first through fifth error signals ES 1 -ES 5 , the first through fifth injection signals IJ 1 -IJ 5 , and the second and third programming signals PS 2 and PS 3 .

The core circuit 108 , by way of the second programming signal PS 2 , can program the error management system 110 to indicate the injection of test errors (i.e., the first through third test errors TE 1 -TE 3 ) in the functional signals (i.e., the first through third functional signals FS 1 -FS 3 ). The third programming signal PS 3 activates the initialization of the injection of test errors (i.e., the first through third test errors TE 1 -TE 3 ) in the functional signals (i.e., the first through third functional signals FS 1 -FS 3 ), based on the error reaction associated with the test errors (i.e., the first through third test errors TE 1 -TE 3 ). In an embodiment, the second and third programming signals PS 2 and PS 3 initiate the activation of the error injection phase for outputting the first and second reaction signals RS 1 and RS 2 .

The first programming signal PS 1 can be generated by the core circuit 108 , based on the second and third programming signals PS 2 and PS 3 . The first programming signal PS 1 can be generated such that, the first programming signal PS 1 is indicative of the injection of the first through third test errors TE 1 -TE 3 in the first through third functional signals FS 1 -FS 3 , respectively. Therefore, when the second and third programming signals PS 2 and PS 3 are received by the error management system 110 and the first programming signal PS 1 is generated by the core circuit 108 , the error injection phase is activated. Although in the presently preferred embodiment, the error injection phase is activated by way of the second and third programming signals PS 2 and PS 3 , it will be apparent to a person skilled in the art that the scope of the present disclosure is not limited to it. In various other embodiments, the error injection phase can be activated by way of the first programming signal PS 1 .

When the error injection phase is activated, the error management system 110 receives the activated first through third error signals ES 1 -ES 3 , sequentially. In another embodiment, the second and third error signals ES 2 and ES 3 may be received before the first error signal ES 1 . The error management system 110 determines by way of the second and third programming signals PS 2 and PS 3 , a number of error signals associated with a corresponding error reaction. Thus, the error management system 110 waits until all the error reactions associated with the corresponding error reaction are received. When all the error signals associated with the corresponding error reaction are received, the error management system 110 can generate a corresponding reaction signal in response to all the error signals associated with the error reaction. For example, the first and second test errors TE 1 and TE 2 are associated with the first error reaction. When the error management system 110 receives the activated first error signal ES 1 indicating the detection of the first test error TE 1 , the error management system 110 stores the first test error TE 1 by way of activating a bit in a corresponding register set of a second plurality of registers 208 b as explained in detail in FIG. 2 . Further, the error management system 110 waits until the error management system 110 receives the activated second error signal ES 2 indicating the detection of the second test error TE 2 . On reception of the activated second error signal ES 2 , the error management system 110 generates the first reaction signal RS 1 that is indicative of the first error reaction in response to both the first and second test errors TE 1 and TE 2 . In another example, a single test error such as the third test error TE 3 is associated with a single error reaction such as the second error reaction. When the error management system 110 receives the activated third error signal ES 3 that indicates the detection of the third test error TE 3 , the second reaction signal RS 2 indicative of the second error reaction is generated by the error management system 110 . It will be understood by a person skilled in the art that when additional bits are activated by the second programming signal PS 2 in the first plurality of registers 208 a and the error management system 110 receives additional error signals corresponding to additional functional signals, the error management system 110 determines whether each of the error signals requires at least one of the first or second reactions. Based on the determination, the error management system 110 waits until all the error signals corresponding to the same reaction are received to generate a common reaction signal in response to all test errors requiring the same reaction.

When the error management system 110 receives an activated error signal and a deactivated injection signal, the error management system 110 generates an instant reaction signal in response to the detected functional error. Thus, when the error management system 110 receives the activated fourth and fifth error signals ES 4 and ES 5 and the deactivated fourth and fifth injection signals IJ 4 and IJ 5 to indicate detection of the first and second functional errors, the error management system 110 generates the third and fourth reaction signals RS 3 and RS 4 , instantly. For example, when the error management system 110 receives the activated fourth error signal ES 4 indicating the detection of the first functional error, the error management system 110 generates the third reaction signal RS 3 indicative of the third error reaction, instantly. Similarly, when the error management system 110 receives the activated fifth error signal ES 5 indicating the detection of the second functional error, the error management system 110 generates the fourth reaction signal RS 4 indicative of the fourth error reaction, instantly.

In one scenario, when the error injection phase is activated and the error management system 110 receives a sixth error signal (not shown) that is deactivated and a sixth injection signal (not shown) that is activated, the error management system 110 determines whether activated bits corresponding to the sixth error signal are present in the error management system 110 . If the corresponding bits are activated, the error management system 110 determines that the sixth error signal is erroneously deactivated by the error detection circuitry 106 . In such a scenario, the error management system 110 processes the sixth error signal similar to the first through third error signals ES 1 -ES 3 .

In another scenario, when the error management system 110 receives a seventh error signal (not shown) that is deactivated and a seventh injection signal (not shown) that is activated and the error management system 110 determines that bits corresponding to the seventh error signal are not activated, the error management system 110 further determines that the seventh injection signal is corrupted. As a result, the error management system 110 determines that the seventh error signal indicates that no error is detected in a corresponding functional signal. Similarly, the error management system 110 can determine if any error signals (i.e., the first through fifth error signals ES 1 -ES 5 ) and any injection signals (i.e., the first through fifth injection signals IJ 1 -IJ 5 ) are corrupted.

In yet another scenario, when a functional error is not present or the injection circuitry 104 does not inject a test error in a corresponding functional signal, the error detection circuitry 106 does not generate an activated error signal and an activated injection signal and passes the received functional signal as it is to the error management system 110 . The error management system 110 further passes the received functional signal as it is to the corresponding device without generating any reaction signal.

In yet another scenario, when the error management system 110 receives an eighth error signal that has both a functional error and an injected test error, the error management system 110 generates a corresponding reaction signal in response to the functional error in a manner similar to generating the third reaction signal RS 3 in response to the first functional error. The error management system 110 further generates another reaction signal in response to the injected test error in a manner similar to the generation of the first error signal ES 1 in response to the first test error TE 1 .

The error management system 110 can be further configured to provide the first and third reaction signals RS 1 and RS 3 to the first and second receiving circuits 112 a and 112 b. Further, the second and fourth reaction signals RS 2 and RS 4 can be provided to the third and fifth functional circuits 102 c and 102 e. The first and second receiving circuits 112 a and 112 b can be coupled with the error management system 110 . The first and second receiving circuits 112 a and 112 b can include suitable circuitry that can be configured to perform one or more operations. For example, on the reception of the first through fourth reaction signals RS 1 -RS 4 , the first and second receiving circuits 112 a and 112 b can be configured to execute first and third reaction operations, respectively. Examples of the reaction operations include, but are not limited to reset, an interrupt, or a non-maskable interrupt of the SoC 100 . When a reaction signal of the first and second reaction signals RS 1 and RS 2 is associated with a reset reaction, the corresponding receiving circuit can correspond to a reset controller. Therefore, based on an error reaction, the first and second receiving circuits 112 a and 112 b can correspond to different components. Further, it will be apparent to a person skilled in the art that when the error management system 110 generates more than four reaction signals (i.e., more than the first through fourth reaction signals RS 1 -RS 4 ), the SoC 100 may include more than two receiving circuits (i.e., more than the first and second receiving circuits 112 a and 112 b ).

FIG. 2 illustrates a schematic block diagram of the error management system 110 of the SoC 100 of FIG. 1 , in accordance with an embodiment of the present disclosure. The error management system 110 can include a sampling circuit 202 , an error tracking circuit 204 , and a reaction circuit 206 .

The sampling circuit 202 can be coupled with the error detection circuitry 106 (i.e., the first through fifth error detection circuits 106 a - 106 e ). The sampling circuit 202 can be further configured to receive the first through fifth error signals ES 1 -ES 5 and the first through fifth injection signals IJ 1 -IJ 5 from the first through fifth error detection circuits 106 a - 106 e , respectively. The sampling circuit 202 may include suitable circuitry that can be configured to perform one or more operations. For example, the sampling circuit 202 can be configured to output first through third activation signals AS 1 -AS 3 and first and second functional error signals FE 1 and FE 2 , based on the first through fifth injection signals IJ 1 -IJ 5 , respectively. Further, the sampling circuit 202 can be configured to provide the first through third activation signals AS 1 -AS 3 to the error tracking circuit 204 . Moreover, the sampling circuit 202 can be configured to provide the first and second functional error signals FE 1 and FE 2 to the reaction circuit 206 .

The sampling circuit 202 receives the activated first through third error signals ES 1 -ES 3 and the activated first through third injection signals IJ 1 -IJ 3 , indicating detection of the first through third test errors TE 1 -TE 3 in the first through third functional signals FS 1 -FS 3 , respectively. Therefore, based on the reception of the activated first through third error signals ES 1 -ES 3 and the activated first through third injection signals IJ 1 -IJ 3 , the sampling circuit 202 can output the first through third activation signals AS 1 -AS 3 , respectively. In the presently preferred embodiment, as the first through third error signals ES 1 -ES 3 are received sequentially, the first through third activation signals AS 1 -AS 3 are outputted sequentially.

Similarly, the sampling circuit 202 can receive the activated fourth and fifth error signals ES 4 and ES 5 and the deactivated fourth and fifth injection signals IJ 4 and IJ 5 , indicating detection of the first and second functional errors in the fourth and fifth functional signals FS 4 and FS 5 , respectively. Thus, based on the reception of the activated fourth and fifth error signals ES 4 and ES 5 and the deactivated fourth and fifth injection signals IJ 4 and IJ 5 , the sampling circuit 202 can output the first and second functional error signals FE 1 and FE 2 , respectively. The first and second functional error signals FE 1 and FE 2 are indicative of the first and second functional errors, respectively. Further, the first and second functional error signals FE 1 and FE 2 are also indicative of the error reactions associated with the first and second functional errors (i.e., the third and fourth error reactions). Thus, the sampling circuit 202 outputs an activation signal when a corresponding injection signal indicates a test error, and a functional error signal when a corresponding injection signal indicates a functional error.

The error tracking circuit 204 can be coupled with the sampling circuit 202 . Further, the error tracking circuit 204 can be configured to receive the first through third activation signals AS 1 -AS 3 from the sampling circuit 202 . The error tracking circuit 204 can be further coupled with the core circuit 108 . The error tracking circuit 204 is further configured to receive the second and third programming signals PS 2 and PS 3 and generate first and second indication signals ID 1 and ID 2 . The first indication signal ID 1 is generated based on the reception of the first and second activation signals AS 1 and AS 2 , and the second indication signal ID 2 is generated based on the reception of the third activation signal AS 3 . Therefore, the error tracking circuit 204 generates an activated first indication signal ID 1 when the first and second activation signals AS 1 and AS 2 are received by the error tracking circuit 204 . Similarly, the error tracking circuit 204 generates an activated second indication signal ID 2 when the third activation signal AS 3 is received by the error tracking circuit 204 . Moreover, the error tracking circuit 204 can be coupled with the reaction circuit 206 . The error tracking circuit 204 can be configured to provide the first and second indication signals ID 1 and ID 2 to the reaction circuit 206 .

The error tracking circuit 204 can include first and second pluralities of registers 208 a and 208 b, a first register set R 1 , and a processing circuit 210 . The first plurality of registers 208 a can be coupled with the core circuit 108 and the processing circuit 210 . The first plurality of registers 208 a are configured to receive the second programming signal PS 2 from the core circuit 108 and a first tracking signal TS 1 from the processing circuit 210 . Based on the type of error reactions, the first plurality of registers 208 a can include second and third register sets R 2 and R 3 . In the presently preferred embodiment, the second register set R 2 can be associated with the first error reaction, and the third register set R 3 can be associated with the second error reaction. Thus, each register set of the first plurality of registers 208 a can be associated with a different error reaction.

The second and third register sets R 2 and R 3 of the first plurality of registers 208 a can include first and second pluralities of bits, respectively. The first and second pluralities of bits can be based on a number of error signals supported by the error management system 110 . In an example, the first and second pluralities of bits correspond to four bits, however, it will be apparent to a person skilled in the art that the scope of the present disclosure is not limited to it. In various other embodiments, the first and second pluralities of bits can correspond to more than four bits.

Based on the reception of the second programming signal PS 2 , first and second bits of the second register set R 2 and a third bit of the third register set R 3 can be activated to indicate the injection of test errors (i.e., the first through third test errors TE 1 -TE 3 ) in the functional signals (i.e., the first through third functional signals FS 1 -FS 3 ). The core circuit 108 can determine a number of test errors that need to be injected to test the SoC 100 . The core circuit 108 further determines a type of reaction associated with each error. Based on the determination of the number of test errors and the type of reaction, the core circuit 108 indicates by way of the second programming signal PS 2 , a number of bits that need to be activated in each of the second and third register sets R 2 and R 3 of the first plurality of registers 208 a. In an example, the second programming signal PS 2 activates two bits associated with the same reaction such as the first and second bits of the second register set R 2 , and a single bit associated with another reaction such as the third bit of the third register set R 3 . As the first and second bits of the second register set R 2 are activated and associated with the first error reaction, the first and second test errors TE 1 and TE 2 are associated with the first error reaction. Similarly, the third test error TE 3 is associated with the second error reaction as the third bit of the third register set R 3 is associated with the second error reaction. Further, the activated first through third bits in the first plurality of registers 208 a can be tracked by the processing circuit 210 , by way of the first tracking signal TS 1 .

The first through third test errors TE 1 -TE 3 are injected in the first through third functional signals FS 1 -FS 3 , based on the activation of the first through third bits, respectively. In other words, the first programming signal PS 1 is provided to the injection circuitry 104 based on the provision of the second programming signal PS 2 by the core circuit 108 to the error management system 110 . In another embodiment, the first and second programming signals PS 1 and PS 2 are simultaneously provided to the injection circuitry 104 and the error management system 110 , respectively.

The second plurality of registers 208 b can be coupled with the sampling circuit 202 and the processing circuit 210 . The second plurality of registers 208 b can be configured to receive the first through third activation signals AS 1 -AS 3 from the sampling circuit 202 and a second tracking signal TS 2 from the processing circuit 210 . The second plurality of registers 208 b can include fourth and fifth register sets R 4 and R 5 . The second plurality of registers 208 b can be grouped into the second plurality of register sets based on a type of error reaction. In the presently preferred embodiment, the fourth register set R 4 can be associated with the first error reaction and the fifth register set R 5 can be associated with the second error reaction. Each register set of the second plurality of registers 208 b can be associated with a different error reaction. Further, the second plurality of registers 208 b can be utilized to store the test errors (i.e., the first through third test errors TE 1 -TE 3 ) by way of activating corresponding bits in the fourth and fifth register sets R 4 and R 5 .

The fourth and fifth register sets R 4 and R 5 of the second plurality of registers 208 b can include third and fourth pluralities of bits, respectively. The third and fourth pluralities of bits can be equal to the first and second pluralities of bits, respectively. In a presently preferred embodiment, the first and second pluralities of bits correspond to four bits, therefore the third and fourth pluralities of bits can correspond to four bits. However, it will be apparent to a person skilled in the art that the scope of the present disclosure is not limited to it.

Based on the reception of the first and second activation signals AS 1 and AS 2 , fourth and fifth bits of the fourth register set R 4 can be activated. Further, based on the reception of the third activation signal AS 3 , a sixth bit of the fifth register set R 5 can be activated. In other words, the fourth and fifth bits of the fourth register set R 4 and the sixth bit of the fifth register set R 5 can be activated by way of the first through third activation signals AS 1 -AS 3 , respectively. Thus, the sampling circuit 202 by way of each activation signal of the first through third activation signals AS 1 -AS 3 , can be configured to activate a corresponding bit in the second plurality of registers 208 b . Further, the second plurality of registers 208 b can receive the first through third activation signals AS 1 -AS 3 , sequentially, therefore, the fourth through sixth bits are activated sequentially. However, it will be apparent to a person skilled in the art that an order of activation of the fourth through sixth bits is not limited to activating the fourth through sixth bits sequentially. In various other embodiments, the order of activation of the fourth through sixth bits may vary if any of the second and third activation signals AS 2 and AS 3 are received before the first activation signal AS 1 , without deviating from the scope of the present disclosure. Further, the activated fourth through sixth bits in the second plurality of registers 208 b can be tracked by the processing circuit 210 , by way of the second tracking signal TS 2 .

The first register set R 1 can be coupled with the core circuit 108 . The core circuit 108 can be configured to provide the third programming signal PS 3 simultaneously with the second programming signal PS 2 to the error management system 110 . The core circuit 108 generates the third programming signal PS 3 to activate a number of bits associated with the type of error reactions of the first through third test errors TE 1 -TE 3 . When both the second and third programming signals PS 2 and PS 3 are provided to the error management system 110 , the core circuit 108 generates and provides the first programming signal PS 1 to the injection circuitry 104 to inject the first through third test errors TE 1 -TE 3 . The first register set R 1 can be configured to receive the third programming signal PS 3 . Further, the first register set R 1 can include a fifth plurality of bits of which seventh and eighth bits are shown. Each bit of the first register set R 1 can be associated with an error reaction. For example, the seventh bit of the first register set R 1 can be associated with the first error reaction, and the eighth bit of the first register set R 1 can be associated with the second error reaction. In the presently preferred embodiment, the first register set R 1 includes two bits (i.e., the seventh and eighth bits) associated with the first and second error reactions, respectively. However, it will be apparent to a person skilled in the art that the scope of the present disclosure is not limited to it, and in various other embodiments, the first register set R 1 can include more than two bits, each associated with a different error reaction, without deviating from the scope of the present disclosure.

Based on the reception of the third programming signal PS 3 , the seventh and eighth bits of the first register set R 1 can be activated. In other words, the seventh and eighth bits of the first register set R 1 are activated by way of the third programming signal PS 3 .

The first register set R 1 can be utilized to initiate the injection of test errors associated with the corresponding error reaction. For example, when the seventh bit associated with the first error reaction is activated, based on the activated first and second bits of the second register set R 2 that is associated with the first error reaction, the first and second test errors TE 1 and TE 2 can be injected in the first and second functional signals FS 1 and FS 2 , respectively. In other words, the first and second test errors TE 1 and TE 2 can be injected when the first and second bits in the second register set R 2 and the seventh bit in the first register set R 1 are activated. Therefore, the error injection phase for the first error reaction is activated when both the first and second bits in the second register set R 2 and the seventh bit in the first register set R 1 are activated. Thus, the first programming signal PS 1 is provided to the injection circuitry 104 when both the second and third programming signals PS 2 and PS 3 are provided to the error management system 110 . Similarly, when the eighth bit associated with the second error reaction is activated, based on the activated third bit of the third register set R 3 that is associated with the second error reaction, the third test error TE 3 can be injected in the third functional signal FS 3 . Therefore, the error injection phase for the second error reaction is activated when the third bit in the third register set R 3 and the eighth bit in the first register set R 1 are activated.

Based on the injection of the first through third test errors TE 1 -TE 3 in the first through third functional signals FS 1 -FS 3 , respectively, the first through third error signals ES 1 -ES 3 are outputted by the error detection circuitry 106 (i.e., by the first through third error detection circuits 106 a - 106 c ), sequentially. Further, based on the reception of the first through third error signals ES 1 -ES 3 , the first through third activation signals AS 1 -AS 3 are outputted and provided by the sampling circuit 202 to the second plurality of registers 208 b , sequentially.

The processing circuit 210 can be coupled with the first and second pluralities of registers 208 a and 208 b. The processing circuit 210 may include suitable circuitry that can be configured to perform one or more operations. The processing circuit 210 can be configured to generate the first and second tracking signals TS 1 and TS 2 and track an activation status of each of the first through third bits by way of the first tracking signal TS 1 and the fourth through sixth bits by way of the second tracking signal TS 2 . The processing circuit 210 can be further configured to generate first and second indications signals ID 1 and ID 2 , sequentially. Further, the processing circuit 210 can be configured to provide the first and second indication signals ID 1 and ID 2 to the reaction circuit 206 .

The processing circuit 210 generates an activated first indication signal ID 1 when a number of the activated bits in the second register set R 2 matches a number of the activated bits in the fourth register set R 4 . In the presently preferred embodiment, the processing circuit 210 generates the activated first indication signal ID 1 when the fourth and fifth bits of the fourth register set R 4 are activated. Further, the processing circuit 210 generates an activated second indication signal ID 2 when a number of the activated bits in the third register set R 3 matches a number of the activated bits in the fifth register set R 5 . In the presently preferred embodiment, the processing circuit 210 generates the activated second indication signal ID 2 when the sixth bit of the fifth register set R 5 is activated.

The processing circuit 210 generates a deactivated first indication signal ID 1 when the number of the activated bits in the second register set R 2 does not match the number of the activated bits in the fourth register set R 4 . In the presently preferred embodiment, the processing circuit 210 generates the deactivated first indication signal ID 1 when any one of the fourth and fifth bits of the fourth register set R 4 are deactivated. For example, when the second plurality of registers 208 b receives the first activation signal AS 1 , the fourth bit of the fourth register set R 4 is activated. The fifth bit is deactivated, as the second activation signal AS 2 is not yet received by the second plurality of registers 208 b. In such a scenario, the processing circuit 210 generates the deactivated first indication signal ID 1 until the fifth bit is activated by the second activation signal AS 2 . Similarly, the processing circuit 210 generates a deactivated second indication signal ID 2 when the number of the activated bits in the third register set R 3 does not match the number of the activated bits in the fifth register set R 5 . In an example, the processing circuit 210 generates the deactivated second indication signal ID 2 when the sixth bit of the fifth register set R 5 is deactivated. In the presently preferred embodiment, the processing circuit 210 provides the first and second indication signals ID 1 and ID 2 to the reaction circuit 206 , sequentially.

The reaction circuit 206 can be coupled with the processing circuit 210 and the sampling circuit 202 . Further, the reaction circuit 206 can be configured to receive the first and second indication signals ID 1 and ID 2 from the processing circuit 210 , and the first and second functional error signals FE 1 and FE 2 from the sampling circuit 202 . The reaction circuit 206 may include suitable circuitry that can be configured to perform one or more operations. For example, the reaction circuit 206 can be further configured to generate the first through fourth reaction signals RS 1 -RS 4 . Further, the reaction circuit 206 can be configured to provide the first and third reaction signals RS 1 and RS 3 to the first and second receiving circuits 112 a and 112 b, respectively. On receiving the first through fourth reaction signals RS 1 -RS 4 , the first receiving circuit 112 a, the third functional circuit 102 c, the second receiving circuit 112 b, and the fifth functional circuit 102 e can be further configured to execute the corresponding error reactions, respectively.

The reaction circuit 206 can generate the first reaction signal RS 1 in response to the first and second test errors TE 1 and TE 2 . Therefore, the first reaction signal RS 1 can be indicative of the first error reaction. Further, the reaction circuit 206 can generate the first reaction signal RS 1 when the reaction circuit 206 receives the activated first indication signal ID 1 . Similarly, the reaction circuit 206 can generate the second reaction signal RS 2 in response to the third test error TE 3 . Therefore, the second reaction signal RS 2 can be indicative of the second error reaction. Further, the reaction circuit 206 can generate the second reaction signal RS 2 when the reaction circuit 206 receives the activated second indication signal ID 2 . In the presently preferred embodiment, as the reaction circuit 206 receives the activated first and second indication signals ID 1 and ID 2 , one after the other, therefore, the reaction circuit 206 can generate the first and second reaction signals RS 1 and RS 2 one after the other.

The reaction circuit 206 can generate the third reaction signal RS 3 in response to the first functional error. Therefore, the third reaction signal RS 3 can be indicative of the third error reaction. Further, the reaction circuit 206 can generate the third reaction signal RS 3 when the reaction circuit 206 receives the first functional error signal FE 1 . Similarly, the reaction circuit 206 can generate the fourth reaction signal RS 4 in response to the second functional error, i.e., when the reaction circuit 206 receives the second functional error signal FE 2 . Therefore, the fourth reaction signal RS 4 can be indicative of the fourth error reaction. In the presently preferred embodiment, as the reaction circuit 206 receives the first and second functional error signals FE 1 and FE 2 , one after the other, the reaction circuit 206 can generate the third and fourth reaction signals RS 3 and RS 4 , one after the other. In an example, the first and second test errors TE 1 and TE 2 are parity errors, and the first error reaction is a reset reaction. Therefore, the first reaction signal RS 1 is provided to the first receiving circuit 112 a such that the first receiving circuit 112 a resets on receiving the first reaction signal RS 1 . Similarly, the third test error TE 3 is a lockstep error, and the second error reaction is an interrupt reaction, therefore, the second reaction signal RS 2 can be provided to the third functional circuit 102 c such that an operation of the third functional circuit 102 c is interrupted on receiving the second reaction signal RS 2 . Further, the first and second functional errors can be lockstep and parity errors, respectively, and the third and fourth error reactions can be reset reactions. Therefore, the third and fourth reaction signals RS 3 and RS 4 are provided to the second receiving circuit 112 b and various circuitries (not shown) of the SoC 100 , to reset the second receiving circuit 112 b and the SoC 100 , respectively.

The error management system 110 of the present disclosure differentiates the first through third test errors TE 1 -TE 3 and the first and second functional errors, by way of the error detection circuitry 106 . Therefore, the error management system 110 is not limited to an error correction code (ECC) checker. Further, the error management system 110 generates the first reaction signal RS 1 in response to both the first and second test errors TE 1 and TE 2 and waits to generate the first reaction signal RS 1 until both the first and second error signals ES 1 and ES 2 are received. Thus, the error management system 110 generates a single reaction in response to multiple test errors that are associated with the same error reaction. Due to a single reaction in response to multiple test errors requiring the same reaction, a number of processing cycles of the SoC 100 reduces. Moreover, availability of the functional circuits (i.e., the first through fifth functional circuits 102 a - 102 e ) to execute functional operations increases as a single reaction is executed by grouping the same set of errors as compared to conventional error management systems that generate a reaction signal instantly on receiving each injected test error.

While various embodiments of the present disclosure have been illustrated and described, it will be clear that the present disclosure is not limited to these embodiments only. Numerous modifications, changes, variations, substitutions, and equivalents will be apparent to those skilled in the art, without departing from the spirit and scope of the present disclosure, as described in the claims. Further, unless stated otherwise, terms such as “first” and “second” are used to arbitrarily distinguish between the elements such terms describe. Thus, these terms are not necessarily intended to indicate temporal or other prioritization of such elements.