Bridge circuit with series-connected switches and control method thereof

This application claims the benefit of CN application 202010741287.9, filed on Jul. 29, 2020, and incorporated herein by reference.

The present invention generally relates to electronic circuits, and more particularly but not exclusively, to a bridge circuit with series-connected switches and control method thereof.

In high-power and high-voltage applications, using series-connected power devices is a good choice. However, a main concern of the series-connected power devices is the unbalanced static and dynamic voltage sharing mainly caused by parameter difference of each series-connected power device (e.g. gate threshold voltage and junction capacitance) and gate signal delays. To solve this problem, traditional methods can be classified into three main types: passive snubber circuits, gate control circuits and voltage clamping circuits.

A passive snubber circuit can balance the voltage of the series-connected power devices by connecting a circuit composed of capacitors, resistors, semiconductor diodes or their combinations in parallel with each series-connected power device. However, a large snubber capacitor of the passive snubber circuit causes obvious snubber loss, increases the volume and reduces the switching speed of the series-connected power devices, which is not available in high frequency applications. A gate drive control circuit can balance the voltage of the series-connected power devices by sampling voltages of the series-connected power devices and adjusting the delay or voltage amplitude of the gate drive signals. However, it is necessary to introduce additional voltage sensing circuits and gate signal drive delay or voltage amplitude compensation circuits, which increases the cost and the complexity. A voltage clamping circuit can balance the voltage of the series-connected power devices by connecting a circuit comprising clamping capacitors, resistors, semiconductor diodes or their combinations coupled in parallel with each series-connected power device. The circuit absorbs the voltage spike when the series-connected power devices are asynchronous and clamps the voltage of the series-connected power devices to the capacitor voltage. Thus, to balance the voltages of the series-connected power devices is to balance the capacitor voltages. A resistor is usually connected in parallel with each series-connected power device to achieve the static voltage sharing, and the excess energy absorbed by the clamping capacitor is generally consumed on the resistor, which increases the power loss.

To overcome the shortcomings of the existing technology, the present invention provides a bridge circuit with series-connected switches and control method thereof.

Embodiments of the present invention are directed to a bridge circuit with series-connected switches, comprising: a first bridge arm, a second bridge arm, a voltage sensing circuit and a control circuit. The first bridge arm comprises a first terminal, a second terminal and a control terminal. A plurality of series-connected first main switches are coupled between the first terminal and the second terminal. Each of the plurality of series-connected first main switches is coupled in parallel with a first auxiliary module, each first auxiliary module comprises a first clamping capacitor and a first auxiliary switch, and the control terminal is configured to receive a first main switch signal to control the plurality of series-connected first main switches. The second bridge arm comprises a first terminal, a second terminal, a control terminal and at least a second main switch. The first terminal of the second bridge arm is coupled with the second terminal of the first bridge arm at a common node, and the control terminal of the second bridge arm is configured to receive a second main switch signal to control the at least a second main switch. The voltage sensing circuit is configured to sample voltages of the first clamping capacitors in the first bridge arm, and is configured to correspondingly generate first voltage sensing signals according to the voltages of the first clamping capacitors. The control circuit, configured to receive the first voltage sensing signals and correspondingly generate first auxiliary switch signals according to the first voltage sensing signals and a first dead time to respectively control the first auxiliary switches.

Embodiments of the present invention are directed to a control method for a bridge circuit with series-connected switches, wherein the bridge circuit comprises a first bridge arm and a second bridge arm. The first bridge arm comprises a plurality of series-connected first main switches. Each of the plurality of series-connected first main switch is coupled in parallel with a first auxiliary module. Each first auxiliary module comprises a first clamping capacitor and a first auxiliary switch. The second bridge arm comprises at least a second main switch. The first bridge arm is configured to receive a first main switch signal to control the plurality of series-connected first main switches. The second bridge arm is configured to receive a second main switch signal to control the at least a second main switch. The control method comprises sensing voltages of the first clamping capacitors in the first bridge arm and correspondingly generating first voltage sensing signals; and turning on at least one first auxiliary switch for a predetermined time during a first dead time according to a sorting result of the first voltage sensing signals, wherein the predetermined time is equal to or less than the first dead time.

Embodiments of the present invention are directed to a control method for a bridge circuit with series-connected switches, wherein the bridge circuit comprises a first bridge arm and a second bridge arm coupled at a common node. The first bridge arm comprises a plurality of series-connected first main switches. Each of the plurality of series-connected first main switch is coupled in parallel with an auxiliary module. Each auxiliary module comprises a clamping capacitor and an auxiliary switch. The second bridge arm comprises at least a second main switch. The first bridge arm is configured to receive a first main switch signal to control the plurality of series-connected first main switches. The second bridge arm is configured to receive a second main switch signal to control the at least a second main switch. The control method comprises sensing voltages of the clamping capacitors in the first bridge arm and correspondingly generating voltage sensing signals; and turning on at least one auxiliary switch for a predetermined time during a first dead time according to a sorting result of the voltage sensing signals, wherein the predetermined time is equal to or less than the first dead time; wherein the first dead time is configured to be a time from a falling edge of the second main switch signal to a rising edge of the first main switch signal.

Compared with the prior art solution, the advantages of the present invention are: the control method of the present invention uses the freewheeling current during the dead time to discharge the clamping capacitor without the static resistance, and therefore the power loss induced by voltage balance is extremely low; in the control method of the present invention, the clamping capacitor is only inserted into the circuit during the dead time, which does not affect the switching speed and the normal operation of the main switch; in the inverter circuit and its control method of the present invention, the clamping capacitor is only inserted during the dead time for voltage balance, rather than an energy storage unit, which greatly reduces the capacitance and volume of the capacitor required in the bridge circuit compared with the modular multilevel converter (MMC) and improves the power density; the bridge circuit of the present invention is beneficial to modularization, fault protection and redundancy.

The present invention can be further understood with reference to the following detailed description and the appended drawings, wherein like elements are provided with like reference numerals.

FIG. 1 is a block diagram of a half bridge circuit with series-connected switches 1000 in accordance with an embodiment of the present invention.

FIG. 2 schematically illustrates a circuit diagram of a first bridge arm 10 and a second bridge arm 20 in the half bridge circuit with series-connected switches 1000 in accordance with an embodiment of the present invention.

FIG. 3 is a block diagram of a full bridge circuit with series-connected switches 2000 in accordance with an embodiment of the present invention.

FIG. 4 schematically illustrates a circuit diagram of a third bridge arm 30 and a fourth bridge arm 40 in the full bridge circuit with series-connected switches 2000 in accordance with an embodiment of the present invention.

FIG. 5 schematically illustrates a circuit diagram of a control circuit 60 in accordance with an embodiment of the present invention.

FIG. 6 is a flow chart of a control method 3000 used in a bridge circuit with series-connected switches in accordance with an embodiment of the present invention.

FIG. 7 schematically illustrates a circuit diagram of a bridge circuit with series-connected switches coupled in a resonant circuit (i.e. an LLC resonant circuit with series-connected switches) in accordance with an embodiment of the present invention.

FIG. 8 illustrates working waveforms of the LLC resonant circuit with series-connected switches shown in FIG. 7 in accordance with an embodiment of the present invention.

FIG. 9 is a circuit modal diagram of the second bridge arm 20 within a second dead time in the waveforms shown in FIG. 8 in accordance with an embodiment of the present invention.

FIG. 10 is a circuit modal diagram of the first bridge arm 10 within a first dead time in the waveforms shown in FIG. 8 in accordance with an embodiment of the present invention.

FIG. 11 illustrates working waveforms of the clamping capacitors voltage when the LLC resonant circuit is in steady state (taking 4 series-connected switches in each arm as an example) in accordance with an embodiment of the present invention.

FIG. 12 schematically illustrates a circuit diagram of a bridge circuit with series-connected switches coupled in an inverter circuit (i.e. an inverter circuit with series-connected switches) in accordance with an embodiment of the present invention.

FIG. 13 illustrates working waveforms of the inverter circuit with series-connected switches shown in FIG. 12 in two output ac cycles in accordance with an embodiment of the present invention.

FIG. 14 is a circuit mode diagram of the first bridge arm 10 in each stage of the working waveform shown in FIG. 13 in accordance with an embodiment of the present invention.

FIG. 15 illustrates working waveforms of the inverter circuit with series-connected switches in the Steady Voltage Stage shown in FIG. 13 in accordance with an embodiment of the present invention.

FIG. 16 illustrates working waveforms of the clamping capacitors voltage of the first bridge arm 10 and the second bridge arm 20 when the inverter circuit is in steady state (taking 4 series-connected switches as an example) in accordance with an embodiment of the present invention.

FIG. 17 is a flow chart of a control method of the LLC resonant circuit with series-connected switches in accordance with an embodiment of the present invention.

FIG. 18 is a flow chart of a control method of the inverter circuit with series-connected switches in accordance with an embodiment of the present invention.

Reference will now be made in detail to the preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. While the invention will be described in conjunction with the preferred embodiments, it will be understood that they are not intended to limit the invention to these embodiments. On the contrary, the invention is intended to cover alternatives, modifications and equivalents, which may be included within the spirit and scope of the invention as defined by the appended claims. Furthermore, in the following detailed description of the present invention, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be obvious to one of ordinary skill in the art that the present invention may be practiced without these specific details. In other instances, well-known methods, procedures, components, and circuits have not been described in detail so as not to unnecessarily obscure aspects of the present invention.

FIG. 1 is a block diagram of a half bridge circuit 1000 with series-connected switches in accordance with an embodiment of the present invention. The half bridge circuit 1000 comprises a first bridge arm 10 , a second bridge arm 20 , a voltage sensing circuit 50 , and a control circuit 60 . The first bridge arm 10 comprises a first terminal 101 , a second terminal 102 , and a control terminal 103 , wherein the control terminal 103 is configured to receive a first main switch signal g. The second bridge arm 20 comprises a first terminal 201 , a second terminal 202 , and a control terminal 203 , wherein the first terminal 201 of the second bridge arm 20 is coupled with the second terminal 102 of the first bridge arm 10 at a common node M 1 , and the control terminal 203 is configured to receive a second main switch signal g′. The half bridge circuit 1000 is configured to output an output current it and an output voltage vr at the common node M 1 .

In an embodiment of the present invention, ad time are included between the first main switching signal g and the second main switching signal g′, during the first dead time, the plurality of series-connected first main switches and the at least a second main switch are off. Wherein when the output current ir is configured to lag behind the output voltage vr (e.g. the circuit coupled to the half bridge circuit 1000 is inductive), the first dead time is the dead time before the rising edge of the first main switch signal g, and the second dead time is the dead time before the rising edge of the second main switch signal g′; and when the output current ir is configured to lead the output voltage vr (e.g. the circuit coupled to the half bridge circuit 1000 is capacitive), the first dead time is the dead time before the rising edge of the second main switch signal g′, and the second dead time is the dead time before the rising edge of the first main switch signal g. In an embodiment of the present invention, the first main switch signal g is complementary to the second main switch signal g′. In an embodiment of the present invention, the first dead time or the second dead time is not limited to the duration of the dead time, but also includes the moment of the dead time (e.g. the start moment, the end moment, or even the moment a little before the start moment), etc. The first dead time or the second dead time can also represent the freewheeling time in the bridge circuit.

FIG. 2 ( a ) schematically illustrates a circuit diagram of the first bridge arm 10 in the half bridge circuit 1000 with series-connected switches. The first bridge arm 10 comprises N series-connected main switches S 11 ˜S 1 N, where N is a natural number greater than or equal to 2. The first main switch signal g is configured to control the N main switches S 11 ˜S 1 N. An auxiliary module ARM 1 N is connected in parallel with each main switch S 1 N (e.g. the auxiliary module ARM 11 is connected in parallel with the main switch S 11 , and the auxiliary module ARM 12 is connected in parallel with the main switch S 12 ). Each auxiliary module ARM 1 N comprises a clamping capacitor C 1 N and an auxiliary switch Sa 1 N (e.g. the auxiliary module ARM 11 comprises the clamping capacitor C 11 and the auxiliary switch Sa 11 ). In one embodiment, each auxiliary switch Sa 1 N comprises an anti-parallel diode and the voltage of each clamping capacitor C 1 N is vc 1 N (e.g. the voltage of the clamping capacitor C 11 is vc 11 ), wherein each auxiliary switch Sa 1 N receives an auxiliary switching signal ga 1 N (e.g. the auxiliary switch signal ga 11 is configured to control the auxiliary switch Sa 11 ). Combining the embodiments shown in FIG. 1 and FIG. 2 ( a ) , the voltage sensing circuit 50 is configured to sample the voltages vc 11 ˜vc 1 N of the clamping capacitors C 11 ˜C 1 N and correspondingly generate voltage sensing signals vc 11 ′˜vc 1 N′. The control circuit 60 is configured to receive the voltage sensing signals vc 11 ′˜vc 1 N′ and correspondingly generate the auxiliary switch signals ga 11 ˜ga 1 N according to the voltage sensing signals vc 11 ′˜vc 1 N′ and a first dead time to respectively control the auxiliary switches Sa 11 ˜Sa 1 N. In one embodiment of the present invention, when a certain voltage sensing signal vc 1 i ′ (i ranges from 1 to N) ranks at top M among the voltage sensing signals vc 11 ′˜vc 1 N′, the control circuit 60 is configured to control the auxiliary switch Sa 1 i corresponding to the certain voltage sensing signal vc 1 i ′ keeping on for at least a first predetermined time during the first dead time, wherein the first predetermined time is less than or equal to the first dead time and not limited to the first dead time, and M is a natural number greater than or equal to one, wherein the control circuit 60 can turn on the auxiliary switch Sa 1 i corresponding to the certain voltage sensing signal vc 1 i at a moment before the falling edge of the first main switch signal if the first dead time is after the falling edge of the first main switch signal or at a moment before the falling edge of the second main switch signal if the first dead time is after the falling edge of the second main switch signal. In one embodiment of the present invention, the auxiliary switch Sa 1 i can utilize the freewheeling current during the second dead time to discharge the corresponding clamping capacitor C 1 i . In one embodiment of the present invention, the first predetermined time can be set to a fixed value in advance. In other embodiments of the present invention, the first predetermined time can also be adjusted instantaneously or periodically based on needs, e.g. it can be calculated instantaneously by a digital controller or adjusted according to a feedback signal.

FIG. 2 ( b ) schematically illustrates a circuit diagram of the second bridge arm 20 in the half bridge circuit 1000 with series-connected switches. The second bridge arm 20 comprises N series-connected main switches S 21 ˜S 2 N. The second main switch signal g′ is configured to control the N main switches S 21 ˜S 2 N. An auxiliary module ARM 2 N is connected in parallel with each main switch S 2 N (e.g. the auxiliary module ARM 21 is connected in parallel with the main switch S 21 , and the auxiliary module ARM 22 is connected in parallel with the main switch S 22 ). Each auxiliary module ARM 2 N comprises a clamping capacitor C 2 N and an auxiliary switch Sa 2 N (e.g. the auxiliary module ARM 21 comprises the clamping capacitor C 21 and the auxiliary switch Sa 21 ). In one embodiment of the present invention, each auxiliary switch Sa 1 N comprises an anti-parallel diode and the voltage of each clamping capacitor C 2 N is vc 2 N (e.g. the voltage of the clamping capacitor C 21 is vc 21 ), wherein each auxiliary switch Sa 2 N receives an auxiliary switching signal ga 2 N (e.g. the auxiliary switch signal ga 21 is configured to control the auxiliary switch Sa 21 ). The voltage sensing circuit 50 is configured to sample the voltages vc 21 ˜vc 2 N of the clamping capacitors C 2 N˜C 2 N and correspondingly generate voltage sensing signals vc 11 ′˜vc 1 N′. The control circuit 60 is configured to receive the voltage sensing signals vc 21 ′˜vc 2 N′, and correspondingly generate the auxiliary switch signals ga 21 ˜ga 2 N according to the voltage sensing signals vc 21 ′˜vc 2 N′ and a second dead time to respectively control the auxiliary switches Sa 21 ˜Sa 2 N. In one embodiment of the present invention, when a certain voltage sensing signal vc 2 i ′ ranks at top K among the voltage sensing signals vc 21 ′˜vc 2 N′, the control circuit 60 is configured to control the auxiliary switch Sa 2 i corresponding to the certain voltage sensing signal vc 2 i ′ keeping on for at least a second predetermined time during the second dead time, wherein the second predetermined time is less than or equal to the second dead time and not limited to the second dead time, and K is a natural number greater than or equal to one. The first predetermined time can be equal to the second predetermined time and the natural number N can be equal to the natural number K. In one embodiment of the present invention, the auxiliary switch Sa 2 i can utilize the freewheeling current during the second dead time to discharge the corresponding clamping capacitor C 2 i.

FIG. 3 is a block diagram of a full bridge circuit 2000 with series-connected switches in accordance with an embodiment of the present invention. The difference from the half bridge circuit 1000 with series-connected switches shown in FIG. 1 is that, the full bridge circuit 2000 further comprises a third bridge arm 30 and a fourth bridge arm 40 . The third bridge arm 30 comprises a first terminal 301 , a second terminal 302 , and a control terminal 303 , wherein the control terminal 303 is configured to receive a second main switch signal g′. The fourth bridge arm 40 comprises a first terminal 401 , a second terminal 402 and a control terminal 403 , wherein the second terminal 302 of the third bridge arm 30 is coupled with the first terminal 401 of the fourth bridge arm 40 at a common node M 2 , and the control terminal 403 is configured to receive a first main switch signal g. The full bridge circuit 2000 outputs an output current it and an output voltage vr between the common node M 1 and the common node M 2 .

FIG. 4 ( a ) schematically illustrates a circuit diagram of the third bridge arm 30 in the full bridge circuit 2000 with series-connected switches. The third bridge arm 30 comprises N series-connected main switches S 31 ˜S 3 N. The second main switch signal g′ is configured to control the N main switches S 31 ˜S 3 N. An auxiliary module ARM 3 N is connected in parallel with each main switch S 3 N (e.g. the auxiliary module ARM 31 is connected in parallel with the main switch S 31 , and the auxiliary module ARM 32 is connected in parallel with the main switch S 32 ). Each auxiliary module ARM 3 N comprises a clamping capacitor C 3 N and an auxiliary switch Sa 3 N (e.g. auxiliary module ARM 31 comprises the clamping capacitor C 31 and the auxiliary switch Sa 31 ). In one embodiment of the present invention, each auxiliary switch Sa 3 N comprises an anti-parallel diode and the voltage of each clamping capacitor C 3 N is vc 3 N (e.g. the voltage of the clamping capacitor C 31 is vc 31 ), wherein each auxiliary switch Sa 3 N receives an auxiliary switching signal ga 3 N (e.g. the auxiliary switch signal ga 31 is configured to control the auxiliary switch Sa 31 ). The voltage sensing circuit 50 is configured to sample the voltages vc 31 ˜vc 3 N of the clamping capacitors C 31 ˜C 3 N and correspondingly generate voltage sensing signals vc 31 ′˜vc 3 N′. The control circuit 60 is configured to receive the voltage sensing signals vc 31 ′˜vc 3 N′, and correspondingly generate the auxiliary switch signals ga 31 ˜ga 3 N according to the voltage sensing signals vc 31 ′˜vc 3 N′ and the second dead time to respectively control the auxiliary switches Sa 31 ˜Sa 3 N. In one embodiment of the present invention, when a certain voltage sensing signal vc 3 i ′ is ranks at top P among the voltage sensing signals vc 31 ′˜vc 3 N′, the control circuit 60 is configured to control the auxiliary switch Sa 3 i corresponding to the certain voltage sensing signal vc 3 i ′ keeping on for at least a third predetermined time during the second dead time wherein the third predetermined time is less than or equal to the second dead time and not limited to the second dead time, and P is a natural number greater than or equal to one. The third predetermined time can be equal to the first predetermined time and the natural number P can be equal to the natural number M. In one embodiment of the present invention, the auxiliary switch Sa 3 i can utilize the freewheeling current during the second dead time to discharge the corresponding clamping capacitor C 3 i.

FIG. 4 ( b ) schematically illustrates a circuit diagram of the fourth bridge arm 40 in the full bridge circuit 2000 with series-connected switches. The fourth bridge arm 40 comprises N series-connected main switches S 41 ˜S 4 N. The first main switch signal g is configured to control the N main switches S 41 ˜S 4 N. An auxiliary module ARM 4 N is connected in parallel with each main switch S 4 N (e.g. the auxiliary module ARM 41 is connected in parallel with the main switch S 41 , and the auxiliary module ARM 42 is connected in parallel with the main switch S 42 ). Each auxiliary module ARM 4 N comprises a clamping capacitor C 4 N and an auxiliary switch Sa 4 N (e.g. auxiliary module ARM 41 comprises the clamping capacitor C 41 and the auxiliary switch Sa 41 ). In one embodiment of the present invention, each auxiliary switch Sa 4 N comprises an anti-parallel diode and the voltage of each clamping capacitor C 4 N is vc 4 N (e.g. the voltage of the clamping capacitor C 41 is vc 41 ), wherein each auxiliary switch Sa 4 N receives an auxiliary switching signal ga 4 N (e.g. the auxiliary switch signal ga 41 is configured to control the turn-on and turn-off of the auxiliary switch Sa 41 ). The voltage sensing circuit 50 is configured to sample the voltages vc 41 ˜vc 4 N of the clamping capacitors C 41 ˜C 4 N and correspondingly generate voltage sensing signals vc 41 ′˜vc 4 N′. The control circuit 60 is configured to receive the voltage sensing signals vc 41 ′˜vc 4 N′, and correspondingly generate the auxiliary switch signals ga 41 ˜ga 4 N according to the voltage sensing signals vc 41 ′˜vc 4 N′ and the first dead time to respectively control the auxiliary switches Sa 41 ˜Sa 4 N. In one embodiment of the present invention, when a certain voltage sensing signal vc 4 i ′ ranks at top Q among the voltage sensing signals vc 41 ′˜vc 4 N′, the control circuit 60 is configured to control the auxiliary switch Sa 4 i corresponding to the certain voltage sensing signal vc 4 i ′ keeping on for at least a fourth predetermined time during the first dead time wherein the fourth predetermined time is less than or equal to the first dead time and not limited to the first dead time, and Q is a natural number greater than or equal to one. The fourth predetermined time can be equal to the first predetermined time and the natural number Q is equal to or unequal to the natural number M. In one embodiment of the present invention, the auxiliary switch Sa 4 i utilizes the freewheeling current during the first dead time to discharge the corresponding clamping capacitor C 4 i.

In other embodiments of the present invention, the first bridge arm 10 , the second bridge arm 20 , the third bridge arm 30 , or the fourth bridge arm 40 may also comprise only one main switch (e.g. the first bridge arm 10 comprising multiple main switches connected in series, but the second bridge arm 20 , the third bridge arm 30 , and the fourth bridge arm 40 only comprising one main switch). In this case, the control circuit 60 can no longer perform the voltage balance control on the bridge arm with only one main switch. In the embodiment shown in FIG. 1 and FIG. 3 , the first bridge arm 10 , the second bridge arm 20 , the third bridge arm 30 and the fourth bridge arm 40 may comprise different number series-connected main switches. The main switch can be a power device with reverse freewheeling capability (e.g. IGBT, IGCT or MOSFET) or it can be a power device without reverse freewheeling capability but externally connected an anti-parallel diode. In one embodiment of the present invention, the capacitance of the clamp capacitor is much larger than that of the corresponding drain-source (or collector-emitter) parasitic capacitor of the main switch. In one embodiment of the present invention, the auxiliary switch comprises an anti-parallel diode, which can be an anti-parallel body diode of the auxiliary switch, or an external anti-parallel diode.

FIG. 5 schematically illustrates a circuit diagram of a control circuit 60 shown in FIG. 1 in accordance with an embodiment of the present invention. The control circuit comprises N sub-controllers 601 - 60 N and a main controller 600 . In an embodiment of the present invention, the sub-controllers 601 - 60 N and the central controller 600 can be FPGA (Field Programmable Gate Array) chips and the optical fiber communication can be adopted between the sub-controllers 601 - 60 N and the central controller 600 . Each sub-controller 60 i is configured to correspondingly receive the voltage sensing signal vc 1 i ′ and transmit it to the main controller 600 . The main controller 600 is configured to correspondingly receive the voltage sensing signals vc 11 ′-vc 1 N′ from the sub-controllers 601 - 60 N and configured to sort the voltage sensing signals vc 11 ′-vc 1 N′ according to their values. Then, the main controller 600 is configured to send turn-on instruction signals to ones of the plurality of sub-controllers corresponding to the voltage sensing signals ranking the top M among the voltage sensing signals and send turn-off instruction signals to rest of the plurality of sub-controllers. The sub-controller 60 i receiving the turn-on instruction signal is configured to correspondingly generate a gate drive signal ga 1 i ′ to the gate drive circuit 70 i , and the gate drive circuit 70 i is configured to correspondingly generate a turn-on signal ga 1 i to turn on the auxiliary switch Sa 1 i . The sub-controller receiving the turn-off instruction signal is configured to correspondingly generate a gate drive signal to the gate drive circuit, and the gate drive circuit is configured to correspondingly generate a turn-off signal to turn off the auxiliary switch. In one embodiment of the present invention, the turn-on instruction comprises a turn-on duration and a turn-on moment, which are generated according to the first dead time or the second dead time.

Note that the embodiment shown in FIG. 5 only illustrates the control circuit corresponding to the first bridge arm 10 . Other control circuits and methods (such as the second bridge arm 20 , the third bridge arm 30 and the fourth bridge arm 40 ) are similar to the embodiment shown in FIG. 5 .

FIG. 6 is a flow chart of a control method 3000 for a bridge circuit with series-connected switches in accordance with an embodiment of the present invention. It comprises steps S 31 ˜S 33 . The bridge circuit comprises a first bridge arm and a second bridge arm. The first bridge arm comprises a plurality of series-connected first main switches. Each of the plurality of series-connected first main switches is coupled in parallel with a first auxiliary module. Each first auxiliary module comprises a first clamping capacitor and a first auxiliary switch. The second bridge arm comprises at least a second main switch. The first bridge arm is configured to receive a first main switch signal to control the plurality of first main switches and the second bridge arm is configured to receive a second main switch signal to control the at least a second main switch. A working cycle of the bridge circuit comprises a first dead time, during the first dead time, the plurality of series-connected first main switches and the at least a second main switch are off.

At step S 31 , sensing voltages of the clamping capacitors and correspondingly generating voltage sensing signals.

At step S 32 , sorting the voltage sensing signals according to the sensing voltage value and getting the sorting result.

At step S 33 , turning on at least one auxiliary switch for a predetermined time during the first dead time according to the sorting result, wherein the predetermined time is equal to or less than the first dead time.

In an embodiment of the present invention, when certain first voltage sensing signals rank at top M among the first voltage sensing signals, the auxiliary switches corresponding to the certain voltage sensing signal are controlled to turn on, while the other auxiliary switches are controlled to turn off, wherein M is a natural number greater than or equal to one. In an embodiment of the present invention, at least one of the first auxiliary switches turns on, and discharges the first clamping capacitor corresponding to the first auxiliary switch in the first dead time by the freewheeling current. I.e., turning on the first auxiliary switches corresponding to certain first voltage sensing signals ranking on top M among the first voltage sensing signals for the predetermined time, wherein M is a natural number greater than or equal to one.

In an embodiment of the present invention, the common node is configured to output an output current and an output voltage. During a working cycle, when the output current lags behind the output voltage, the first dead time is the dead time before the rising edge of the first main switch signal, and the second dead time is the dead time before the rising edge of the second main switch signal. When the output current leads the output voltage, the first dead time is the dead time before the rising edge of the second main switch signal, and the second dead time is the dead time before the rising edge of the first main switch signal.

FIG. 7 schematically illustrates a circuit diagram of a bridge circuit with series-connected switches (i.e. an LLC resonant circuit) coupled in a resonant circuit in accordance with an embodiment of the present invention. The LLC resonant circuit comprises a bridge circuit 80 , a resonant network 90 , a transformer 91 , a rectifier 92 and an output capacitor 93 . The bridge circuit 80 comprises two bridge arm capacitors Ci and a half bridge circuit with series-connected switches as shown in FIG. 1 . The half bridge circuit comprises a first bridge arm 10 and a second bridge arm 20 . The midpoints M 1 and M 2 of the two bridge arms of the bridge circuit 80 are coupled to the primary side of the transformer 91 via the resonant network 90 . The resonant network 90 comprises an inductor Lr and a capacitor Cr. The rectifier 40 and the output capacitor 50 are located on the secondary side of the transformer 30 . The rectifier can be a full-bridge rectifier circuit, a half-bridge rectifier circuit or a voltage-doubling rectifier circuit. Vi and Vo are the input voltage and the output voltage of the LLC resonant circuit, respectively. In the embodiment shown in FIG. 7 , to simplify the description, each main switch and its parallel auxiliary module are defined as a submodule. That is, the first bridge arm 10 comprises submodules SM 11 ˜SM 1 N connected in series and the second bridge arm 20 comprises submodules SM 21 ˜SM 2 N connected in series. Each submodule SM 1 i and SM 2 i comprises a main switch S, an auxiliary diode Da, an auxiliary switch Sa, and a clamping capacitor C. Each main switch S is coupled in parallel with an auxiliary module, each auxiliary module comprises a clamping capacitor C and an auxiliary switch Sa. The auxiliary switch Sa is coupled in anti-parallel with the auxiliary diode Da. The two output ports of each submodule are the drain/source (or collector/emitter) of the main switch S. The submodule has the following characteristics: when the auxiliary switching Sa turns off, the clamping capacitor C can only be charged via the auxiliary diode Da; when the auxiliary switch turns on, the clamping capacitor can be discharged or charged. To simplify the description, the components in each submodule are not numbered differently. However, in an actual embodiment of the present invention, the structure of the first bridge arm 10 shown in FIG. 7 and the label of each components are the same as the first bridge arm 10 shown in FIG. 2 ( a ) , and the structure of the second bridge arm 20 shown in FIG. 7 and the label of each components are the same as the second bridge arm 20 shown in FIG. 2 ( b ) . In the embodiment shown in FIG. 7 , in each submodule SM 1 i and SM 2 i , when the main switch S turns off, once the voltage across S exceeds that of the clamping capacitor C, the auxiliary diode Da will conduct. Since the capacitance of the clamp capacitor C is much larger than the parasitic capacitance of the main switch S, the voltage of the main switch S is clamped to the voltage of the capacitor C. Therefore, the voltages can be shared evenly among the series-connected main switches if the voltages of the clamping capacitors are well-balanced.

FIG. 8 illustrates working waveforms of the bridge circuit with series-connected switches coupled in the resonant circuit in accordance with an embodiment of the present invention. Wherein Vi is the input voltage of the LLC resonant circuit, v 10 and v 20 are the bridge arm voltage of the first bridge arm 10 and the second bridge arm 20 , respectively, it is the resonant current, Ts is the switching cycle of each main switch, td is the dead time between the first main switch signal g and the second main switch signal g′. In the embodiment shown in FIG. 8 , the first dead time is the dead time before the rising edge of the first main switch signal g, and the second dead time is the dead time before the rising edge of the second main switch signal g′. ga,on and g′a,on are the pulse gate signals of the auxiliary switch in the first bridge arm 10 and the second bridge arm 20 , respectively. In each switching cycle, the pulse signals ga,on and g′a,on maintain a high level for a predetermined time and remains low for the rest of the time during the first dead time and the second time, respectively. In an embodiment shown in FIG. 8 , the pulse gate signal ga,on (g′a,on) are assigned to one auxiliary switch in the first (second) bridge arm respectively, and the gate signals of other auxiliary switches are off signals (that is, low level); in other embodiments of the present invention, the pulse signal ga, on (g′a, on) can also be assigned to two or more than two auxiliary switches in the first (second) bridge arm, and the gate signals of other auxiliary switches are off signals (that is, low level). The high level duration of pulse gate signal ga,on and g′a,on is ta and t′a, respectively. In the embodiment in FIG. 8 , ta=t′a, and ta<td, where the values of ta and t′a can be adjusted according to circuit parameters and the dead time td can be set according to practical needs. In other embodiment of the present invention, ta is equal or unequal to t′a. In one embodiment of the present invention, the dead time td should ensure the main switch realize zero voltage switching-on.

In the embodiment shown in FIG. 8 , t 1 represents the start moment of a switching cycle, at which moment the first main switch signal g steps from low level to high level. t 2 represents the start moment of the second dead time in this switching cycle, at which moment the first main switch signal g steps from high level to low level and the pulse gate signal g′a,on steps from low level to high level. t 3 represents the moment when the pulse gate signal g′a,on steps from high level to low level. t 4 represents the end moment of the second dead time in this switching period, at which moment the second main switch signal g′ steps from low level to high level. In other embodiment of the present invention, the rising edge of the pulse gate signal g′a,on is not limited in the second dead time, and can be ahead of the falling edge of the first main switch signal g. t 5 represents the start moment of the first dead time in this switching period, at which moment the second main switch signal g′ steps from high level to low level and the pulse gate signal ga,on steps from low level to high level. t 6 represents the moment when the pulse gate signal ga,on steps from high level to low level. In other embodiment of the present invention, the rising edge of the pulse gate signal ga,on is not limited in the first dead time, and can be ahead of the falling edge of the second main switch signal g′. t 7 represents the end moment of this switching period, at which moment the first main switch signal g steps from low level to high level. In the switching cycle from t 1 to t 7 , the submodule which obtains the pulse gate signal ga,on in the first bridge arm 10 is SM 1 j , and vc 1 j represents the voltage of the clamping capacitor in the submodule SM 1 j , while the submodule which obtains the pulse gate signal g′a,on in the second bridge arm 20 is SM 2 k , and vc 2 k represents the voltage of the clamping capacitor in the submodule SM 2 k , wherein j and k can represent any natural number from 1 to N. In the waveforms shown in FIG. 8 , the clamping capacitor voltages (vc 1 j and vc 2 k ) are amplified to show the operating characteristics of the circuit in the embodiment. In actual working conditions, the voltage fluctuation of the clamp capacitor is affected by the capacitance of the clamping capacitor C.

FIG. 9 is a circuit modal diagram of the second bridge arm 20 during the second dead time in the waveforms shown in FIG. 8 in accordance with an embodiment of the present invention. FIG. 9 ( a ) is a circuit modal diagram of the second bridge arm 20 during the period when the pulse gate signal g′a,on maintains a high level during the second dead time, corresponding to t 2 ˜t 3 in a second dead time (t 2 ˜t 4 ); wherein from t 2 to t 3 , when the main switch S in the first bridge arm 10 turns off, its parasitic capacitor is charged quickly, and the parasitic capacitor of the main switch S in the second bridge arm 20 is discharged. Because the auxiliary switch Sa in the submodule SM 2 k in the second bridge arm 20 turns on, the clamping capacitor C in the submodule SM 2 k is in parallel with the parasitic capacitor of the corresponding main switch S, which are discharged at the same time until the auxiliary switch Sa in the submodule SM 2 k turns off. Since the capacitance of the clamping capacitor C is much larger than the parasitic capacitance of the main switch S, the freewheeling current of the bridge arm mainly flows through the clamping capacitor C, while the voltages of parasitic capacitors of the remaining submodules are quickly discharged to 0. The freewheeling current of the bridge arm is transferred to the anti-parallel diode of the corresponding main switch S to ensure zero voltage switch-on of the corresponding main switch S. Since the clamping capacitor in the submodule SM 2 k is inserted into the second bridge arm 20 and the parasitic capacitors voltages of the main switches S in the remaining submodules are discharged to 0, the voltage v 20 of the second bridge arm 20 is equal to the clamping capacitor voltage vc 2 k (ignoring the conduction voltage drop of anti-parallel diode of the main switch S and the auxiliary switch Sa in each submodule), while the voltage v 10 of the first bridge arm 10 is equal to the difference between the input voltage Vi and vc 2 k.

FIG. 9 ( b ) is a circuit modal diagram of the second bridge arm 20 during the period when the pulse gate signal g′a,on maintains a low level during the second dead time, corresponding to t 3 ˜t 4 in a second dead time (t 2 ˜t 4 ); wherein from t 3 to t 4 , the auxiliary switch Sa in the submodule SM 2 k turns off, and the parasitic capacitor of the main switch S in the submodule SM 2 k is discharged by the freewheeling current of the bridge arm. By designing the duration of this stage (td-ta) reasonably, the parasitic capacitor of the main switch S in the submodule SM 2 k will be discharged to 0 at the end of this stage, realizing zero voltage switch-on of the main switch S. When the parasitic capacitor of the main switch S in the submodule SM 2 k is discharged, the parasitic capacitor of the main switch S in the first bridge arm 10 continues to be charged to maintain the sum of the voltage v 10 and the voltage v 20 equal to the input voltage Vi. When the voltage of the parasitic capacitor in any submodule in the first bridge arm 10 is higher than the voltage of its corresponding clamping capacitor C, the auxiliary diode Da in the corresponding submodule conducts and the clamping capacitor C is charged until the arm current of the first bridge arm 10 drops to zero.

FIG. 10 is a circuit modal diagram of the first bridge arm 10 during the first dead time in the waveforms shown in FIG. 8 in accordance with an embodiment of the present invention. FIG. 10 ( a ) is a circuit modal diagram of the first bridge arm 10 during the period when the pulse gate signal ga,on maintains a high level in the first dead time, corresponding to t 5 ˜t 6 in the first dead time (t 5 ˜t 7 ); wherein from t 5 to t 6 , when the main switch S in the second bridge arm 20 turns off, its parasitic capacitor is charged quickly, and the parasitic capacitor of the main switch S in the first bridge arm 10 is discharged. Because the auxiliary switch Sa in the submodule SM 1 j in the first bridge arm 10 turns on, the clamping capacitor C in the submodule SM 1 j is in parallel with the parasitic capacitance of the corresponding main switch S, which are discharged at the same time until the auxiliary switch Sa in the submodule SM 1 j turns off. Since the capacitance of the clamping capacitor C is much larger than the parasitic capacitance of the main switch S, the freewheeling current of the bridge arm mainly flows through the clamping capacitor C, while the voltages of parasitic capacitors in the remaining submodules of the first bridge 10 are quickly discharged to 0. The freewheeling current of the bridge arm is transferred to the anti-parallel diode of the corresponding main switch S to ensure zero voltage switch-on of the corresponding main switch S. Since the clamping capacitor in the submodule SM 1 j is inserted into the first bridge arm 10 , and the parasitic capacitors of the main switches S in the remaining submodules are discharged to 0, the voltage v 20 of the first bridge arm 10 is equal to the clamping capacitor voltage vc 1 j (ignoring the conduction voltage drop of anti-parallel diode of the main switch S and the auxiliary switch Sa in each submodule), while the voltage v 20 of the second bridge arm 20 is equal to the difference between the input voltage Vi and vc 1 j.

FIG. 10 ( b ) is a circuit modal diagram of the first bridge arm 10 during the period when the pulse gate signal ga,on maintains a low level during the first dead time, corresponding to t 6 ˜t 7 in the first dead time (t 5 ˜t 7 ); wherein from t 6 to t 7 , the auxiliary switch Sa in the submodule SM 1 j turns off, and the parasitic capacitor of the main switch S in the submodule SM 1 j is discharged by the freewheeling current of the bridge arm. By designing the duration of this stage (td-ta) reasonably, the parasitic capacitor of the main switch S in the submodule SM 1 j will be discharged to 0 at the end of this stage, realizing zero voltage switch-on of the main switch S. When the parasitic capacitor of the main switch S in the submodule SM 1 j is discharged, the parasitic capacitor of the main switch S in the second bridge arm 20 continues to be charged to maintain the sum of the voltage v 10 and the voltage v 20 equal to the input voltage Vi. When the voltage of the parasitic capacitor in any submodule in the second bridge arm 20 is higher than the voltage of its corresponding clamping capacitor C, the auxiliary diode Da in the corresponding submodule conducts and the clamping capacitor C is charged until the arm current of the second bridge arm 20 drops to zero.

FIG. 11 illustrates working waveforms of the clamping capacitors voltage when the LLC resonant circuit is in steady state in accordance with an embodiment of the present invention. In the steady-state waveform shown in FIG. 11 , at the end of a switching period (0-Ts), the clamping capacitor voltage vc 12 in the sub-module SM 12 is the highest in the first bridge arm 10 . In the next switching period (Ts˜2Ts), during the dead time before the main switch in the first bridge arm 10 turns on, the auxiliary switch Sa in the auxiliary module SM 12 turns on for a predetermined time ta and its corresponding clamping capacitor C is discharged. As a result, the clamping capacitor voltage vc 12 decreases, while the voltages of other clamping capacitors in the first bridge arm 10 remain unchanged. If ta is set properly, at the end of this discharge process, there will be:

v c11 +v c12 +v c13 +v c14 <V i

During the dead time after the main switch in the first bridge arm 10 turns off, the voltage v 10 of the first bridge arm 10 rises gradually and will eventually be equal to the input voltage Vi, but the sum of the clamping capacitor voltages in the first bridge arm 10 is less than the input voltage Vi. As a result, during the dead time after the main switch in the first bridge arm 10 turns off, there is a charging process for all the clamping capacitors C in the first bridge arm 10 . Then, when the entire switching cycle Ts˜2Ts ends, the original highest clamping capacitor voltage vc 12 in the first bridge arm 10 decreases, while the original lower clamping capacitor voltages vc 11 , vc 13 , and vc 14 increase, which means the imbalance among AM capacitor voltages is compensated. Using the voltage balance control method described in FIG. 11 , a similar compensation also exists in the second bridge arm 20 and continues in every switching cycle, finally achieving that the clamping capacitor voltages in each bridge arm dynamically balanced around Vi/4. The voltage fluctuation of the clamping capacitor is affected by the number of sub-modules N in each bridge arm and the pulse duration ta of the auxiliary switch Sa. The dashed box in FIG. 11 shows the waveforms of the clamping capacitor voltages vc 11 ˜vc 1 N and vc 21 ˜vc 2 N during the dead time in detail, which is consistent with the working principle discussed in FIG. 8 .

FIG. 12 schematically illustrates a circuit diagram of a bridge circuit with series-connected switches coupled in an inverter circuit in accordance with an embodiment of the present invention. The inverter circuit comprises a bridge circuit 80 and a filter inductor 150 or filter 151 . The bridge circuit 80 comprises two bridge arm capacitors Ci and a half bridge circuit with series-connected switches as shown in FIG. 1 . The half bridge circuit comprises a first bridge arm 10 and a second bridge arm 20 . The midpoints M 1 and M 2 of the two bridge arms of the bridge circuit 80 are coupled to the load via the filter inductor 150 or the filter 151 . The load can be an ac source such as a power grid, a motor, or a heating device. The low-pass filter 151 comprises a filter inductor Lf and a filter capacitor Cf. Vi and Vo are the input voltage and the output voltage of the inverter circuit, respectively. In the embodiment shown in FIG. 12 , to simplify the description, each main switch and its parallel auxiliary module are defined as a submodule, that is, the first bridge arm 10 comprises submodules SM 11 ˜SM 1 N connected in series and the second bridge arm 20 comprises submodules SM 21 ˜SM 2 N connected in series. Each submodule SM 1 i and SM 2 i comprises a main switch S, an auxiliary diode Da, an auxiliary switch Sa, and a clamping capacitor C. Each main switch S is coupled in parallel with an auxiliary module, each auxiliary module comprises a clamping capacitor C and an auxiliary switch Sa. The auxiliary switch Sa is coupled in anti-parallel with the auxiliary diode Da. The two output ports of each submodule are the drain/source (or collector/emitter) of the main switch S. iarm is the bridge arm current, and the direction shown in FIG. 12 is positive. The submodule has the following characteristics: when the auxiliary switching Sa turns off, the clamping capacitor C can only be charged via the auxiliary diode Da and cannot be discharged; only when the auxiliary switching turns on and the bridge arm current iarm<0, the clamping capacitor can be discharged. To simplify the description, the components in each submodule are not numbered differently. However, in an actual embodiment of the present invention, the structure of the first bridge arm 10 shown in FIG. 12 and the label of each component are the same as the first bridge arm 10 and the second bridge arm 20 shown in FIG. 2 ( a ) and FIG. 2 ( b ) , respectively.

FIG. 13 illustrates working waveforms of the bridge circuit with series-connected switches coupled in the inverter circuit in two output ac cycles in accordance with an embodiment of the present invention. Wherein Vi is the input voltage of the inverter circuit, v 10 and v 20 are the bridge arm voltage of the first bridge arm 10 and the second bridge arm 20 , respectively, iL is the current of the filter inductor, io is the output ac current, To is the period of the output ac current, iarm 1 is the current flowing through the first bridge arm, vc 1 and vc 2 are the voltages of the clamping capacitors C of the submodules SM 11 ˜SM 1 N in the first bridge arm 10 and the submodules SM 21 ˜SM 2 N in the second bridge arm 20 , respectively. The first main switch signal g and the second main switch signal g′ adopt bipolar SPWM modulation (the modulation frequency is much larger than the output ac frequency). In order to avoid punch-through of the first bridge arm 10 and the second bridge arm 20 , there is a dead time td between the first main switch signal g and the second main switch signal g′. The definition of the first dead time, the second dead time, the pulse gate signal ga,on and g′a,on of the auxiliary switch in the first bridge arm 10 and the second bridge arm 20 are the same as that of the LLC resonant circuit shown in FIG. 8 . Based on the charging and discharging state of the clamping capacitors C of the submodules SM 11 ˜SM 1 N in the first bridge arm 10 , an output ac cycle is divided into 3 stages: Charge Stage t 0 ˜t 1 , Discharge Stage t 1 ˜t 2 and Steady Voltage Stage t 2 ˜t 3 . The charging and discharging state of the clamping capacitors C of the submodules SM 21 ˜SM 2 N in the second bridge arm 20 are similar to that of the first bridge arm 10 , which is also divided into three stages, and not repeated here. In actual working conditions, the voltage fluctuation of the clamp capacitor is affected by the capacitance of the clamping capacitor C.

FIG. 14 ( a ) is a circuit modal diagram of the first bridge arm 10 in the Charge Stage in the waveforms shown in FIG. 13 according to an embodiment of the present invention, in which period iarm 1 >0. FIG. 14 ( a ) is a circuit modal diagram of the first bridge arm 10 during the period when the pulse gate signal g′a,on maintains a high level with in the second dead time, corresponding to t 2 ˜t 3 in the second dead time (t 2 ˜t 4 ) shown in FIG. 8 ; wherein from t 2 to t 3 , iarm 1 >0, iL>0. When the main switch S in the first bridge arm 10 turns off, due to the inevitable parasitic inductances Larm 1 and Larm 2 of the first bridge arm 10 and the second bridge arm 20 , the filter inductor current iL cannot be transferred from the first bridge arm 10 to the second bridge arm 20 immediately and the parasitic capacitor of the main switch S in the first bridge arm 10 is charged quickly by the freewheeling current of the parasitic inductance Larm 1 of the first bridge arm 10 . Since the capacitance of the clamping capacitor C is much larger than the parasitic capacitance of the main switch S, the current iarm 1 of the first bridge arm 10 continues to charge the clamping capacitor C until iarm 1 drops to zero. Thus, the voltages of the clamping capacitors C of all submodules SM 11 ˜SM 1 N in the first bridge arm 10 keep rising in the Charge Stage. After several switching cycles, when iarm 1 <0, the clamping capacitors C of the submodules SM 11 ˜SM 1 N in the first bridge arm 10 can be discharged and the inverter circuit enters the Discharge Stage.

FIG. 14 ( b ) is a circuit modal diagram of the first bridge arm 10 in the Discharge Stage in the waveforms shown in FIG. 13 according to an embodiment of the present invention, in which period iarm 1 <0. FIG. 14 ( b ) is a circuit modal diagram of the first bridge arm 10 during the period when the pulse gate signal ga,on maintains a high level during the first dead time, corresponding to t 5 ˜t 6 in the first dead time (t 5 ˜t 7 ) shown in FIG. 8 ; wherein from t 5 to t 6 , since iarm 1 <0 and the main switch S in the second bridge arm 20 is off, its parasitic capacitor charges quickly, while the parasitic capacitor of the main switch in the first bridge arm 10 discharges. Because the auxiliary switch Sa in the submodule SM 1 j in the first bridge arm 10 turns on, the clamping capacitor C in the submodule SM 1 j is coupled in parallel with the parasitic capacitor of the corresponding main switch S, which are discharged at the same time until the auxiliary switch Sa in the submodule SM 1 j turns off. Since the capacitance of the clamping capacitor C is much larger than the parasitic capacitance of the main switch S, the freewheeling current of the bridge arm mainly flows through the clamping capacitor C, while the voltages of parasitic capacitors in the remaining submodules of the first bridge 10 are quickly discharged to 0. The freewheeling current transfers to the anti-parallel diode of the corresponding main switch S to ensure the zero voltage switching-on of the corresponding main switch S. Since the clamping capacitor in the submodule SM 1 j is inserted into the first bridge arm 10 , and the parasitic capacitors of the main switches S in the remaining submodules are discharged to 0, the voltage v 10 of the first bridge arm 10 is equal to the clamping capacitor voltage vc 1 j (ignoring the conduction voltage drop of anti-parallel diode of the main switch S and the auxiliary switch Sa in each submodule), while the voltage v 20 of the second bridge arm 20 is equal to the difference between the input voltage Vi and vc 1 j . This Discharge Stage ends until the voltage of each clamping capacitor in the bridge arm 10 drops to around Vi/4.

FIG. 15 illustrates working waveforms of the inverter circuit with series-connected switches in the Steady Voltage Stage shown in FIG. 13 in accordance with an embodiment of the present invention, in which period iarm 1 <0. From t 1 to t 2 , since iarm 1 <0 and the main switch S of the second bridge arm 20 is off, its parasitic capacitor charges quickly, while the parasitic capacitor of the main switch in the first bridge arm 10 discharges, the circuit modal diagram of the first bridge arm 10 during which period is the same as that in FIG. 14 ( b ) . When t 1 <t<t 2 , the auxiliary switch Sa in the submodule SM 1 j in the first bridge arm 10 turns on, so the clamping capacitor C in the submodule SM 1 j is coupled in parallel with the parasitic capacitor of the main switch S, which are discharged at the same time. When the auxiliary switch Sa in the submodule SM 1 j turns off, there is

v c11 +v c12 +v c13 +v c14 <V i .

Then, when the main switch S in the second bridge arm 20 turns on, the clamping capacitor C of the submodule SM 11 ˜SM 1 N in the first bridge arm 10 is coupled in parallel with the parasitic capacitor of the corresponding main switch S, which are charged at the same time by dc voltage source, till

v c11 +v c12 +v c13 +v 14 =V i .

The circuit modal diagram of the first bridge arm 10 in this period is the same as that in FIG. 14 ( a ) . The above process continues in each switching cycle. Therefore, in the Steady Voltage Stage, the clamping capacitor voltage in the first bridge arm 10 is dynamically balanced at Vi/4.

FIG. 16 illustrates working waveforms of the clamping capacitors voltage of the first bridge arm 10 and the second bridge arm 20 when the inverter circuit is in steady state (taking 4 series-connected switches as an example) in accordance with an embodiment of the present invention.

In the steady state waveforms shown in FIG. 16 , from t 0 to t 1 , the first bridge arm 10 is in Charge stage (iL>0, iarm 1 >0, iarm2<0). In the dead time after the main switch in the first bridge arm 10 turns off, the clamping capacitor of the submodules SM 11 ˜SM 1 N is charged by the freewheeling current of the parasitic inductor Larm 1 of the first bridge arm 10 . After several switching cycles, the clamping capacitor voltage of the first bridge arm 10 reaches peak value at the end of the Charge Stage. The second bridge arm 20 is in the Discharge Stage. The auxiliary switch Sa in the auxiliary modules SM 21 ˜SM 2 N of the second bridge arm 20 turns on for a predetermined time to alternatively. Since iarm 2 <0, the corresponding clamping capacitors C discharge in turn. After several switching cycles, when the clamping capacitor voltages satisfy v c21 +v c22 +v c23 +v c24 −V i , the second bridge arm 20 enters the Steady Voltage Stage. From t 1 to t 2 , the first bridge arm 10 is in the Discharge stage (iL<0, iarm 1 <0, iarm 2 >0). The auxiliary switch Sa in the auxiliary modules SM 11 ˜SM 1 N of the first bridge arm 10 turns on for a predetermined time ta alternatively. Since iarm 2 <0, the corresponding clamping capacitors C discharge in turn. The second bridge arm 20 is in the Charge Stage. The duration of the Discharge Stage is affected by the number of submodules inserted into the dead time in each bridge arm and the predetermined time ta of the auxiliary switch Sa. If ta is set properly, after several switching cycles, at the end of the Discharge Stage, there will be v c11 +v c12 +v c13 +v c14 <V i . Then, the first bridge arm 10 enters the Steady Voltage Stage naturally, and the clamping capacitor voltages vc 11 ˜vc 1 N of the first bridge arm 10 are dynamically balanced at Vi/4. In general, in an output ac cycle To, the first bridge arm 10 goes through the Steady Voltage Stage, the Charge Stage, and the Discharge Stage, and then returns back to the Steady Voltage Stage, realizing the voltage balance of the clamping capacitors C in the first bridge arm 10 . Using this voltage balance control method, a similar process also exists in the second bridge arm 20 , finally achieving the clamping capacitor voltages in each bridge arm periodically balanced.

FIG. 17 is a flow chart 4000 of a control method of a bridge circuit with series-connected switches coupled in a resonant circuit in accordance with an embodiment of the present invention. The resonant circuit has a bridge circuit with series-connected switches, a resonant network, a transformer and a rectifier circuit, wherein the bridge circuit comprises a first bridge arm and a second bridge arm coupled to a common node, the first bridge arm comprising a plurality of series-connected first main switches, wherein each of the plurality of series-connected first main switch is coupled in parallel with an auxiliary module, each auxiliary module comprises a clamping capacitor and an auxiliary switch, the second bridge arm comprising at least a second main switch, the first bridge arm configured to receive a first main switch signal to control the plurality of series-connected first main switches, the second bridge arm configured to receive a second main switch signal to control the at least a second main switch, a switching cycle of the resonant circuit comprises a first time period, the first dead time, a second time period and a second dead time, and the control method comprises steps S 41 ˜S 44 :

At step S 41 , during the first time period, controlling the plurality of series-connected first main switches off, the at least a second main switch on and the auxiliary switches off.

At step S 42 , during the first dead time, controlling the plurality of series-connected first main switches and the at least a second main switch off, controlling the at least one auxiliary switch on for the predetermined time, and discharging the clamping capacitor corresponding to the at least one auxiliary switch.

At step S 43 , during the second time period, controlling the plurality of series-connected first main switches on, controlling the at least a second main switch off, controlling the auxiliary switches off, and controlling the resonant circuit working in a normal resonant state.

At step S 44 , during the second dead time, controlling the plurality of series-connected first main switches, the at least a second main switch and the auxiliary switches off.

For the control method of the LLC resonant circuit shown in FIG. 17 , the control method further comprises:

A control circuit is used to sort the voltages of all the clamping capacitors, and control the auxiliary switch corresponding to the one or more clamping capacitors with the highest voltage on for a predetermined time.

In one embodiment of the present invention, the first time period is the time during which the first main switch signal maintains a low level and the second main switch signal maintains a high level, corresponding to t 4 ˜t 5 in the working waveforms of the LLC resonant circuit shown in FIG. 8 . The first dead time is the period when the first main switch signal maintains a low level and after the second main switch signal steps from a high level to a low level, corresponding to t 5 ˜t 7 in the working waveforms of the LLC resonant circuit shown in FIG. 8 . The second time period is the time when the second main switch signal maintains a low level and after the first main switch signal steps from a low level to a high level, corresponding to t 1 ˜t 2 in the working waveforms of the LLC resonant circuit shown in FIG. 8 . The second dead time is the period when the first main switch signal maintains a low level and after the second main switch signal steps from a high level to a low level, corresponding to t 2 ˜t 4 in the working waveforms of the LLC resonant circuit shown in FIG. 8 .

In other embodiments of the present invention, the second bridge arm may comprise a plurality of series-connected second main switches, wherein each of the plurality of series-connected second main switch is coupled in parallel with an auxiliary module, and each auxiliary module comprises a clamping capacitor and an auxiliary switch. In this case, the plurality of first main switches and the plurality of second main switches are controlled to turn off during the second dead time, while at least one auxiliary switch of the auxiliary module in the second bridge arm is controlled to keep on for a predetermined time and at least one clamping capacitor in the auxiliary module in the second bridge arm is discharged by the freewheeling current, wherein the predetermined time is less than or equal to the second dead time.

In one embodiment of the present invention, the method further comprises controlling the plurality of first main switches and the at least a second main switch off during the first dead time of a working cycle of the bridge circuit.

FIG. 18 is a flow chart 5000 of a control method of a bridge circuit with series-connected switches coupled in an inverter circuit in accordance with an embodiment of the present invention. The inverter circuit has a bridge circuit with series-connected switches and a filter, the bridge circuit comprising a first bridge arm and a second bridge arm coupled to a common node, the first bridge arm comprising a plurality of series-connected first main switches, wherein each of the plurality of series-connected first main switch is coupled in parallel with an auxiliary module, each auxiliary module comprises a clamping capacitor and an auxiliary switch, the second bridge arm comprising at least a second main switch, the first bridge arm configured to receive a first main switch signal to control the plurality of series-connected first main switches, the second bridge arm configured to receive a second main switch signal to control the at least a second main switch. An output ac cycle of the inverter circuit comprises a charge stage and a discharge stage, wherein the output ac cycle comprises several switching cycles, and the switching cycle comprises a first time period, the first dead time, a second time period and a second dead time. The control method comprises steps S 51 ˜S 54 :

At step S 51 , during the first time period, controlling the plurality of series-connected first main switches off, the at least a second main switch on and the auxiliary switches off.

At step S 52 , during the first dead time, controlling the plurality of series-connected first main switches and the at least a second main switch off, wherein during the discharge stage, controlling at least one auxiliary switch of the auxiliary module in the first bridge arm on for the predetermined time and discharging the clamping capacitor corresponding to the at least one auxiliary switch.

At step S 53 , during the second time period, controlling the plurality of series-connected first main switches on, the at least a second main switch off, and the auxiliary switches off, and controlling the inverter circuit working in a normal inverter state.

At step S 54 , during the second dead time, controlling the plurality of series-connected first main switches, the at least a second main switch and the auxiliary switches off.

For the control method of the inverter circuit, the control method further comprises:

During the second dead time, controlling the plurality of series-connected first main switches and the at least a second main switch off, wherein during the discharge stage, controlling at least one auxiliary switch of the auxiliary module in the first bridge arm on for the predetermined time and discharging the clamping capacitor corresponding to the at least one auxiliary switch.

For the control method of the inverter circuit shown in FIG. 18 , the control method further comprises:

A control circuit is used to sort the voltages of all the clamping capacitors, and control the auxiliary switch corresponding to the one or more clamping capacitors with the highest voltage on for a predetermined time.

In one embodiment of the present invention, the definitions of the first time period, the second time period, the first dead time and the second dead time in the one switching cycle are consistent with the LLC resonant circuit. The Charge Stage of one output cycle is the period when iarm 1 is always positive, corresponding to t 0 ˜t 1 in the waveforms of the inverter circuit shown in FIG. 13 . The Discharge Stage starts from the moment when iarm 1 is negative and ends when the clamping capacitor voltage in the first bridge arm discharges to around Vi/4 (taking 4 submodules as an example), corresponding to t 1 ˜t 2 in the waveforms of the inverter circuit shown in FIG. 13 . The Steady Voltage Stage starts from the end of the Discharge Stage till iarm 1 is always positive, that is, the Charge Stage of the next output ac cycle, corresponding to t 2 ˜t 3 in the waveforms of the inverter circuit shown in FIG. 13 . Note that the duration of the Discharge Stage is affected by the number of submodules inserted into the dead time in each bridge arm and the predetermined time ta of the auxiliary switch Sa. When the predetermined time ta is short and the number of the inserted submodules is small, the discharge speed of the clamp capacitor is slow and the duration of the Discharge Stage is long. In the critical state, the end of the Discharge Stage is just the beginning of Charge Stage in the next switching cycle and hence there is no Steady Voltage Stage but only Charge and Discharge Stage, while in general cases, there are Charge, Discharge, and Steady Voltage Stage.

In other embodiments of the present invention, the second bridge arm may comprise a plurality of series-connected second main switches, wherein each of the plurality of series-connected second main switch is coupled in parallel with an auxiliary module, and each auxiliary module comprises a clamping capacitor and an auxiliary switch. In this case, the plurality of first main switches and the plurality of second main switches are controlled to turn off during the second dead time, while at least one auxiliary switch of the auxiliary module in the second bridge arm is controlled to keep on for a predetermined time and at least one clamping capacitor in the auxiliary module in the second bridge arm is discharged by the freewheeling current, wherein the predetermined time is less than or equal to the second dead time.

Obviously, many modifications and variations of the present invention are possible in light of the above teachings. It is therefore to be understood that within the scope of the appended claims the invention may be practiced otherwise than as specifically described. It should be understood, of course, the foregoing disclosure relates only to a preferred embodiment (or embodiments) of the invention and that numerous modifications may be made therein without departing from the spirit and the scope of the invention as set forth in the appended claims. Various modifications are contemplated and they obviously will be resorted to by those skilled in the art without departing from the spirit and the scope of the invention as hereinafter defined by the appended claims as only a preferred embodiment(s) thereof has been disclosed.