Isolated converter with high boost ratio

This patent application is a continuing application of U.S. patent application Ser. No. 16/867,242 filed on May 5, 2020, and entitled “ISOLATED CONVERTER WITH HIGH BOOST RATIO,” which claims the benefit of United States Provisional Patent Application No. 62/860,650 filed Jun. 12, 2019, and claims priority of CN202010248753.X filed Apr. 1, 2020. The entire disclosures of the above applications are all incorporated herein by reference.

The present disclosure relates to an isolated converter, and more particularly to an isolated converter with high boost ratio.

The statements in this section merely provide background information related to the present disclosure and do not necessarily constitute prior art.

Please refer to FIG. 1 , which shows a circuit block diagram of a conventional non-isolated boost converter. If a high voltage conversion ratio (boost ratio) is required, for example more than 10 times, two or more than two boost (DC-to-DC) converters are used to implement the requirement of high boost ratio. As shown in FIG. 1 , a first DC boost converter and a second DC boost converter are used. However, disadvantages of the multi-stage boost converters are higher circuit component costs and lower conversion efficiency.

Please refer to FIG. 2 , which shows a circuit diagram of a conventional push-pull converter. The push-pull converter has an advantage of electrical isolation by an isolated transformer. By adjusting the number of coil turns of the isolated transformer, the high boost ratio (voltage conversion ratio) of the push-pull converter can be implemented. If the voltage conversion ratio is too high, however, excessive number of the secondary-side coil turns causes an increase in the leakage inductance of the isolated transformer, resulting in higher stress on the switch and/or the diode, and therefore the components with higher rated voltage need to be used. Further, the turned-on resistance of the switch becomes larger cause increased circuit costs, reduced efficiency, and larger transformer volume.

Please refer to FIG. 3 , which shows a circuit diagram of a conventional full-bridge LLC resonant converter. The switches of the LLC resonant converter can operate under ZVS (zero voltage switching) condition, and usually the switching frequency is designed near the resonance point. By adjusting the number of coil turns of the isolated transformer, the high voltage conversion ratio of the LLC resonant converter can be implemented. If the voltage conversion ratio is too high, however, excessive number of the coil turns causes the increased coil turns of the transformer, increased volume of the transformer, and reduced efficiency. Moreover, the full-bridge LLC resonant converter shown in FIG. 3 provides the first- and third-quadrant operations of the transformers. The quadrant here refers to the main operation area of the transformer in the B-H curve (hysteresis phenomenon is ignored).

Please refer to FIG. 4 , which shows a circuit diagram of a conventional full-bridge phase-shift converter. The switches of the full-bridge converter can operate under ZVS condition by phase control techniques. In comparison with the push-pull converter, the full-bridge converter has fewer switching losses. By adjusting the number of coil turns of the isolated transformer, the required output voltage of the full-bridge converter can be implemented. In order to implement the high boost ratio (voltage conversion ratio), however, the excessive number of the coil turns causes larger transformer volume, higher stress of the semiconductor switch, and lower conversion efficiency.

In the above several common isolated converters, the isolated transformer thereof operates in the first quadrant and the third quadrant. The present disclosure proposes an isolated converter with high boost ratio that can operate in the first quadrant and the third quadrant. The high boost ratio of the isolated converter can be implemented by charging capacitors to establish a high output voltage, thereby effectively reducing the number of coil turns of the isolated transformer. Accordingly, it is to increase efficiency of the boost circuit, reduce circuit component costs, and reduce occupied volume due to the reduction of the number of coil turns of the isolated transformer.

An object of the present disclosure is to provide an isolated converter with high boost ratio to solve the above-mentioned problems.

In order to achieve the above-mentioned object, the isolated converter with high boost ratio includes a transformer, a first bridge arm, a second bridge arm, and a boost circuit. The transformer includes a secondary side having a secondary side first node and a secondary side second node. The first bridge arm has a first diode and a second diode. A cathode of the first diode is coupled to a DC positive output node, an anode of the first diode is coupled to a first bridge arm upper node. An anode of the second diode is coupled to a DC negative output node, and a cathode of the second diode is coupled to a first bridge arm lower node. The second bridge arm has a third diode and a fourth diode. A cathode of the third diode is coupled to the DC positive output node, an anode of the third diode is coupled to a second bridge arm upper node. An anode of the fourth diode is coupled to the DC negative output node, and a cathode of the fourth diode is coupled to a second bridge arm lower node. The boost circuit includes at least one fifth diode, at least one sixth diode, and at least two capacitors. The at least one fifth diode is coupled between the first bridge arm and the secondary side second node. The at least one sixth diode is coupled between the second bridge arm and the secondary side first node. The at least two capacitors are coupled to the secondary side first node and the secondary side second node.

Accordingly, the isolated converter with high boost ratio is provided to increase efficiency of the boost circuit, reduce circuit component costs, and reduce occupied volume due to the reduction of the number of coil turns of the isolated transformer.

Another object of the present disclosure is to provide an isolated converter with high boost ratio to solve the above-mentioned problems.

In order to achieve the above-mentioned object, the isolated converter with high boost ratio includes a transformer, a first bridge arm, a second bridge arm, and a boost circuit. The transformer includes a secondary side having a secondary side first node and a secondary side second node. The first bridge arm has a first switch and a second switch. A first end of the first switch is coupled to a DC positive output node, a second end of the first switch is coupled to a first bridge arm upper node, a first end of the second switch is coupled to a DC negative output node, and a second end of the second switch is coupled to a first bridge arm lower node. The second bridge arm has a third switch and a fourth switch. A first end of the third switch is coupled to the DC positive output node, a second end of the third switch is coupled to a second bridge arm upper node, a first end of the fourth switch is coupled to the DC negative output node, and a second end of the fourth switch is coupled to a second bridge arm lower node. The boost circuit includes at least one fifth switch, at least one sixth switch, and at least two capacitors. The at least one fifth switch is coupled between the first bridge arm and the secondary side second node. The at least one sixth switch is coupled between the second bridge arm and the secondary side first node. The at least two capacitors are coupled to the secondary side first node and the secondary side second node.

Accordingly, the isolated converter with high boost ratio is provided to increase efficiency of the boost circuit, reduce circuit component costs, and reduce occupied volume due to the reduction of the number of coil turns of the isolated transformer.

It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the present disclosure as claimed. Other advantages and features of the present disclosure will be apparent from the following description, drawings and claims.

The present disclosure can be more fully understood by reading the following detailed description of the embodiment, with reference made to the accompanying drawing as follows:

FIG. 1 is a circuit block diagram of a conventional non-isolated boost converter.

FIG. 2 is a circuit diagram of a conventional push-pull converter.

FIG. 3 is a circuit diagram of a conventional full-bridge LLC resonant converter.

FIG. 4 is a circuit diagram of a conventional full-bridge phase-shift converter.

FIG. 5 is a single-bus circuit structure of an isolated converter with high boost ratio according to a first embodiment of the present disclosure.

FIG. 6 is a single-bus circuit structure of the isolated converter with high boost ratio according to a second embodiment of the present disclosure.

FIG. 7 is a schematic diagram of current paths of a first-quadrant operation in FIG. 5 .

FIG. 8 is a schematic diagram of current paths of a third-quadrant operation in FIG. 5 .

FIG. 9 is a single-bus circuit structure of the isolated converter with high boost ratio according to a third embodiment of the present disclosure.

FIG. 10 is a single-bus circuit structure of the isolated converter with high boost ratio according to a fourth embodiment of the present disclosure.

FIG. 11 is a dual-bus circuit structure of the isolated converter with high boost ratio according to the present disclosure.

FIG. 12 is a circuit diagram of a push-pull converter having the single-bus circuit structure in FIG. 5 .

FIG. 13 is a circuit diagram of a full-bridge converter having the single-bus circuit structure in FIG. 5 .

FIG. 14 is a circuit diagram of a full-bridge LLC resonant converter having the single-bus circuit structure in FIG. 5 .

FIG. 15 is a circuit diagram of a push-pull converter having the dual-bus circuit structure in FIG. 11 .

FIG. 16 is a circuit diagram of a full-bridge converter having the dual-bus circuit structure in FIG. 11 .

FIG. 17 is a circuit diagram of a full-bridge LLC resonant converter having the dual-bus circuit structure in FIG. 11 .

Reference will now be made to the drawing figures to describe the present disclosure in detail. It will be understood that the drawing figures and exemplified embodiments of present disclosure are not limited to the details thereof.

Please refer to FIG. 5 , which shows a single-bus circuit structure of an isolated converter with high boost ratio according to a first embodiment of the present disclosure. The isolated converter includes a transformer T 1 , a first bridge arm Lb 1 , a second bridge arm Lb 2 , and a boost circuit 10 . The transformer T 1 includes a secondary side having a secondary side first node Ps 1 and a secondary side second node Ps 2 . The first bridge arm Lb 1 includes a first diode D 1 and a second diode D 2 . A cathode of the first diode D 1 is coupled to a DC positive output node+Vb, an anode of the first diode D 1 is coupled to a first bridge arm upper node Pu 1 , an anode of the second diode D 2 is coupled to a DC negative output node −Vb, and a cathode of the second diode D 2 is coupled to a first bridge arm lower node Pw 1 . The second bridge arm Lb 2 includes a third diode D 3 and a fourth diode D 4 . A cathode of the third diode D 3 is coupled to the DC positive output node+Vb, an anode of the third diode D 3 is coupled to a second bridge arm upper node Pu 2 , an anode of the fourth diode D 4 is coupled to the DC negative output node −Vb, and a cathode of the fourth diode D 4 is coupled to a second bridge arm lower node Pw 2 .

The boost circuit 10 includes at least one fifth diode D 5 , at least one sixth diode D 6 , and at least two capacitors. The at least one fifth diode D 5 is coupled between the first bridge arm Lb 1 and the secondary side second node Ps 2 . The at least one sixth diode D 6 is coupled between the second bridge arm Lb 2 and the secondary side first node Ps 1 . The at least two capacitors are coupled to the secondary side first node Ps 1 and the secondary side second node Ps 2 .

As shown in FIG. 5 , the number of the at least two capacitors is two, including a first capacitor C 1 and a second capacitor C 2 . Two ends of the first capacitor C 1 are coupled to the secondary side first node Ps 1 and the first bridge arm upper node Pu 1 , and two ends of the second capacitor C 2 are coupled to the secondary side second node Ps 2 and the second bridge arm upper node Pu 2 . A cathode of the fifth diode D 5 is coupled to the first bridge arm upper node Pu 1 , and an anode of the fifth diode D 5 is coupled to the secondary side second node Ps 2 ; a cathode of the sixth diode D 6 is coupled to the second bridge arm upper node Pu 2 , and an anode of the sixth diode D 6 is coupled to the secondary side first node Ps 1 .

As shown in FIG. 6 , the number of the at least two capacitors is two, including a first capacitor C 1 and a second capacitor C 2 . Two ends of the first capacitor C 1 are coupled to the secondary side first node Ps 1 and the first bridge arm lower node Pw 1 , and two ends of the second capacitor C 2 are coupled to the secondary side second node Ps 2 and the second bridge arm lower node Pw 2 . An anode of the fifth diode D 5 is coupled to the first bridge arm lower node Pw 1 , and a cathode of the fifth diode D 5 is coupled to the secondary side second node Ps 2 ; an anode of the sixth diode D 6 is coupled to the second bridge arm lower node Pw 2 , and a cathode of the sixth diode D 6 is coupled to the secondary side first node Ps 1 .

The diode-capacitor circuit, which is coupled to the secondary side of the transformer T 1 , is proposed to charge the capacitors through the secondary side coil turns, thereby reducing coil turns, increasing conversion efficiency, and reducing occupied volume. Further, the diode-capacitor circuit can be used in a variety of isolated converters capable of operating both in a first quadrant and a third quadrant.

Please refer to FIG. 7 , which shows a schematic diagram of current paths of a first-quadrant operation in FIG. 5 . When the isolated converter operates in a first quadrant, a main current Ic 1 flows through the secondary side of the transformer T 1 , the second capacitor C 2 , the third diode D 3 , the DC positive output node+Vb, the DC negative output node −Vb, the second diode D 2 , and the secondary side. A pre-charge current Ic 2 flows through the secondary side of the transformer T 1 , the fifth diode D 5 , the first capacitor C 1 , and the secondary side. In particular, the first capacitor C 1 is charged by the pre-charge current Ic 2 .

In addition, when the isolated converter shown in FIG. 6 operates in a first quadrant (not shown), a main current flows through the secondary side of the transformer T 1 , the third diode D 3 , the DC positive output node+Vb, the DC negative output node −Vb, the second diode D 2 , the first capacitor C 1 , and the secondary side. A pre-charge current flows through the secondary side of the transformer T 1 , the second capacitor C 2 , the sixth diode D 6 , and the secondary side.

Please refer to FIG. 8 , which shows a schematic diagram of current paths of a third-quadrant operation in FIG. 5 . When the isolated converter operates in a third quadrant, a main current Ic 1 flows through the secondary side of the transformer T 1 , the first capacitor C 1 , the first diode D 1 , the DC positive output node+Vb, the DC negative output node −Vb, the fourth diode D 4 , and the secondary side. A pre-charge current Ic 2 flows through the secondary side of the transformer T 1 , the sixth diode D 6 , the second capacitor C 2 , and the secondary side. Similarly, when the isolated converter shown in FIG. 6 operates in a third quadrant (not shown), a main current flows through the secondary side of the transformer T 1 , the first diode D 1 , the DC positive output node+Vb, the DC negative output node −Vb, the fourth diode D 4 , the second capacitor C 2 , and the secondary side. A pre-charge current flows through the secondary side of the transformer T 1 , the first capacitor C 1 , the fifth diode D 5 , and the secondary side.

Please refer to FIG. 9 , which shows a single-bus circuit structure of the isolated converter with high boost ratio according to a third embodiment of the present disclosure, and the circuit structure of FIG. 9 is a combination of the circuit structure of FIG. 5 and the circuit structure of FIG. 6 . As shown in FIG. 9 , the number of the at least two capacitors is four, including a first capacitor C 1 , a second capacitor C 2 , a third capacitor C 3 , and a fourth capacitor C 4 . The number of the at least one fifth diode D 5 is two, including an upper fifth diode D 5 and a lower fifth diode D 5 . The number of the at least one sixth diode D 6 is two, including an upper sixth diode D 6 and a lower sixth diode D 6 .

Two ends of the first capacitor C 1 are coupled to the secondary side first node Ps 1 and the first bridge arm upper node Pu 1 . Two ends of the second capacitor C 2 are coupled to the secondary side second node Ps 2 and the second bridge arm upper node Pu 2 . Two ends of the third capacitor C 3 are coupled to the secondary side first node Ps 1 and the first bridge arm lower node Pw 1 . Two ends of the fourth capacitor C 4 are coupled to the secondary side second node Ps 2 and the second bridge arm lower node Pw 2 .

A cathode of the upper fifth diode D 5 is coupled to the first bridge arm upper node Pu 1 , and an anode of the upper fifth diode D 5 is coupled to the secondary side second node Ps 2 . A cathode of the upper sixth diode D 6 is coupled to the second bridge arm upper node Pu 2 , and an anode of the upper sixth diode D 6 is coupled to the secondary side first node Ps 1 . An anode of the lower fifth diode D 5 is coupled to the first bridge arm lower node Pw 1 , and a cathode of the lower fifth diode D 5 is coupled to the secondary side second node Ps 2 . An anode of the lower sixth diode D 6 is coupled to the second bridge arm lower node Pw 2 , and a cathode of the lower sixth diode D 6 is coupled to the secondary side first node Ps 1 .

In the circuit structure shown in FIG. 9 , when the isolated converter operates in a first quadrant (not shown), a main current flows through the secondary side of the transformer T 1 , the second capacitor C 2 , the third diode D 3 , the DC positive output node+Vb, the DC negative output node −Vb, the second diode D 2 , the third capacitor C 3 , and the secondary side. A first pre-charge current flows through the secondary side, the upper fifth diode D 5 , the first capacitor C 1 , and the secondary side. A second pre-charge current flows through the secondary side, the fourth capacitor C 4 , the lower sixth diode D 6 , and the secondary side. When the isolated converter operates in a third quadrant (not shown), a main current flows through the secondary side, the first capacitor C 1 , the first diode D 1 , the DC positive output node+Vb, the DC negative output node −Vb, the fourth diode D 4 , the fourth capacitor C 4 , and the secondary side. A first pre-charge current flows through the secondary side, the upper sixth diode D 6 , the second capacitor C 2 , and the secondary side. A second pre-charge current flows through the secondary side, the third capacitor C 3 , the lower fifth diode D 5 , and the secondary side.

Please refer to FIG. 10 , which shows a single-bus circuit structure of the isolated converter with high boost ratio according to a fourth embodiment of the present disclosure. The main difference between FIG. 10 and FIG. 9 is that all the diodes D 1 -D 6 in FIG. 9 are replaced by power switches S 1 -S 6 . In this embodiment, the power switches S 1 -S 6 are, for example but not limited to, metal-oxide-semiconductor field-effect transistors (MOSFETs). By actively controlling the power switches S 1 -S 6 , the isolated converter can achieve the function of bidirectional operation. Similarly, the diodes in the isolated converters shown in FIG. 5 , FIG. 6 , and FIG. 9 also can be replaced by power switches so that the isolated converter can achieve the function of bidirectional operation and achieve less conduction loss. In FIG. 5 , FIG. 6 , and FIG. 9 , the “diode” is not limited to a diode that is independently packaged, it can be also a parasitic element of the power switch, such as a body diode of the MOSFET.

Please refer to FIG. 11 , which shows a dual-bus circuit structure of the isolated converter with high boost ratio according to the present disclosure. In the same concept of the diode-capacitor circuit, the dual-bus circuit structure is proposed for the specific application, such as a dual-bus output of the UPS's power converter. In comparison with the single-bus circuit structure of the isolated converter with high boost ratio shown in FIG. 9 , the dual-bus circuit structure of the isolated converter with high boost ratio shown in FIG. 11 further includes a center-tapped node Pct. Therefore, balance charging and discharging operation of the dual-bus output voltage can be implemented through the center-tapped structure, and the circuit is similar to FIG. 9 and will not be repeated here.

Please refer to FIG. 12 , which shows a circuit diagram of a push-pull converter having the single-bus circuit structure in FIG. 5 . The diode-capacitor circuit shown in FIG. 5 is applied to the push-pull converter having the single-bus circuit structure to achieve the DC-to-DC converter with high boost ratio and high efficiency. Moreover, it can be controlled by a fixed frequency control manner.

In addition, the diode-capacitor circuit shown in FIG. 6 , FIG. 9 , and FIG. 10 is also suitable for the push-pull converter (its detailed circuit diagram is not shown) having the single-bus circuit.

Please refer to FIG. 13 , which shows a circuit diagram of a full-bridge converter having the single-bus circuit structure in FIG. 5 . The diode-capacitor circuit shown in FIG. 5 is applied to the full-bridge converter having the single-bus circuit structure to achieve the DC-to-DC converter with high boost ratio and high efficiency.

In addition, the diode-capacitor circuit shown in FIG. 6 , FIG. 9 , and FIG. 10 is also suitable for the full-bridge converter (its detailed circuit diagram is not shown) having the single-bus circuit.

Please refer to FIG. 14 , which shows a circuit diagram of a full-bridge LLC resonant converter having the single-bus circuit structure in FIG. 5 . The diode-capacitor circuit shown in FIG. 5 is applied to the full-bridge LLC resonant converter having the single-bus circuit structure to achieve the DC-to-DC converter with high boost ratio and high efficiency.

In addition, the diode-capacitor circuit shown in FIG. 6 , FIG. 9 , and FIG. 10 is also suitable for the full-bridge LLC resonant converter (its detailed circuit diagram is not shown) having the single-bus circuit.

Please refer to FIG. 15 , which shows a circuit diagram of a push-pull converter having the dual-bus circuit structure in FIG. 11 . The diode-capacitor circuit shown in FIG. 11 is applied to the push-pull converter having the dual-bus circuit structure to achieve the DC-to-DC converter with high boost ratio and high efficiency.

Please refer to FIG. 16 , which shows a circuit diagram of a full-bridge converter having the dual-bus circuit structure in FIG. 11 . The diode-capacitor circuit shown in FIG. 11 is applied to the full-bridge converter having the dual-bus circuit structure to achieve the DC-to-DC converter with high boost ratio and high efficiency.

Please refer to FIG. 17 , which shows a circuit diagram of a full-bridge LLC resonant converter having the dual-bus circuit structure in FIG. 11 . The diode-capacitor circuit shown in FIG. 11 is applied to the full-bridge LLC resonant converter having the dual-bus circuit structure to achieve the DC-to-DC converter with high boost ratio and high efficiency.

Although the present disclosure has been described with reference to the preferred embodiment thereof, it will be understood that the present disclosure is not limited to the details thereof. Various substitutions and modifications have been suggested in the foregoing description, and others will occur to those of ordinary skill in the art. Therefore, all such substitutions and modifications are intended to be embraced within the scope of the present disclosure as defined in the appended claims.