Receiving end of electronic device and method of setting phase threshold of timing recovery operation

1. Field of the Invention

The present invention generally relates to timing recovery technology, and, more particularly, to a method of setting the phase threshold of the timing recovery operation and to the receiving end of an electronic device that implements the method.

2. Description of Related Art

In the process of transmitting and receiving a signal, the transmission time at the transmitting end and the reception time at the receiving end may be out of synchronization when the transmitting end and the receiving end are affected by the external environment or the jitter effect. The degree of out of synchronization may be as small as a few phase differences, or so large that the frequencies at the transmitting end and the receiving end become different. The receiving end uses a timing recovery circuit to tackle this frequency or phase difference, and a suitable phase threshold is crucial to the stability of the system. A frequently switching phase is unfavorable to the convergence of the system. For example, various equalizers (e.g., the echo canceller, the feed forward equalizer, the feedback equalizer, etc.) tend to function improperly when operating in an unstable state (i.e., frequent phase switching), resulting in poor performance or malfunction of the system.

Therefore, a circuit and a method are needed to provide an appropriate phase threshold according to the current actual operating environment.

In view of the issues of the prior art, an object of the present invention is to provide a method of setting the phase threshold of the timing recovery operation and to provide the receiving end of the electronic device which implements the method.

A receiving end of an electronic device is provided. The receiving end of the electronic device includes an analog front end circuit, a phase detector, and a calculation circuit. The analog front end circuit is configured to receive an input signal and adjust a phase of the input signal according to a phase control signal. The phase detector is coupled to the analog front end circuit and configured to detect the phase of the input signal to generate a current phase value and a phase difference accumulated value, to calculate a target phase value according to the phase difference accumulated value, and to generate a first phase driving value according to the target phase value and the current phase value. The calculation circuit is coupled to the phase detector and the analog front end circuit and configured to generate the phase control signal according to the first phase driving value and a phase threshold. After the calculation circuit generates the phase control signal, the phase detector generates a second phase driving value, and the calculation circuit updates the phase threshold according to the first phase driving value and the second phase driving value.

A receiving end of an electronic device is provided. The receiving end of the electronic device includes an analog front end circuit, a phase detector, and a calculation circuit. The analog front end circuit is configured to receive an input signal and adjust a phase of the input signal according to a phase control signal. The phase detector is coupled to the analog front end circuit and configured to detect the phase of the input signal to generate a current phase value and a phase difference accumulated value, to calculate a target phase value according to the phase difference accumulated value, and to generate a first phase driving value according to the target phase value and the current phase value. The calculation circuit is coupled to the phase detector and the analog front end circuit and configured to generate the phase control signal according to the first phase driving value and a phase threshold. After the calculation circuit generates the phase control signal, the phase detector generates a second phase driving value, and the calculation circuit updates the phase threshold according to the phase threshold and the second phase driving value.

A method of setting a phase threshold of a timing recovery operation is provided. The method includes the following steps: (A) receiving an input signal; (B) detecting a phase of the input signal to generate a current phase value and a phase difference accumulated value; (C) calculating a target phase value according to the phase difference accumulated value; (D) generating a first phase driving value according to the target phase value and the current phase value; (E) generating a phase control signal according to the first phase driving value and a phase threshold; (F) adjusting the phase of the input signal according to the phase control signal; (G) repeating steps (A) to (C) to update the target phase value and the current phase value; (H) generating a second phase driving value according to the updated target phase value and the updated current phase value; and (I) updating the phase threshold according to an absolute difference between the first phase driving value and the second phase driving value, or according to an absolute difference between the phase threshold and the second phase driving value.

The phase threshold adjustment mechanism of the present invention can determine a new phase threshold according to the current phase interval. In comparison with the prior art, the present invention can prevent the receiving end from being out of synchronization in phase with the transmitting end due to failing to adjust the phase in time, as well as prevent the transient error or the decreased signal-to-noise ratio (SNR) in the receiving end due to adjusting the phase too frequently.

These and other objectives of the present invention no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiments with reference to the various figures and drawings.

FIG. 1 illustrates a functional block diagram of the receiving end of the electronic device according to an embodiment of the present invention.

FIG. 2 illustrates a schematic diagram of the phase intervals in one period.

FIG. 3 illustrates a flowchart of setting the phase threshold of the timing recovery operation according to an embodiment of the present invention.

FIG. 4 shows that the phase detector 130 generates an accumulated phase driving value B in each period.

FIGS. 5A and 5B illustrate an example of phase change.

FIGS. 6A and 6B illustrate another example of phase change.

The following description is written by referring to terms of this technical field. If any term is defined in this specification, such term should be interpreted accordingly. In addition, the connection between objects or events in the below-described embodiments can be direct or indirect provided that these embodiments are practicable under such connection. Said “indirect” means that an intermediate object or a physical space exists between the objects, or an intermediate event or a time interval exists between the events.

The disclosure herein includes method of setting a phase threshold of a timing recovery operation and a receiving end of an electronic device that implements the method. On account of that some or all elements of the receiving end of the electronic device could be known, the detail of such elements is omitted provided that such detail has little to do with the features of this disclosure, and that this omission nowhere dissatisfies the specification and enablement requirements. The method of setting a phase threshold can be performed by the receiving end of the electronic device or its equivalent. A person having ordinary skill in the art can choose components or steps equivalent to those described in this specification to carry out the present invention, which means that the scope of this invention is not limited to the embodiments in the specification.

FIG. 1 is a functional block diagram of the receiving end of the electronic device according to an embodiment of the present invention. The receiving end 100 includes an analog front end (AFE) circuit 110 , an analog-to-digital converter (ADC) 120 , a phase detector (PD) 130 , a calculation circuit 140 , and a memory 150 . The AFE circuit 110 is controlled by the phase control signal to adjust the phase of the input signal. The AFE circuit 110 divides a period into multiple phase intervals, according to which the adjustment of the phase is performed. In practice, due to the limitation of the circuit itself, the phase intervals are not equal. FIG. 2 is a schematic diagram illustrating the phase intervals within one period. As shown in FIG. 2 , the phase intervals close to 0 degrees are relatively narrow, while the phase intervals close to 359 degrees are relatively wide. FIG. 2 is only an example of uneven phase intervals. The present invention is not limited to this example and can also be applied to other kinds of uneven phase intervals.

In some embodiments, the phase control signal controls the AFE circuit 110 to make the phase of the input signal larger (i.e., increase the phase) or make the phase of the input signal smaller (i.e., decrease the phase). For example, a phase control signal of a high voltage level controls the AFE circuit 110 to adjust the phase of the input signal from P N to P N+1 , and a phase control signal of a low voltage level controls the AFE circuit 110 to adjust the phase of the input signal from P N to P N−1 . In some embodiments, the calculation circuit 140 controls the AFE circuit 110 to adjust the phase of the input signal by one phase interval (increase or decrease) at a time.

Reference is made to FIG. 1 to FIG. 3 for the discussions below. FIG. 3 is a flowchart of setting the phase threshold of the timing recovery operation according to an embodiment of the present invention. The AFE circuit 110 receives the input signal and adjusts the phase of the input signal according to the phase control signal (step S 310 ), and then the ADC 120 converts the input signal from the analog domain to the digital domain. In each period of the input signal, the phase detector 130 detects the phase of the input signal to generate a current phase value and a phase difference accumulated value (step S 315 ) and calculates the target phase value according to the phase difference accumulated value (step S 320 ). In the current operating environment, if the AFE circuit 110 adjusts the phase of the input signal to the target phase value, the receiving end 100 will operate in a better state (e.g., a better signal-to-noise ratio (SNR)). In other words, the target phase value is the ideal phase of the input signal under the current operating environment. The calculations of the current phase value, the phase difference accumulated value, and the target phase value are techniques well known to people having ordinary skill in the art, so the details shall be omitted herein for brevity (Please refer to: Wolaver, Dan H. (1991), Phase - Locked Loop Circuit Design , Prentice Hall, ISBN 0-13-662743-9). The phase detector 130 further generates an accumulated phase driving value according to the target phase value and the current phase value within a set time length (e.g., Y unit time in the digital domain, which unit time may be, for example, the period of a system clock, Y is a positive integer) (step S 325 , which will be discussed in detail below). After receiving the phase driving value, the calculation circuit 140 may store it in the memory 150 .

After receiving the phase driving value from the phase detector 130 , the calculation circuit 140 determines whether the phase threshold needs updating (e.g., to determine whether the flag FLG is 1, the flag FLG can be stored in the memory 150 ) (step S 330 ). If the result of step S 330 is YES (e.g., the flag FLG=1), the calculation circuit 140 determines whether the number of accumulated phase driving values is greater than a target value (step S 335 ). When the number of accumulated phase driving values is greater than the target value (the result of step S 335 is YES), the calculation circuit 140 calculates the average of the phase driving values (step S 340 ). The purpose of step S 335 and step S 340 is to prevent frequent updating of the phase threshold due to the instantaneous extreme value of the phase driving value; these two steps are beneficial to improve the stability and accuracy of the process in FIG. 3 .

However, in some embodiments, the calculation circuit 140 does not calculate the average of the phase driving values (i.e., step S 335 and step S 340 are not performed); instead, the calculation circuit 140 performs step S 345 after determining that the phase threshold needs updating (the result of step S 330 is YES). In the embodiment where the average of the phase driving values is not calculated, the calculation circuit 140 updates, in step S 345 , the phase threshold according to the current phase driving value and the phase driving value prior to the phase adjustment or, alternatively, updates the phase threshold according to the current phase driving value and the current phase threshold. Step S 345 will be discussed in detail below.

When the number of accumulated phase driving values is greater than the target value (the result of step S 335 is YES), the calculation circuit 140 calculates the average of the phase driving values (step S 340 ) and then updates the phase threshold according to both the average value and the phase driving value prior to the phase adjustment, or according to both the average value and the current phase threshold (step S 345 , which will be discussed in detail below). After the phase threshold is updated, the calculation circuit 140 sets the flag FLG to 0 which indicates that the phase threshold does not need updating (step S 350 ).

When the result of step S 330 is NO, or the result of step S 335 is NO, the calculation circuit 140 determines whether the phase driving value is greater than the phase threshold (step S 355 ). If the result of step S 355 is NO, the process returns to step S 310 , and the AFE circuit 110 proceeds to receive the input signal. In other words, when the phase driving value is not greater than the phase threshold, the calculation circuit 140 does not perform step S 360 (i.e., does not generate the phase control signal).

If the result of step S 355 is YES, the calculation circuit 140 generates the phase control signal (step S 360 ) and sets the flag FLG to 1 which indicates that the phase threshold needs updating (step S 370 ). Steps S 360 and S 370 will be discussed in detail below in connection with FIG. 4 .

FIG. 4 shows that the phase detector 130 generates an accumulated phase driving value B in each period: the phase driving value B 1 is generated between time points T and 2T (T is the period of the input signal), the phase driving value B 2 is generated between time points 2T and 3T, the phase driving value B 3 is generated between time points 3T and 4T, and so on. Assuming that the phase driving value B 3 is greater than the phase threshold (the result of step S 355 is YES), the calculation circuit 140 generates the phase control signal to control the AFE circuit 110 to adjust the phase of the input signal (step S 360 ) and sets the flag FLG to 1 (step S 370 ). Taking FIG. 4 as an example and assuming that the target value of step S 335 is three and the phase driving values B 4 , B 5 , and B 6 are not greater than the phase threshold, the calculation circuit 140 calculates the average of the phase driving values B 4 , B 5 , and B 6 in step S 340 , and then, in step S 345 , the calculation circuit 140 updates the phase threshold according to the average phase driving value (i.e., the average of B 4 , B 5 and B 6 ) and the phase driving value prior to the phase adjustment (i.e., B 3 ) or, alternatively, updates the phase threshold according to the average phase driving value and the current phase threshold.

In the following, the steps of FIG. 3 and the operation details of the phase detector 130 and the calculation circuit 140 are discussed in detail by referring to the phase changes shown in FIGS. 5A and 5B . FIGS. 5A and 5B show the relationships between the target phase value PT, the current phase value PC, the phase threshold P th , and the phase driving value B. In the example of FIGS. 5A and 5B , the AFE circuit 110 was operating in the range of wide phase intervals (as shown in FIG. 5A , the current phase value PC corresponds to the phase P N , which is in the range of wide phase intervals (e.g., |P N+ −P N |)). After a period of time, due to changes in the environment (such as the voltage or temperature), the AFE circuit 110 has become to operate in the range of narrow phase intervals (as shown in FIG. 5B , the current phase value PC′ corresponds to the phase P M , which is in the range of narrow phase intervals (e.g., |P M+1 +P M |)) (where |P M+1 −P M |<|P N+1 −P N |).

The phase driving value is the difference between the target phase value and the current phase value (i.e., B=PT−PC, B′=PT−PC′, B″=PT−PC″). A smaller absolute value of the phase driving value B (or B′, B″) indicates that the receiving end 100 is operating in a relatively stable state. A greater absolute value of the phase driving value B (or B′, B″) indicates that the receiving end 100 is operating in a relatively unstable state (which means that the AFE circuit 110 may be about to adjust the phase of the input signal or must immediately adjust the phase of the input signal).

It is assumed in FIGS. 5A and 5B that the magnitude of the old (i.e., prior to the update) phase threshold P th is set to correspond to a phase interval (i.e., P th corresponds to P N+1 −P N ). Since the magnitude of the phase driving value B is smaller than the phase threshold P th in the example of FIG. 5A , the result of step S 355 in FIG. 3 is NO.

In FIG. 5B , when the absolute value of the difference between the target phase value PT and the current phase value PC′ (i.e., the absolute value of the phase driving value B′) is greater than the old phase threshold P th (i.e., |B′|>P th , the result of step S 355 is YES), the calculation circuit 140 generates the phase control signal (step S 360 ) and sets the flag FLG to 1 (step S 370 ). In this instance, since the phase driving value B′ is a positive number (because the target phase value PT is greater than the current phase value PC′), in the next step S 310 the AFE circuit 110 switches, according to the phase control signal, the current phase value of the input signal from PC′ (corresponding to the phase P M ) to PC″ (corresponding to the phase P M+1 ).

Even though the AFE circuit 110 has adjusted the phase of the input signal, the two target phase values PT generated in two consecutive steps S 320 are very similar because the operating environment of the receiving end 100 usually does not change significantly in a short period of time. In other words, as shown in FIG. 5B , within a short period of time (depending on the operating environment) after the current phase value has just changed from the current phase value PC′ to the current phase value PC″, the change of the target phase value PT is 0 or very small.

Next, the phase detector 130 generates a phase driving value B″ in step S 325 . The calculation circuit 140 updates the phase threshold P th according to the phase driving value B″ (or the average of multiple phase driving values B″) and the phase driving value B′, or according to the phase driving value B″ (or the average of multiple phase driving values B″) and the old phase threshold P th (step S 345 ). More specifically, in some embodiments, the new (updated) P th ∝=α|B″− B″ | ( B″ is an average of multiple phase driving values B″, where a (a rational number) is the multiple ratio). In other embodiments, when the target phase value PT is very close to the phase threshold P th (i.e., when B′≅P th ), P th ′=α|P th − B″ |. In the embodiment where the average of the phase driving values B is not calculated (i.e., steps S 335 and S 340 are skipped), B″ =B″. In some embodiments, α=1, that is, the new P th ′=|B′− B″ | (or P th =|P th − B″ |). Taking FIG. SB as an example, when α=1, P th ′ is approximately at the position of the current phase value PC″.

As shown in FIG. 5B , |B′− B″ | can reflect the distance between the phase P M+1 and the phase P M (i.e., the current phase interval, that is, the current differential nonlinearity (DNL)). In other words, the new P th ′ is determined based on the current phase interval, so the new P th ′ is proportional to the current phase interval.

FIGS. 6A and 6B show another example of phase change. In this example, the AFE circuit 110 which was operating in the range of narrow phase intervals (as shown in FIG. 6A ) has gradually become to operate in the range of wide phase intervals (as shown in FIG. 6B ). In the example of FIG. 6 , since the phase driving value B′ is a positive number (because the target phase value PT is greater than the current phase value PC′), which is the same as the case in FIG. 5 , the AFE circuit 110 switches, according to the phase control signal, the current phase value of the input signal from PC′ (corresponding to the phase P M ) to PC″ (corresponding to the phase P M+1 ) (step S 310 ). In FIG. 6B , since the target phase value PT is smaller than the current phase value PC″, the phase driving value B″ is a negative number (B″=PT−PC″<0). Similar to FIG. 5B , because |B′− B″ | (=B′+| B″ |) reflects the phase interval of FIG. 6B (i.e., the distance between the phase P M+1 and the phase P M ), the new P th ′=α|B′− B″ | is also determined according to the current phase interval (proportional to |B′− B″ |).

The phase threshold adjustment mechanism discussed above can determine a new phase threshold according to the phase range (a range of wide phase intervals or narrow phase intervals) in which the AFE circuit 110 is currently operating. Therefore, when the current phase value PC of the AFE circuit 110 shifts from a wide phase interval to a narrow phase interval (as the case of FIG. 5 ), the calculation circuit 140 decreases the phase threshold P th to avoid being out of synchronization with the transmitting end due to the system's failing to adjust the phase in time. On the other hand, when the current phase value PC of the AFE circuit 110 shifts from a narrow phase interval to a wide phase interval (as the case of FIG. 6 ), the calculation circuit 140 increases the phase threshold P th to avoid a transient error or a decreased SNR in the system due to frequent phase adjustments.

People having ordinary skill in the art can implement the calculation circuit 140 with logic circuits, a digital signal processor (DSP), a finite state machine, or equivalent circuits according to the flow in FIG. 3 . The receiving end 100 can be applied in a wired environment or a wireless environment.

Since a person having ordinary skill in the art can appreciate the implementation detail and the modification thereto of the present method invention through the disclosure of the device invention, repeated and redundant description is thus omitted. Please note that there is no step sequence limitation for the method inventions as long as the execution of each step is applicable. Furthermore, the shape, size, and ratio of any element and the step sequence of any flowchart in the disclosed figures are exemplary for understanding, not for limiting the scope of this invention.

The aforementioned descriptions represent merely the preferred embodiments of the present invention, without any intention to limit the scope of the present invention thereto. Various equivalent changes, alterations, or modifications based on the claims of the present invention are all consequently viewed as being embraced by the scope of the present invention.