Data driver, display apparatus including the same and method of sensing threshold voltage of pixel using the same

This application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2020-0087706, filed on Jul. 15, 2020 in the Korean Intellectual Property Office (KIPO), the content of which is herein incorporated by reference in its entirety.

The present inventive concept relates to a data driver, a display apparatus including the data driver, and a method of sensing a threshold voltage of a pixel using the display apparatus. More particularly, embodiments of the present inventive concept relate to a data driver outputting a sensing data voltage using only one output amplifier, a display apparatus including the data driver, and a method of sensing a threshold voltage of a pixel using the display apparatus.

Generally, a display apparatus includes a display panel and a display panel driver. The display panel includes a plurality of gate lines and a plurality of data lines. The display panel driver includes a gate driver and a data driver. The gate driver outputs gate signals to the gate lines. The data driver outputs data voltages to the data lines.

In a writing mode, the data driver may output a data voltage to the display panel. In a sensing mode, the data driver may output a sensing voltage to the display panel. In the sensing mode, the data driver may determine a threshold voltage of a switching element of a pixel by sensing a voltage of the pixel.

The data driver includes a plurality of amplifiers, and an error in the sensed threshold voltage may occur due to a voltage difference between the amplifiers. Due to the error, a display defect may occur in an image displayed on the display panel.

An embodiment of the present inventive concept provides a data driver for reducing a sensing error of a pixel's threshold voltage.

An embodiment of the present inventive concept provides a display apparatus including the data driver.

An embodiment of the present inventive concept provides a method of sensing a pixel's threshold voltage using the display apparatus.

In an embodiment of a data driver according to the present inventive concept, the data driver may include a plurality of amplifiers configured to output a plurality of data voltages to a plurality of data lines. The amplifiers are configured to output the data voltages to the corresponding data lines in a writing mode. Only one of the plurality of amplifiers is configured to output a sensing data voltage to the plurality of data lines in a sensing mode.

In an embodiment, the data driver may further include a first amplifier connected to a first data line, a switch connected between a second amplifier and a second data line, and at least one channel-connecting switch disposed at a connecting path between the first data line and the second data line.

In an embodiment, the at least one channel-connecting switch may include a first channel-connecting switch connected between the first data line and a common node and a second channel-connecting switch connected between the second data line and the common node.

In an embodiment, the switch may be turned on and the first channel-connecting switch and the second channel-connecting switch may be turned off in the writing mode. The switch may be turned off and the first channel-connecting switch and the second channel-connecting switch may be turned on in the sensing mode.

In an embodiment, the data driver may include a plurality of readout chips. The switch, the first channel-connecting switch and the second channel-connecting switch may be disposed in a first readout chip. The data driver may further include a first chip-connecting line connecting the first readout chip with a second readout chip, and a chip-connecting switch connected between the first chip-connecting line and at least one of the data lines.

In an embodiment, switch may be turned on, and the first channel-connecting switch, the second channel-connecting switch and the chip-connecting switch may be turned off in the writing mode. The switch may be turned off, and the first channel-connecting switch, the second channel-connecting switch and the chip-connecting switch may be turned on in the sensing mode.

In an embodiment, the data driver may further include a sensing amplifier and a sensing switch connected between the sensing amplifier and at least one of the data lines.

In an embodiment further comprising a first switch connected between the first amplifier and the first data line, the switch is a second switch, the first switch and the second switch may be turned on, and the first channel-connecting switch, the second channel-connecting switch and the sensing switch may be turned off in the writing mode. The first switch and the second switch may be turned off and the first channel-connecting switch, the second channel-connecting switch and the sensing switch may be turned on in the second mode.

In an embodiment, the data driver may include a plurality of readout chips. The first switch, the second switch, the first channel-connecting switch and the second channel-connecting switch may be disposed in a first readout chip. The data driver may further include a first chip-connecting line connecting the first readout chip with a second readout chip, a chip-connecting switch connected between the first chip-connecting line and at least one of the data lines, a sensing amplifier and a sensing switch connected between the sensing amplifier and at least one of the data lines.

In an embodiment, the first switch and the second switch may be turned on and the first channel-connecting switch, the second channel-connecting switch and the chip-connecting switch and the sensing switch may be turned off in the writing mode. The first switch and the second switch may be turned off, the first channel-connecting switch, the second channel-connecting switch, the chip-connecting switch and the sensing switch may be turned on in the sensing mode.

In an embodiment of a display apparatus according to the present inventive concept, the display apparatus includes a display panel and a data driver. The display panel is configured to display an image based on input image data. The display panel includes a plurality of data lines and a plurality of pixels connected to the data lines. The data driver includes a plurality of amplifiers configured to output data voltages to the data lines. The amplifiers are configured to output the data voltages to the corresponding data lines in a writing mode. Only one amplifier is configured to output a sensing data voltage to the data lines in a sensing mode.

In an embodiment, the pixel may include a first thin-film transistor configured to apply a first power voltage to a second node in response to a signal at a first node, a second thin-film transistor configured to output the data voltage to the first node in response to a first signal, a third thin-film transistor configured to output a signal at the second node to a sensing node in response to a second signal, a storage capacitor comprising a first end portion connected to the first node and a second end portion connected to the second node, and a light-emitting element comprising a first electrode connected to the second node and a second electrode configured to receive a second power voltage.

In an embodiment, the data driver may further include a first amplifier connected with a first data line, a switch connected between a second amplifier and a second data line, and at least one channel-connecting switch disposed at a connecting path between the first data line and the second data line.

In an embodiment, the at least one channel-connecting switch may include a first channel-connecting switch connected between the first data line and a common node, and a second channel-connecting switch connected between the second data line and the common node.

In an embodiment, the data driver may include a plurality of readout chips. The switch, the first channel-connecting switch and the second channel-connecting switch may be disposed in a first readout chip. The data driver may further include a first chip-connecting line connecting the first readout chip with a second readout chip, and a chip-connecting switch connected between the first chip-connecting line and at least one of the data lines.

In an embodiment, the data driver may further include a sensing amplifier and a sensing switch connected between the sensing amplifier and at least one of the data lines.

In an embodiment, the data driver may include a plurality of readout chips. The switch, the first channel-connecting switch and the second channel-connecting switch may be disposed in a first readout chip. The data driver may further include a first chip-connecting line connecting the first readout chip and a second readout chip, a chip-connecting switch connected between the first chip-connecting line and at least one of the data lines, a sensing amplifier and a sensing switch connected between the sensing amplifier and at least one of the data lines.

In an embodiment of a method of sensing a threshold voltage of a pixel according to the present inventive concept, the method includes outputting a plurality of data voltages to a plurality of corresponding data lines connected to a plurality of pixels using a plurality of amplifiers in a writing mode, outputting a sensing data voltage to the data lines using only one amplifier in a sensing mode and receiving a sensing signal using a plurality of sensing lines connected to the pixels in the sensing mode.

In an embodiment, a first amplifier is connected to a first data line, a switch connected between a second amplifier and a second data line may be turned on, and a channel-connecting switch connected between the first data line and the second data line may be turned off in the writing mode.

In an embodiment, the switch may be turned off and the channel-connecting switch may be turned on in the sensing mode.

According to the data driver, the display apparatus and the method of sensing the threshold voltage of the pixel, the sensing data voltage is output using only one output amplifier in the single readout chip or in the plurality of readout chips in the sensing mode so that the sensing error of the threshold voltage of the pixel may be minimized.

Thus, display defects due to sensing errors of the pixel's threshold voltage may be prevented and the display quality of the display panel may be optimized.

The above and other features of the present inventive concept may become more apparent by reviewing detailed embodiments thereof with reference to the accompanying drawings, in which:

FIG. 1 is a block diagram illustrating a display apparatus according to an embodiment of the present inventive concept;

FIG. 2 is a plan view diagram illustrating the display apparatus of FIG. 1 ;

FIG. 3 is a circuit diagram illustrating a pixel of FIG. 1 ;

FIG. 4 is a timing diagram illustrating input and output signals of the pixel of FIG. 3 in a sensing mode;

FIG. 5 is a plan view diagram illustrating readout chips of FIG. 2 and chip connecting lines connecting the readout chips;

FIG. 6 is a circuit diagram illustrating the readout chips of FIG. 2 in the sensing mode;

FIG. 7 is a circuit diagram illustrating the readout chips of FIG. 2 in a writing mode;

FIG. 8 is a circuit diagram illustrating readout chips of a display apparatus according to an embodiment of the present inventive concept;

FIG. 9 is a circuit diagram illustrating readout chips of a display apparatus according to an embodiment of the present inventive concept; and

FIG. 10 is a circuit diagram illustrating readout chips of a display apparatus according to an embodiment of the present inventive concept.

Hereinafter, the present inventive concept will be explained in detail with reference to the accompanying drawings.

FIG. 1 shows a display apparatus 10 according to an embodiment of the present inventive concept.

Referring to FIG. 1 , the display apparatus 10 includes a display panel 100 and a display panel driver. The display panel driver includes a driving controller 200 , a gate driver 300 that may but need not be integrally formed in the display panel 100 , a gamma reference voltage generator 400 , and a data driver 500 .

For example, the driving controller 200 and the data driver 500 may be integrally formed. For example, the driving controller 200 , the gamma reference voltage generator 400 and the data driver 500 may be integrally formed. A driving module including at least the driving controller 200 and the data driver 500 which are integrally formed may be called to a timing controller embedded data driver (TED).

The display panel 100 has a display region AA on which an image is displayed and a peripheral region PA adjacent to the display region AA.

For example, in the present embodiment, the display panel 100 may be an organic light emitting diode display panel including an organic light emitting diode. Alternatively, the display panel 100 may be a liquid crystal display panel including a liquid crystal layer.

The display panel 100 includes a plurality of gate lines GL, a plurality of data lines DL and a plurality of pixels P connected to the gate lines GL and the data lines DL. The gate lines GL extend in a first direction D 1 and the data lines DL extend in a second direction D 2 crossing the first direction Dl.

The driving controller 200 receives input image data IMG and an input control signal CONT from an external apparatus. The input image data IMG may include red image data, green image data and blue image data. The input image data IMG may include white image data. The input image data IMG may include magenta image data, yellow image data and cyan image data. The input control signal CONT may include a master clock signal and a data enable signal. The input control signal CONT may further include a vertical synchronizing signal and a horizontal synchronizing signal.

The driving controller 200 generates a first control signal CONT 1 , a second control signal CONT 2 , a third control signal CONT 3 and a data signal DATA based on the input image data IMG and the input control signal CONT.

The driving controller 200 generates the first control signal CONT 1 for controlling an operation of the gate driver 300 based on the input control signal CONT, and outputs the first control signal CONT 1 to the gate driver 300 . The first control signal CONT 1 may further include a vertical start signal and a gate clock signal.

The driving controller 200 generates the second control signal CONT 2 for controlling an operation of the data driver 500 based on the input control signal CONT, and outputs the second control signal CONT 2 to the data driver 500 . The second control signal CONT 2 may include a horizontal start signal and a load signal.

The driving controller 200 generates the data signal DATA based on the input image data IMG. The driving controller 200 outputs the data signal DATA to the data driver 500 .

The driving controller 200 generates the third control signal CONT 3 for controlling an operation of the gamma reference voltage generator 400 based on the input control signal CONT, and outputs the third control signal CONT 3 to the gamma reference voltage generator 400 .

The gate driver 300 generates gate signals driving the gate lines GL in response to the first control signal CONT 1 received from the driving controller 200 . The gate driver 300 outputs the gate signals to the gate lines GL. For example, the gate driver 300 may sequentially output the gate signals to the gate lines GL.

In the present example embodiment, the gate driver 300 may be integrated on the peripheral region PA of the display panel 100 .

The gamma reference voltage generator 400 generates a gamma reference voltage VGREF in response to the third control signal CONT 3 received from the driving controller 200 . The gamma reference voltage generator 400 provides the gamma reference voltage VGREF to the data driver 500 . The gamma reference voltage VGREF has a value corresponding to a level of the data signal DATA.

In an embodiment, the gamma reference voltage generator 400 may be disposed in the driving controller 200 , or in the data driver 500 , without limitation.

The data driver 500 receives the second control signal CONT 2 and the data signal DATA from the driving controller 200 , and receives the gamma reference voltages VGREF from the gamma reference voltage generator 400 . The data driver 500 converts the data signal DATA into data voltages having an analog type using the gamma reference voltages VGREF. The data driver 500 outputs the data voltages to the data lines DL.

FIG. 2 shows the display apparatus of FIG. 1 in a plan view.

Referring to FIGS. 1 and 2 , the display apparatus may include a printed circuit board assembly PBA, a first printed circuit P 1 and a second printed circuit P 2 . The printed circuit board assembly PBA may be connected to the first printed circuit P 1 and the second printed circuit P 2 . For example, the driving controller 200 may be disposed on the printed circuit board assembly PBA.

The display apparatus may further include a plurality of flexible circuits FP connected to the first printed circuit P 1 and the display panel 100 . The display apparatus may further include another plurality of flexible circuits FP connected to the second printed circuit P 2 and the display panel 100 .

Readout chips RSIC of the data driver 500 may be disposed on the flexible circuits FP. Each readout chip RSIC may be an integrated circuit chip.

FIG. 3 shows a circuit for the pixel P of FIG. 1 . FIG. 4 shows timing of input and output signals for the circuit of the pixel P of FIG. 3 in a sensing mode.

Referring to FIGS. 1 through 4 , the pixel P may include a first thin film transistor T 1 applying a first power voltage ELVDD to a second node N 2 in response to a signal at a first node N 1 , a second thin film transistor T 2 applying the data voltage VDATA to the first node N 1 in response to a first signal S 1 , a third thin film transistor T 3 applying a signal at the second node N 2 to a sensing node NS in response to a second signal S 2 , a storage capacitor CS including a first end portion connected to the first node N 1 and a second end portion connected to the second node N 2 , and a light emitting element EE including a first electrode connected to the second node N 2 and a second electrode receiving a second power voltage ELVSS.

Herein, the second power voltage ELVSS may be less than the first power voltage ELVDD. For example, the light emitting element may be an organic light emitting diode.

The pixel P may further include a switch SW applying a sensing initialization voltage VSEN to the second node N 2 via the third thin film transistor T 3 . The switch SW may be turned on and turned off based on a third signal S 3 .

For example, the second signal S 2 and the third signal S 3 are activated in a sensing initialization step so that the sensing initialization voltage VSEN may be applied to the second node N 2 .

As shown in FIG. 4 , the first signal S 1 is activated in a sensing mode so that a data voltage VDATA may be applied to the first node N 1 through the second thin film transistor T 2 . Herein, the data voltage VDATA may be a sensing data voltage applied to sense a threshold voltage of the first thin film transistor.

The first thin film transistor T 1 is turned on by the sensing data voltage applied to the first node in the sensing mode, and by the sensing initialization voltage VSEN which has already been applied to the second node in the sensing initialization step.

In addition, the second signal S 2 is also activated in the sensing mode so that the third thin film transistor T 3 is turned on and the signal VR at the second node N 2 may be output to the sensing node NS through the third thin film transistor T 3 in the sensing mode.

An analog-to-digital converter ADC is connected to the sensing node NS. The analog-to-digital converter ADC may convert the signal VR at the sensing node NS to a digital sensing signal to sense the threshold voltage of the first thin film transistor T 1 .

In the sensing mode, the third signal S 3 is inactivated so that the sensing initialization voltage VSEN is not applied to the sensing node NS after initialization in the sensing mode. In the sensing mode, the second power voltage ELVSS has a high level so that the pixel P does not emit light.

FIG. 5 shows, in a plan view, readout chips RSIC 1 , RSIC 2 , RSIC 3 and RSIC 4 of FIG. 2 , and chip connecting lines CL 1 , CL 2 and CL 3 connecting the readout chips RSIC 1 , RSIC 2 , RSIC 3 and RSIC 4 . FIG. 6 shows a circuit including the readout chips RSIC 1 , RSIC 2 , RSIC 3 and RSIC 4 of FIG. 2 in the sensing mode. FIG. 7 shows a circuit including the readout chips RSIC 1 , RSIC 2 , RSIC 3 and RSIC 4 of FIG. 2 in a writing mode.

Referring to FIGS. 1 through 7 , the data driver 500 may include a plurality of readout chips RSIC 1 , RSIC 2 , RSIC 3 and RSIC 4 . The readout chips RSIC 1 , RSIC 2 , RSIC 3 and RSIC 4 may be connected to each other in the sensing mode through the chip connecting lines CL 1 , CL 2 and CL 3 and switches S 17 , S 27 , S 37 and S 47 , where S 17 may be replaced with a conductive connection in an alternate embodiment.

FIG. 5 illustrates a first chip connecting line CL 1 connecting a first readout chip RSIC 1 with a second readout chip RSIC 2 , a second chip connecting line CL 2 connecting the second readout chip RSIC 2 with a third readout chip RSIC 3 , and a third chip connecting line CL 3 connecting the third readout chip RSIC 3 with a fourth readout chip RSIC 3 . As shown in FIG. 6 , for example, the first chip connecting line CL 1 connecting the first readout chip RSIC 1 with the second readout chip RSIC 2 , the second chip connecting line CL 2 connecting the second readout chip RSIC 2 with the third readout chip RSIC 3 , and the third chip connecting line CL 3 connecting the third readout chip RSIC 3 with a fourth readout chip RSIC 3 may be formed as a main connecting line with branches extended from the main connecting line. In the present embodiment, the first through third chip connecting lines CL 1 , CL 2 and CL 3 may be respectively formed as shown in FIG. 5 and the first through third chip connecting lines CL 1 , CL 2 and CL 3 may be integratedly formed as shown in FIG. 6 .

The data driver 500 includes a plurality of amplifiers outputting the data voltages to the data lines. As shown in FIGS. 6 and 7 , each of the readout chips RSIC 1 , RSIC 2 , RSIC 3 and RSIC 4 may include the amplifiers outputting the data voltages to the data lines.

The data driver 500 may be operated in a writing mode and in the sensing mode. In the writing mode, the data voltage for displaying an image may be written in the pixels P of the display panel 100 . In the sensing mode, the threshold voltage of the pixels P may be sensed from the pixels P.

The sensing mode may be operated in a power on period when the display apparatus starts to turn on, in a black period between active periods when the image is written to the display panel 100 and in a power off period when the display apparatus starts to turn off. The driving controller 200 may compensate the data applied to the pixel P according to the sensed threshold voltage of the pixel and output the compensated data to the data driver 500 . The threshold voltage may vary from pixel to pixel due to process distribution and may vary from pixel to pixel according to usage times. If the threshold voltages of the pixels P are not compensated, a difference of display images of the pixels P may occur so that the display quality of the display panel 100 may be deteriorated.

In the writing mode, the amplifiers of the data driver 500 may output the data voltages to the corresponding data lines. In the writing mode, the plurality of amplifiers and the plurality of data lines may be matched one-to-one.

In contrast, in the sensing mode, a single amplifier of the data driver 500 may output the sensing data voltage to the plurality of data lines. In the sensing mode, the single amplifier and the plurality of data lines may be matched one-to-many.

In the present embodiment, for example, the sensing data voltage is applied to all of the data lines corresponding to the four readout chips RSIC 1 , RSIC 2 , RSIC 3 and RSIC 4 using the single amplifier A 11 of the data driver 500 in the sensing mode. In an alternate embodiment, the single amplifier used in the sensing mode may be different from all of the amplifiers used in the writing mode.

Alternatively, for example, the sensing data voltage may be applied to all of the data lines corresponding to eight readout chips disposed at the first printed circuit P 1 and the second printed circuit P 2 in FIG. 2 using the single amplifier A 11 of the data driver 500 .

As shown in FIG. 6 , the first readout chip RSIC 1 may include a first amplifier A 11 , a second amplifier A 12 and a third amplifier A 13 . Although the three amplifiers A 11 , A 12 and A 13 are illustrated in FIG. 6 for convenience of explanation, the first readout chip RSIC 1 may further include many amplifiers in addition to the three amplifiers A 11 , A 12 and A 13 . For example, when the number of channels of the first readout chip RSIC 1 is 960 , the readout chip RSIC 1 may include 960 amplifiers.

The first readout chip RSIC 1 may further include a first switch S 11 connected between the first amplifier A 11 and a first data line DL 11 , a second switch S 12 connected between the second amplifier A 12 and a second data line DL 12 and a third switch S 13 connected between the third amplifier A 13 and a third data line DL 13 . In an alternate embodiment, the first switch S 11 may be replaced with a conductive connection.

In addition, the first readout chip RSIC 1 may further include at least one channel connecting switch disposed at a connecting path between the first data line DL 11 and the second data line DL 12 . For example, the first readout chip RSIC 1 may include a first channel connecting switch S 14 connected between the first data line DL 11 and a common node and a second channel connecting switch S 15 connected between the second data line DL 12 and the common node.

In addition, the first readout chip RSIC 1 may further include at least one channel connecting switch disposed at a connecting path between the second data line DL 12 and the third data line DL 13 . For example, the first readout chip RSIC 1 may include the second channel connecting switch S 15 connected between the second data line DL 12 and the common node and a third channel connecting switch S 16 connected between the third data line DL 13 and the common node.

In addition, the first readout chip RSIC 1 may further include a first chip connecting switch S 17 disposed between the first chip connecting line CL 1 , which connects the first readout chip RSIC 1 and the second readout chip RSIC 2 , and at least one (e.g., DL 11 ) of the data lines.

In the present embodiment, in the writing mode, the first switch S 11 , the second switch S 12 and the third switch S 13 may be turned on and the first channel connecting switch S 14 , the second channel connecting switch S 15 , the third channel connecting switch S 16 and the chip connecting switch S 17 may be turned off.

Thus, in the writing mode, the amplifiers A 11 through A 13 and the data lines DL 11 through DL 13 form a one-to-one connection so that the data voltages are output to the data lines DL 11 through DL 13 by the amplifiers A 11 through A 13 .

In contrast, in the sensing mode, the first switch S 11 may be turned on; the second switch S 12 and the third switch S 13 may be turned off; the first channel connecting switch S 14 , the second channel connecting switch S 15 , the third channel connecting switch S 16 and the chip connecting switch S 17 may be turned on.

Thus, in the sensing mode, the first amplifier A 11 and the data lines DL 11 through DL 13 form a one-to-many connection so that substantially the same sensing data voltage is applied to the data lines DL 11 through DL 13 by only the first amplifier A 11 .

In addition, the sensing data voltage of the first amplifier A 11 of the first readout chip RSIC 1 may be transmitted to the second readout chip RSIC 2 through the chip connecting switch S 17 and the first chip connecting line CL 1 .

Therefore, in the sensing mode, the sensing data voltage may be applied to data lines DL 21 through DL 23 of the second readout chip RSIC 2 by only the first amplifier A 11 .

In the same way, in the sensing mode, the sensing data voltage may be output to data lines DL 31 through DL 33 of the third readout chip RSIC 3 and data lines DL 41 through DL 43 of the fourth readout chip RSIC 4 by only the first amplifier A 11 .

The second readout chip RSIC 2 may include a fourth amplifier A 21 , a fifth amplifier A 22 and a sixth amplifier A 23 . The second readout chip RSIC 2 may further include a fourth switch S 21 connected between the fourth amplifier A 21 and a fourth data line DL 21 , a fifth switch S 22 connected between the fifth amplifier A 22 and a fifth data line DL 22 and a sixth switch S 23 connected between the sixth amplifier A 23 and a sixth data line DL 23 .

In addition, the second readout chip RSIC 2 may further include channel connecting switches S 24 , S 25 and S 26 disposed at connecting paths between the fourth through sixth data lines DL 21 through DL 23 .

In addition, the second readout chip RSIC 2 may further include a second chip connecting switch S 27 disposed between the second chip connecting line CL 2 , which connects the second readout chip RSIC 2 and the third readout chip RSIC 3 , and at least one (e.g., DL 21 ) of the data lines.

The third readout chip RSIC 3 may include a seventh amplifier A 31 , an eighth amplifier A 32 and a ninth amplifier A 33 . The third readout chip RSIC 3 may further include a seventh switch S 31 connected between the seventh amplifier A 31 and a seventh data line DL 31 , an eighth switch S 32 connected between the eighth amplifier A 32 and an eighth data line DL 32 and a ninth switch S 33 connected between the ninth amplifier A 33 and a ninth data line DL 33 .

In addition, the third readout chip RSIC 3 may further include channel connecting switches S 34 , S 35 and S 36 disposed at connecting paths between the seventh through ninth data lines DL 31 through DL 33 .

In addition, the third readout chip RSIC 3 may further include a third chip connecting switch S 37 disposed between the third chip connecting line CL 3 , which connects the third readout chip RSIC 3 and the fourth readout chip RSIC 4 , and at least one (e.g., DL 31 ) of the data lines.

The fourth readout chip RSIC 4 may include a tenth amplifier A 41 , an eleventh amplifier A 42 and a twelfth amplifier A 43 . The fourth readout chip RSIC 4 may further include a tenth switch S 41 connected between the tenth amplifier A 41 and a tenth data line DL 41 , an eleventh switch S 42 connected between the eleventh amplifier A 42 and an eleventh data line DL 42 and a twelfth switch S 43 connected between the twelfth amplifier A 43 and a twelfth data line DL 43 .

In addition, the fourth readout chip RSIC 4 may further include channel connecting switches S 44 , S 45 and S 46 disposed at connecting paths between the tenth through twelfth data lines DL 41 through DL 43 .

In addition, the fourth readout chip RSIC 4 may further include a fourth chip connecting switch S 47 disposed between the third chip connecting line CL 3 and at least one (e.g., DL 41 ) of the data lines.

According to the present embodiment, the sensing data voltage is output using only one output amplifier A 11 in the plurality of readout chips RSIC 1 through RSIC 4 in the sensing mode so that the sensing error of the threshold voltage of the pixel P may be reduced.

Thus, display defects due to sensing errors of the threshold voltage of the pixel P may be prevented and the display quality of the display panel may be optimized.

FIG. 8 shows a circuit including readout chips of a display apparatus according to an embodiment of the present inventive concept.

The data driver and the display apparatus according to the present embodiment are substantially the same as the data driver and the display apparatus of the previous embodiment explained with reference to FIGS. 1 through 7 except that the sensing data voltage is output using only one output amplifier in each of the readout chips. Thus, the same reference numerals may be used to refer to the same or like parts as those described in the previous embodiment of FIGS. 1 through 7 and any repetitive explanation concerning the above elements may be omitted.

Referring to FIGS. 1 through 4 and 8 , the display apparatus 10 includes a display panel 100 and a display panel driver. The display panel driver includes a driving controller 200 , a gate driver 300 , a gamma reference voltage generator 400 and a data driver 500 .

The data driver 500 includes a plurality of amplifiers outputting the data voltages to the data lines. As shown in FIG. 8 , each of the readout chips RSIC 1 , RSIC 2 , RSIC 3 and RSIC 4 may include the amplifiers outputting the data voltages to the data lines.

In a writing mode, the amplifiers of the data driver 500 may output the data voltages to the corresponding data lines. In the writing mode, the amplifiers and the data lines may be matched one-to-one.

In contrast, in the sensing mode, a single amplifier of the data driver 500 may output the sensing data voltage to the plurality of data lines. In the sensing mode, the amplifier and the data lines may be matched one-to-many.

In the present embodiment, for example, the sensing data voltage is applied to all of the data lines in each of the readout chips RSIC 1 , RSIC 2 , RSIC 3 and RSIC 4 using a single amplifier A 11 , A 21 , A 31 and A 41 in each of the readout chips RSIC 1 , RSIC 2 , RSIC 3 and RSIC 4 .

Thus, the data driver of the present embodiment need not include the chip connecting lines CL 1 , CL 2 and CL 3 , which connect between the readout chips RSIC 1 , RSIC 2 , RSIC 3 and RSIC 4 , and the chip connecting switches S 17 , S 27 and S 37 connected to the chip connecting lines CL 1 , CL 2 and CL 3 which are shown in FIGS. 6 and 7 .

According to the present embodiment, the sensing data voltage is output using only one output amplifier (e.g., A 11 , A 21 , A 31 and A 41 ) per single readout chip (e.g., RSIC 1 , RSIC 2 , RSIC 3 and RSIC 4 ) in the sensing mode so that the sensing error of the threshold voltage of the pixel P may be reduced.

Thus, a display defect due to the sensing error of the threshold voltage of the pixel P may be prevented and the display quality of the display panel may be optimized.

FIG. 9 shows a circuit including readout chips of a display apparatus according to an embodiment of the present inventive concept.

The data driver and the display apparatus according to the present embodiment are substantially the same as the data driver and the display apparatus of the previous embodiment explained with reference to FIGS. 1 through 7 except that the first readout chip further includes a sensing amplifier and a sensing switch. Thus, the same reference numerals may be used to refer to the same or like parts as those described in the previous embodiment of FIGS. 1 through 7 and any repetitive explanation concerning the above elements may be omitted.

Referring to FIGS. 1 through 4 and 9 , the display apparatus 10 includes a display panel 100 and a display panel driver. The display panel driver includes a driving controller 200 , a gate driver 300 , a gamma reference voltage generator 400 and a data driver 500 .

The data driver 500 includes a plurality of amplifiers outputting the data voltages to the data lines. As shown in FIG. 9 , each of the readout chips RSIC 1 , RSIC 2 , RSIC 3 and RSIC 4 may include the amplifiers outputting the data voltages to the data lines.

In a writing mode, the amplifiers of the data driver 500 may output the data voltages to the corresponding data lines. In the writing mode, the amplifiers and the data lines may be matched one-to-one.

In contrast, in the sensing mode, a single amplifier A 0 of the data driver 500 may output the sensing data voltage to the plurality of data lines. In the sensing mode, the amplifier and the data lines may be matched one-to-many.

In the present embodiment, for example, the sensing data voltage is applied to all of the data lines corresponding to the four readout chips RSIC 1 , RSIC 2 , RSIC 3 and RSIC 4 using the single amplifier A 0 of the data driver 500 in the sensing mode.

Alternatively, for example, the sensing data voltage may be applied to all of the data lines corresponding to eight readout chips disposed at the first printed circuit P 1 and the second printed circuit P 2 in FIG. 2 using the single amplifier A 0 of the data driver 500 .

In the present embodiment, the first readout chip RSIC 1 may further include a sensing amplifier A 0 and a sensing switch S 0 connected to the sensing amplifier A 0 and at least one (e.g., DL 11 ) of the data lines.

In the writing mode, the first through third switches S 11 through S 13 may be turned on and the first through third channel connecting switches S 14 through S 16 and the sensing switch S 0 may be turned off.

In the sensing mode, the first through third switches S 11 through S 13 may be turned off and the first through third channel connecting switches S 14 through S 16 and the sensing switch S 0 may be turned on.

In the writing mode, the first readout chip RSIC 1 may output the data voltages using the first through third amplifiers A 11 through A 13 . In the sensing mode, the first readout chip RSIC 1 may output the sensing data voltage to all of the data lines of the first readout chip RSIC 1 using the sensing amplifier A 0 which is formed independently from the first through third amplifiers A 11 through A 13 .

In addition, the sensing data voltage of the sensing amplifier A 0 of the first readout chip RSIC 1 may be transmitted to the second readout chip RSIC 2 through the chip connecting switch S 17 and the first chip connecting line CL 1 .

Therefore, in the sensing mode, the sensing data voltage may be output to data lines DL 21 through DL 23 of the second readout chip RSIC 2 by only the sensing amplifier A 0 .

In the same way, in the sensing mode, the sensing data voltage may be output to data lines DL 31 through DL 33 of the third readout chip RSIC 3 and data lines DL 41 through DL 43 of the fourth readout chip RSIC 4 by only the sensing amplifier A 0 .

According to the present embodiment, the sensing data voltage is output using only one output amplifier A 0 in the plurality of readout chips RSIC 1 through RSIC 4 in the sensing mode so that the sensing error of the threshold voltage of the pixel P may be reduced.

Thus, the display defect due to the sensing error of the threshold voltage of the pixel P may be prevented and the display quality of the display panel may be optimized.

FIG. 10 shows a circuit diagram including readout chips of a display apparatus according to an embodiment of the present inventive concept.

The data driver and the display apparatus according to the present embodiment are substantially the same as the data driver and the display apparatus of the previous embodiment explained with reference to FIG. 9 except that the sensing data voltage is output using only one output amplifier in each of the readout chips. Thus, the same reference numerals may be used to refer to the same or like parts as those described in the previous embodiment of FIG. 9 and any repetitive explanation concerning the above elements may be omitted.

Referring to FIGS. 1 through 4 and 10 , the display apparatus 10 includes a display panel 100 and a display panel driver. The display panel driver includes a driving controller 200 , a gate driver 300 , a gamma reference voltage generator 400 and a data driver 500 .

The data driver 500 includes a plurality of amplifiers outputting the data voltages to the data lines. As shown in FIG. 10 , each of the readout chips RSIC 1 , RSIC 2 , RSIC 3 and RSIC 4 may include the amplifiers outputting the data voltages to the data lines.

In a writing mode, the amplifiers of the data driver 500 may output the data voltages to the corresponding data lines. In the writing mode, the amplifiers and the data lines may be matched one-to-one.

In contrast, in the sensing mode, a single amplifier of the data driver 500 may output the sensing data voltage to the plurality of data lines. In the sensing mode, the amplifier and the data lines may be matched one-to-many.

In the present embodiment, for example, each of the readout chips RSIC 1 , RSIC 2 , RSIC 3 and RSIC 4 may further include a sensing amplifier A 01 , A 02 , A 03 and A 04 and a sensing switch S 01 , S 02 , S 03 and S 04 connected to the sensing amplifier A 01 , A 02 , A 03 and A 04 and at least one (e.g., DL 11 , DL 21 , DL 31 and DL 41 ) of the data lines.

In the writing mode, the first through third switches S 11 through S 13 may be turned on and the first through third channel connecting switches S 14 through S 16 and the sensing switch S 01 may be turned off.

In the sensing mode, the first through third switches S 11 through S 13 may be turned off and the first through third channel connecting switches S 14 through S 16 and the sensing switch S 01 may be turned on.

In the writing mode, the first readout chip RSIC 1 may output the data voltages using the first through third amplifiers A 11 through A 13 . In the sensing mode, the first readout chip RSIC 1 may output the sensing data voltage to all of the data lines of the first readout chip RSIC 1 using the sensing amplifier A 01 which is formed independently from the first through third amplifiers A 11 through A 13 .

Similarly, in the sensing mode, the second through fourth readout chips RSIC 2 through RSIC 4 may output the sensing data voltage to all of the data lines of the second through fourth readout chips RSIC 2 through RSIC 4 using the sensing amplifiers A 02 , A 03 and A 04 which are formed independently from the data amplifiers.

According to the present embodiment, the sensing data voltage is output using only one output amplifier (e.g., A 01 , A 02 , A 03 and A 04 ) in each single readout chip (e.g., RSIC 1 , RSIC 2 , RSIC 3 and RSIC 4 ) in the sensing mode so that the sensing error of the threshold voltage of the pixel P may be reduced.

Thus, display defects due to the sensing error of the threshold voltage of the pixel P may be prevented and the display quality of the display panel may be optimized.

According to the present embodiment, the sensing error may be reduced so that the display quality of the display panel 100 may be optimized.

The foregoing is illustrative of the present inventive concept and is not to be construed as limiting thereof. Although some embodiments of the present inventive concept have been described, those of ordinary skill in the pertinent art will readily appreciate that many modifications are possible in the embodiments without materially departing from the teachings of the present inventive concept.

Accordingly, all such modifications are intended to be included within the scope of the present inventive concept as defined in the claims. In the claims, means-plus-function clauses are intended to cover the structures described herein as performing the recited function and not only structural equivalents but also equivalent structures. Therefore, it is to be understood that the foregoing is illustrative of the present inventive concept and is not to be construed as limited to the specific embodiments disclosed, and that modifications to the disclosed embodiments, as well as other embodiments, are intended to be included within the scope of the appended claims. The present inventive concept is defined by the following claims, with equivalents of the claims to be included therein.