Decision feedback equalizer

This application is a national phase entry of PCT Application No. PCT/JP2019/035680, filed on Sep. 11, 2019, which claims priority to Japanese Application No. 2018-178477, filed on Sep. 25, 2018, which applications are hereby incorporated herein by reference.

The present invention relates to a decision feedback equalizer that compensates an intersymbol interference caused by a dispersion property of a channel coupling a transmitter and a receiver.

A data communication system such as a local area network includes a transmitter (TX), a channel (transmission path), and a receiver (RX). The transmitter receives a data signal and transmits an analog signal. The analog signal transmitted from the transmitter is transmitted to the receiver through the channel. The receiver converts the analog signal (output signal from the channel) transmitted through the channel to a digital signal of “o” or “1” by comparing the analog signal with a reference voltage.

The analog signal (TX output) output from the transmitter includes serial symbol data divided by unit times (hereinafter, “UI”) depending on clock cycles (TX clock cycles) in the transmitter.

In a case where the time interval of the symbol data is a time interval for one UI in the TX output, the time interval of the symbol data is extended to a time interval for several UIs due to the dispersion property of the channel in the output signal from the channel, that is, the signal (RX input) input to the receiver. Because of the extension, some symbol data overlap. For that, a part of the last data (symbol data that are input last time) remaining in the current data (symbol data that are input this time) causes an intersymbol interference (ISI).

Thus, it is difficult for the receiver to perform proper determination on the current data, and an improper digital output may be generated in the receiver. Therefore, in order for the receiver to perform the proper determination, the intersymbol interference is required to be compensated.

For compensating the intersymbol interference, a decision feedback equalizer (DFE) is used at a frontend of the receiver. In the decision feedback equalizer, the intersymbol interference by the last data is removed from the current data through the use of a feedback signal depending on the amount of the intersymbol interference generated from the last data. Thus, the intersymbol interference is compensated, and the proper determination can be performed on the current data.

FIG. 5 shows a configuration of essential parts of a conventional decision feedback equalizer (DFE) 200 . The DFE 200 includes an adder 1 A, a flip-flop (F/F) 2 A, and a buffer 3 .

In the DFE 200 , the adder 1 A has an addition unit 11 and an xh block (feedback signal generation unit) 12 and receives, as an input signal IN, an analog signal (RX input) transmitted from a transmitter to a receiver through a channel and generates an adder output SO by adding (adding by inverting the symbol of) a feedback signal FB (analog signal) generated in the xh block to the input signal IN.

In the adder 1 A, the feedback signal FB to be given to the addition unit 11 has a value of +h or −h in order to remove the intersymbol interference. Here, h is a variable depending on the amount of the intersymbol interference (ISI) occurring in the input signal IN due to the last data. Because of the addition of the feedback signal FB to the input signal IN, the intersymbol interference is removed from the input signal IN, and the adder output SO becomes a signal not having an influence of the intersymbol interference.

The symbol of the value of h that the feedback signal FB has depends on an output (flip-flop output) DOUT of the flip-flop 2 A. The flip-flop 2 A has an amplifier (SA) 21 A and an SR latch (latch circuit) 22 and generates the flip-flop output DOUT for each sampling cycle of a clock signal CK by comparing the adder output SO from the adder 1 A with a reference voltage (VR). Normally, the sampling cycle of the clock signal CK is equal to the UI of the RX input.

The amplifier 21 A has a sampling block 21 - 1 , a latch block 21 - 2 , a reset block 21 - 3 , and addition units 21 - 4 and 21 - 5 . The amplifier 21 A generates an amplifier output SAO, and the amplifier output SAO is a return-to-zero (RZ) digital signal. The amplifier output SAO alternately has two states of a reset state (return-to-zero state) and a data state (“i” or “o”) in a time domain.

In the amplifier 21 A, when the clock signal CK has “Low”, the amplifier output SAO has the reset state. In this case, an input (latch block input) S 1 to be input to the latch block 21 - 2 and the amplifier output SAO are pre-charged by the reset block 21 - 3 so as to have a specific voltage (VDD).

When the clock signal CK is shifted to “High”, the sampling block 21 - 1 starts a sampling operation, and the reset block 21 - 3 cancels the pre-charging of the latch block input S 1 and the amplifier output SAO. Thus, the amplifier output SAO has a VDI. Here, the VDI is a voltage value in proportion to “SO−VR” (a difference between SO and VR) at the sampling time.

After that, the latch block 21 - 2 starts a latch operation and converts the analog signal having VDI to a digital signal (“1”/“0”) with a large voltage gain. After the latch operation, the amplifier output SAO is a digital signal. When the clock signal CK has “High”, the amplifier output SAO has the data state.

The subsequent SR latch 22 converts the amplifier output SAO (which is a return-to-zero (RZ) digital signal) to a non-return-to-zero (NRZ) digital signal by removing the reset state from the amplifier output SAO.

The output DOUT (flip-flop output DOUT) from the SR latch 22 is fed back to the adder 1 A through the buffer 3 as a feedback signal FBD (digital signal). In the adder 1 A, the feedback signal FBD (digital signal) is converted to a feedback signal FB (analog signal) depending on the amount of the intersymbol interference by the xh block 12 and is transmitted to the addition unit 11 .

FIG. 6 shows a timing chart indicating operations of the DFE 200 . In the DFE 200 , the adder 1 A generates an adder output SO(n) by adding an input signal IN(n) and a feedback signal FB (n−1) in the addition unit 11 .

The input signal IN(n) and the adder output SO(n) are the n-th data of the input signal IN and the n-th data of the adder output SO, respectively, and are data at the n-th sampling time of the clock signal CK. The feedback signal FB(n−1) is the (n−1)th feedback signal FB by the (n−1)th sampling of the clock signal CK.

When the flip-flop output DOUT(n−1) is “1”, the feedback signal FB(n−1) is +h. Therefore, the adder output SO is SO(n)=IN(n)−h. VR is normally 0. When the flip-flop output DOUT(n−1) is “0”, the feedback signal FB(n−1) is −h. Therefore, the adder output SO is SO(n)=IN(n)+h. Here, h is a variable depending on the amount of the intersymbol interference described above and is controlled in the xh block 12 .

Because of a gain (α) of the sampling block 21 - 1 , SAO(n) is a*{IN(n)±h}. In order to properly remove the intersymbol interference, the adder output SO(n) which is a result of addition of the input signal IN(n) and the feedback signal FB(n−1) is required to be settled before the n-th sampling of the clock signal CK.

Therefore, in a case where the time from the (n−1)th sampling of the clock signal CK to the settling of the value of the adder output SO(n) is a feedback loop delay T FB , the feedback loop delay T FB is required to be smaller than one UI.

In other words, in order to properly remove the intersymbol interference, a relationship T FB =T SAM +T LA +T SR +T BUF +T SUM <1 UI is required to be satisfied. Here, T SAM , T LA , T SR , T BUF , and T SUM are propagation delays in the sampling block 21 - 1 , the latch block 21 - 2 , the SR latch 22 , the buffer 3 , and the adder 1 A, respectively. Because of this requirement, the operational data rate of the receiver is limited.

Here, as a method for increasing the operational data rate of the receiver, that is, as a method for rapidly operating the receiver, reducing the feedback loop delay T FB may be considered. In order to realize that, two techniques are generally applied (see Non-Patent Literature 1, for example). FIG. 7 shows a configuration of essential pails of a DFE 201 applying the two techniques.

In the DFE 201 , according to a first technique, instead of the flip-flop output DOUT, the amplifier output SAO to the SR latch 22 is used as a feedback signal FBD through the buffer 3 . Also, in the DFE 201 , according to a second technique, an amplifier (adder-contained amplifier (SE_SA)) 21 B containing an adder 1 B is used.

In other words, in the DFE 201 , the adder 1 B having a combination of an addition unit 21 - 4 ′ and an xh block 21 - 6 is provided in an amplifier 21 B such that the xh block 21 - 6 transmits a feedback signal FB (analog signal) generated from the feedback signal FBD (digital signal) to the addition unit 21 - 4 ′.

In the DFE 201 , an operation for adding an output from the sampling block 21 - 1 and a feedback signal FB from the xh block 21 - 6 in the adder 1 B occurs during a sampling operation in the sampling block 21 - 1 .

Thus, the delay time T SUM in the adder 1 A shown in FIG. 5 is removed in addition to the propagation delay T SR in the SR latch 22 , and the feedback loop delay T FB is reduced to T SAM +T LA +T BUF . Therefore, the operational data rate of the receiver can be increased.

Non-Patent Literature

Non-Patent Literature 1: S.-J. Bae et al, “A 60 nm 6 Gb/s/pin GDDR5 Graphics DRAM with Multifaceted Clocking and ISI/SSN-Reduction Techniques,” in IEEE ISSCC Dig. Tech. Papers, February 2008, pp. 278-279.

Technical Problem

However, there is a problem that, when the operational data rate of the receiver is further increased, even the DFE 201 having a feedback loop delay T FB reduced by application of the two techniques is not enough, and it is difficult to compensate the intersymbol interference of a high speed signal.

Embodiments of the present invention are made to solve such a problem, and it is an object of embodiments of the present invention to realize a decision feedback equalizer that can further reduce the feedback loop delay T FB and compensate an intersymbol interference of a high speed signal.

Means for Solving the Problem

In order to achieve the object, a decision feedback equalizer ( 100 ) according to embodiments of the present invention that compensates an intersymbol interference (ISI) caused by a dispersion property of a channel coupling a transmitter (TX) and a receiver (RX) includes an amplifier ( 21 C) receiving, as an input signal (IN), an analog signal transmitted from the transmitter to the receiver through the channel, and amplifying and outputting the input signal as a return-to-zero digital signal (SAO), a latch circuit ( 22 ) latching and outputting the output from the amplifier as a non-return-to-zero digital signal (DOUT), and a buffer ( 3 ) provided on a path for feeding back the output from the amplifier to the amplifier. In this case, the amplifier includes a sampling block ( 21 - 1 ) sampling and outputting the input signal at predetermined cycles, a latch block ( 21 - 2 ) latching and outputting the output from the sampling block, an adder ( 1 C) having a feedback signal generation unit ( 21 - 7 ) generating a feedback signal (FB) depending on an amount of the intersymbol interference from the output (FBD) from the amplifier, which is fed back through the buffer, and an addition unit ( 21 - 5 ′) adding the feedback signal generated by the feedback signal generation unit to the output from the latch block, and a reset block ( 21 - 3 ) controlling input timing of the output from the sampling block to the latch block and input timing of the output from the latch block to the addition unit.

In embodiments of the present invention, the adder provided within the amplifier generates a feedback signal from an output from the amplifier, which is fed back through the buffer, adds and outputs the generated feedback signal and an output from the latch block as an output from the amplifier. In this case, the operation for adding the output from the latch block and the feedback signal in the adder occurs during a latch operation in the latch block. Thus, the delay time T SAM is removed, and the feedback loop delay T FB is reduced to T LA +T BUF .

Note that, in the description above, the constituent elements and the like in the figures corresponding to the constituent elements of embodiments of the present invention are indicated by reference signs within parentheses.

Effects of the Invention

As described above, according to embodiments of the present invention, because the operation for adding an output from the latch block and a feedback signal in the adder occurs during a latch operation in the latch block, the feedback loop delay T FB can be further reduced, and the intersymbol interference of a high speed signal can be compensated.

FIG. 1 is a diagram showing a configuration of essential parts of a decision feedback equalizer (DFE) according to Embodiment 1 of the present invention.

FIG. 2 is a diagram showing a specific circuit configuration of an amplifier (adder-contained amplifier) in the DFE shown in FIG. 1 .

FIG. 3 is a timing chart showing operations of the DFE using the amplifier shown in FIG. 2 .

FIG. 4 is a diagram showing a configuration of essential parts of a DFE having a ¼ rate architecture (DFE according to Embodiment 2).

FIG. 5 is a diagram showing a configuration of essential parts of a conventional DFE.

FIG. 6 is a timing chart showing operations of the DFE shown in FIG. 5 .

FIG. 7 is a diagram showing a configuration of essential parts of a conventional DFE using an adder-contained amplifier.

FIG. 8 is a diagram showing a specific circuit configuration of the amplifier in the DFE shown in FIG. 7 .

FIG. 9 is a timing chart showing operations of the DFE using the amplifier shown in FIG. 8 .

With reference to drawings, embodiments of the present invention will be described in detail below. FIG. 1 is a diagram showing essential parts of a decision feedback equalizer (DFE) 100 according to Embodiment 1 of the present invention. In FIG. 1 , the same reference signs are given to the same constituent elements as the constituent elements described with reference to FIG. 7 , and the description will be omitted.

In the DFE 100 , in order to further reduce the feedback loop delay TFB, the amplifier output SAO is used as the feedback signal FBD through the buffer 3 , and an amplifier (adder-contained amplifier (SE_SA)) having an adder 1 C between the latch block 21 - 2 and the SR latch 22 is used.

In other words, in the DFE 100 , the adder 1 C having a combination of an addition unit 21 - 5 ′ and an xh block 21 - 7 is provided within an amplifier 21 C, and the xh block 21 - 7 transmits a feedback signal FB (analog signal) generated from a feedback signal FBD (digital signal) to the addition unit 21 - 5 ′.

In the DFE 100 , a reset block 21 - 3 is controlled by a clock signal CK and resets output nodes of the sampling block 21 - 1 and the latch block 21 - 2 . In this case, while the clock signal CK is having “Low”, the output node of the sampling block 21 - 1 and the output node of the latch block 21 - 2 are pre-charged to VDD by the reset block 21 - 3 . While the clock signal CK is having “High”, the pre-charging to VDD of the output node of the sampling block 21 - 1 and the output node of the latch block 21 - 2 is cancelled, and the output from the sampling block 21 - 1 is transmitted to the latch block 21 - 2 , and the output from the latch block 21 - 2 is transmitted to the addition unit 21 - 5 ′. In other words, the reset block 21 - 3 controls input timing of the output from the sampling block 21 - 1 to the latch block 21 - 2 and input timing of the output from the latch block 21 - 2 to the addition unit 21 - 5 ′. The purpose of the reset block 21 - 3 is pre-charging for a sampling operation or a latch operation to be performed next, and the timing is determined by the clock signal CK.

In the DFE 100 , an operation for adding the output from the latch block 21 - 2 and the feedback signal FB from the xh block 21 - 7 occurs during the latch operation in the latch block 21 - 2 .

Thus, compared with the conventional DFE 201 shown in FIG. 7 , the delay time TSAM is removed, and the feedback loop delay TFB is reduced to TLA+TBUF. As a result, the operational data rate of the receiver can further be increased, and the intersymbol interference of a high speed signal can be compensated.

The amplifier 21 C in the DFE 100 will be described with reference to a specific circuit configuration thereof. Here, a specific circuit configuration of the amplifier 21 B in the conventional DFE 201 shown in FIG. 7 will be described first, and the specific circuit configuration of the amplifier 21 C in the DFE 100 of this embodiment will then be described.

FIG. 8 shows a specific circuit configuration of the amplifier 21 B in the conventional DFE 201 . This circuit is shown as a circuit in a case where the amplifier 21 B is differential.

In the circuit configuration, IN+ is one component of an input signal IN input as a differential signal, and IN− is the other component. S 1 + is one component of the latch block input S 1 occurring as a differential signal, and S 1 − is the other component. FBD+ is one component of the feedback signal FBD transmitted as a differential signal, and FBD− is the other component. SAO+ is one component of the amplifier output SAO output as a differential signal, and SAO− is the other component.

In the amplifier 21 B, the sampling block 21 - 1 includes an N-channel MOS transistor Mn 1 , an N-channel MOS transistor Mn 2 , and an N-channel MOS transistor Mn 3 . Here, the N-channel MOS transistor Mn 1 has a source connected to a ground line and a gate that receives input of a clock signal CK. The N-channel MOS transistor Mn 2 has a source connected to a drain of the N-channel MOS transistor Mn 1 and a gate that receives input of the input signal IN+. The N-channel MOS transistor Mn 3 has a source connected to the drain of the N-channel MOS transistor Mn 1 and a gate that receives input of the input signal IN−.

The latch block 21 - 2 includes a P-channel MOS transistor Mp 1 , a P-channel MOS transistor Mp 2 , an N-channel MOS transistor Mn 4 , and an N-channel MOS transistor Mn 5 . Here, the P-channel MOS transistor Mp 1 and the P-channel MOS transistor Mp 2 have sources connected to a power supply line. The N-channel MOS transistor Mn 4 has a drain connected to a drain of the P-channel MOS transistor Mp 1 , a gate connected to a gate of the P-channel MOS transistor Mp 1 , and a source connected to a drain of the N-channel MOS transistor Mn 2 . A drain, a gate and a source of the N-channel MOS transistor Mn 5 are connected in the way described below. The drain of the N-channel MOS transistor Mn 5 is connected to the drain of the P-channel MOS transistor Mp 2 and a connection point between the gate of the P-channel MOS transistor Mp 1 and the gate of the N-channel MOS transistor Mn 4 . The gate of the N-channel MOS transistor Mn 5 is connected to a gate of the P-channel MOS transistor Mp 2 and a connection point between the drain of the P-channel MOS transistor Mp 1 and the drain of the N-channel MOS transistor Mn 4 . The source of the N-channel MOS transistor Mn 5 is connected to a drain of the N-channel MOS transistor Mn 3 .

The reset block 21 - 3 includes a P-channel MOS transistor Mp 3 , a P-channel MOS transistor Mp 4 , a P-channel MOS transistor Mpg, and a P-channel MOS transistor Mph. Here, the P-channel MOS transistor Mp 3 has a source connected to the power supply line, a drain connected to a connection point between the drain of the P-channel MOS transistor Mp 1 and the drain of the N-channel MOS transistor Mn 4 , and a gate that receives input of a clock signal CK. The P-channel MOS transistor Mp 4 has a source connected to the power supply line, a drain connected to a connection point between the source of the N-channel MOS transistor Mn 4 and a drain of the N-channel MOS transistor Mn 2 , and a gate that receives input of a clock signal CK. The P-channel MOS transistor Mpg has a source connected to the power supply line, a drain connected to a connection point between the drain of the P-channel MOS transistor Mp 2 and the drain of the N-channel MOS transistor Mn 5 , and a gate that receives input of a clock signal CK. The P-channel MOS transistor Mp 6 has a source connected to the power supply line, a drain connected to a connection point between the source of the N-channel MOS transistor Mn 5 and the drain of the N-channel MOS transistor Mn 3 , and a gate that receives input of a clock signal CK.

The xh block 21 - 6 includes an N-channel MOS transistor Mn 6 , an N-channel MOS transistor Mn 7 , and an N-channel MOS transistor Mn 8 . Here, the N-channel MOS transistor Mn 6 has a source connected to the ground line and a gate that receives input of the clock signals CK. The N-channel MOS transistor Mn 7 has a source connected to a drain of the N-channel MOS transistor Mn 6 , a drain connected to a connection point between the source of the N-channel MOS transistor Mn 5 and the drain of the P-channel MOS transistor Mp 6 , and a gate that receives input of the feedback signal FBD+. The N-channel MOS transistor Mn 8 has a source connected to the drain of the N-channel MOS transistor Mn 6 , a drain connected to a connection point between the drain of the P-channel MOS transistor Mp 4 and the source of the N-channel MOS transistor Mn 4 , and a gate that receives input of the feedback signal FBD−.

FIG. 9 shows a timing chart indicating operations of the DFE 201 including the amplifier 21 B shown in FIG. 8 . In the DFE 201 including the amplifier 21 B, when the clock signal CK has “Low”, the nodes of S 1 +, S 1 −, SAO+ and SAO− are charged to VDD by the reset block 21 - 3 . When the clock signal CK is shifted to “High”, the sampling block 21 - 1 and the xh block 21 - 6 start pulling current from the two nodes of S 1 + and S 1 −.

At the two nodes of S 1 + and S 1 −, the current by the sampling block 21 - 1 is added to the current by the xh block 21 - 6 . The added current is transmitted to the two nodes of SAO+ and SAO−. As a result, in a sampling operation, SAO− depends on the current by IN+, and FBD− and SAO+ depend on current by IN− and FBD+.

After the sampling operation, VDI that is “SAO + −SAO − ” is α*{(IN + −IN − )−h*(FBD + −FBD − )}. Here, α is a gain of the sampling operation, and h is an intersymbol interference coefficient depending on the ratio between the current flowing in the N-channel MOS transistor Mn 1 and the current flowing in the N-channel MOS transistor Mn 6 . Because FBD+ and FBD − are digital signals of “1” or “0”, VDI is α*{(IN + −IN − )±h}. However, this is the same result as that of a case where the DFE 201 shown in FIG. 7 has a single-end architecture.

When SAO + or SAO − is lower than “VDD−V TH ”, the P-channel MOS transistors Mp 1 and Mp 2 are turned on, and the latch block 21 - 2 starts a latch operation. V TH is a threshold voltage of the P-channel MOS transistors Mp 1 and Mp 2 . After the latch operation, one of SAO+ and SAO is shifted to have V DD , and the other one is shifted to have V SS .

In the DFE 201 including the differential amplifier 21 B, in order to properly remove the intersymbol interference, FBD + and FBD − of the (n−1)th data are required to arrive before the n-th sampling of the clock signal CK. Therefore, the feedback loop delay T FB (T FB =T SAM +T LA +T BUF ) is required to be smaller than 1 UI.

FIG. 2 shows a specific circuit configuration of the amplifier 21 C in the DFE too ( FIG. 1 ) of this embodiment. This circuit is also shown as a circuit in a case where the amplifier 21 C is differential. FIG. 3 shows a timing chart corresponding to FIG. 9 .

In this circuit, instead of the xh block 21 - 6 in the conventional amplifier 21 B shown in FIG. 8 , an xh block 21 - 7 using P-channel MOS transistors Mp 7 to Mp 9 is used.

Because configurations of a sampling block 21 - 1 , a latch block 21 - 2 and a reset block 21 - 3 in this circuit are the same as the configurations of the sampling block 21 - 1 , the latch block 21 - 2 and the reset block 21 - 3 in the amplifier 21 B shown in FIG. 8 , the description will be omitted.

In the amplifier 21 C, the xh block 21 - 7 includes a P-channel MOS transistor Mp 7 , a P-channel MOS transistor Mp 8 , and a P-channel MOS transistor Mp 9 . Here, the P-channel MOS transistor Mp 7 has a source connected to a power supply line and a gate that receives input of a control voltage VB. A drain, a gate and a source of the P-channel MOS transistor Mp 8 are connected in the way described below. The source of the P-channel MOS transistor Mp 8 is connected to a drain of the P-channel MOS transistor Mp 7 . The drain of the P-channel MOS transistor Mp 8 is connected to a connection point between the gate of the P-channel MOS transistor Mp 1 and the gate of the N-channel MOS transistor Mn 4 and a connection point between the drain of the P-channel MOS transistor Mp 2 and the drain of the N-channel MOS transistor Mn 5 . The gate of the P-channel MOS transistor Mp 8 receives input of the feedback signal FBD+. A drain, a gate and a source of the P-channel MOS transistor Mp 9 are connected in the way described below. The source of the P-channel MOS transistor Mp 9 is connected to the drain of the P-channel MOS transistor Mp 7 . The drain of the P-channel MOS transistor Mp 9 is connected to a connection point between the drain of the P-channel MOS transistor Mp 1 and the drain of the N-channel MOS transistor Mn 4 and a connection point between the gate of the P-channel MOS transistor Mp 2 and the gate of the N-channel MOS transistor Mn 5 . The gate of the P-channel MOS transistor Mp 9 receives input of the feedback signal FB − .

In the amplifier 21 C, an offset voltage of −α*h*(FBD + −FBD − ) is added to the output from the latch block 21 - 2 by the xh block 21 - 7 . Because of this addition of the offset voltage, VDI is α*(IN + −IN − )−α*h*(FBD + −FBD − ). This exhibits the same result as that of the amplifier 21 B shown in FIG. 8 . α*h is controlled by a control voltage VB.

In the amplifier 21 C, because the offset voltage is added to the output from the latch block 21 - 2 , the arrival time of the feedback signal (FBD + , FBD − ) is alleviated to the starting time of a latch operation. In other words, in order to properly remove the intersymbol interference, FBD + and FBD − of the (n−1)th data are required to arrive before the latch operation of the n-th data.

Because the feedback loop includes a latch operation in the amplifier 21 C and a buffer operation in the buffer 3 , the feedback loop delay T FB is T LA +T BUF . In this amplifier 21 C, T FB is smaller than that of the conventional amplifier 21 B, providing an effect that the operational data rate of the DFE 100 is further increased.

The DFE 100 shown in FIG. 1 can be implemented as a ¼ rate architecture. FIG. 4 shows a configuration of essential parts of a DFE 101 having a ¼ rate architecture. The DFE 101 includes four slices SL 1 to SL 4 where one slice includes a combination of the amplifier 21 C, the SR latch 22 and the buffer 3 shown in FIG. 1 .

The first slice SL 1 includes an amplifier 21 C 1 , an SR latch 22 1 , and a buffer 3 1 . The second slice SL 2 includes an amplifier 21 C 2 , an SR latch 22 2 , and a buffer 3 2 . The third slice SL 3 includes an amplifier 21 C 3 , an SR latch 22 3 , and a buffer 3 3 . The fourth slice SL 4 includes an amplifier 21 C 4 , an SR latch 22 4 , and a buffer 3 4 .

In the DFE 101 , the xh block 21 - 7 within the amplifier 21 C 1 in the first slice SL 1 generates a feedback signal FB from an output from the amplifier 21 C 4 in the final (fourth) slice SL 4 , which is fed back through the buffer 3 4 in the final (fourth) slice SL 4 , instead of an output from the amplifier 21 C 1 , which is fed back through the buffer 3 1 in the first slice SL 1 .

The amplifier 21 C 2 in the second slice SL 2 generates a feedback signal FB from an output from the amplifier 21 C 1 in the preceding slice SL 1 , which is fed back through the buffer 3 1 in the preceding slice SL 1 , instead of an output from the amplifier 21 C 2 in the second slice SL 2 , which is fed back through the buffer 3 2 in the second slice SL 2 .

The amplifier 21 C 3 in the third slice SL 3 generates a feedback signal FB from an output from the amplifier 21 C 2 in the preceding slice SL 2 , which is fed back through the buffer 3 2 in the preceding slice SL 2 , instead of an output from the amplifier 21 C 3 in the third slice SL 3 , which is fed back through the buffer 3 3 in the third slice SL 3 .

The amplifier 21 C 4 in the fourth slice SL 4 generates a feedback signal FB from an output from the amplifier 21 C 3 in the preceding slice SL 3 , which is fed back through the buffer 3 3 in the preceding slice SL 3 , instead of an output from the amplifier 21 C 4 in the fourth slice SL 4 , which is fed back through the buffer 3 4 in the fourth slice SL 4 .

In this DFE 101 , the amplifiers 21 C 1 , 21 C 2 , 21 C 3 and 21 C 4 are synchronized by a clock signal CK 0 , a clock signal CK 90 , a clock signal CK 180 and a clock signal CK 270 , respectively. In this example, it is assumed that the amplifiers 21 C 1 , 21 C 2 , 21 C 3 and 21 C 4 have the circuit configuration shown in FIG. 2 .

The clock signals CK 0 , CK 90 , CK 180 and CK 270 have a cycle of 4×UI where UI is the same as the RX input. Sampling operations are sequentially performed in the amplifiers 21 C 1 , 21 C 2 , 21 C 3 and 21 C 4 in order of the clock signal CK 0 , the clock signal CK 90 , the clock signal CK 180 , and the clock signal CK 270 . The amplifier 21 C 2 starts a sampling operation by using the clock signal CK 90 after one UI from the sampling by the clock signal CK 0 in the amplifier 21 C 1 .

After the next one UI, the amplifier 21 C 3 starts a sampling operation by using the clock signal CK 180 . After the further next one UI, the amplifier 21 C 4 starts a sampling operation. Then, after the further next one UI, the amplifier 21 C 1 starts a sampling operation again. The sampling operations are repeated in the order described above.

For a DFE operation, an amplifier output SAO 0 that is an output from the amplifier 21 C 1 synchronized by the clock signal CK 0 is transmitted to the amplifier 21 C 2 as FBD 0 through the buffer 3 1 . An amplifier output SAO 90 that is an output from the amplifier 21 C 2 synchronized by the clock signal CK 90 is transmitted to the amplifier 21 C 3 as FBD 90 through the buffer 3 2 . An amplifier output SAO 180 that is an output from the amplifier 21 C 3 synchronized by the clock signal CK 180 is transmitted to the amplifier 21 C 4 as FBD 180 through the buffer 3 3 . An amplifier output SAO 270 that is an output from the amplifier 21 C 4 synchronized by the clock signal CK 270 is transmitted to the amplifier 21 C 1 as FBD 270 through the buffer 3 4 .

Expansion of the Embodiments

Having described the present invention with reference to the embodiments, the present invention is not limited to the embodiments. Various changes that can be understood by those skilled in the art without departing from the technical spirit of the present invention can be made to the configuration and details of the present invention.

1 C Adder

2 C Flip-flop

3 , 31 to 34 Buffer

21 C, 21 C 1 to 21 C 4 Amplifier (adder-contained amplifier)

21 - 1 Sampling block

21 - 2 Latch block

21 - 3 Reset block

21 - 4 Addition unit

21 - 5 ′ Addition unit

21 - 7 xh block

22 , 221 to 224 SR latch

Mp 1 to Mp 9 P-channel MOS transistor

Mn 1 to Mn 5 N-channel MOS transistor

SL 1 to SL 4 Slice

100 , 101 DFE

22 , 221 to 224 SR latch

Mp 1 to Mp 9 P-channel MOS transistor

Mn 1 to Mn 5 N-channel MOS transistor

SL 1 to SL 4 Slice

100 , 101 DFE.