Pixel circuit and method for driving the same, and display panel

This Application is a Section 371 National Stage Application of International Application No. PCT/CN2020/103554, filed on Jul. 22, 2020, which published as WO 2021/027514 A1 on Feb. 18, 2021, not in English, and claims priority to Chinese Patent Application No. 201910752533.8, filed on Aug. 14, 2019, the disclosures of which are incorporated herein by reference in their entireties.

The present disclosure relates to a field of display technology, and in particular to a pixel circuit and a method for driving the pixel circuit, and a display panel.

In a conventional organic light-emitting diode (OLED) display, sub-pixels of different colors in each pixel unit are arranged laterally on a panel, which occupy a large space of the panel.

According to a first aspect of the present disclosure, a pixel circuit is provided, including: a driving sub-circuit electrically coupled to a first node, a first power signal terminal and a second node, and configured to transmit a first power voltage at the first power signal terminal to the second node under control of a voltage at the first node; and a light-emitting control sub-circuit electrically coupled to the second node, a second power signal terminal, a first light-emitting control terminal, a second light-emitting control terminal, a third light-emitting control terminal, a first electrode of a first light-emitting element, a second electrode of the first light-emitting element, a first electrode of a second light-emitting element, a second electrode of the second light-emitting element, a first electrode of a third light-emitting element and a second electrode of the third light-emitting element, and configured to: transmit a voltage at the second node and a second power voltage at the second power signal terminal to the first electrode of the first light-emitting element and the second electrode of the first light-emitting element respectively in a first period, transmit a voltage at the second node and a second power voltage at the second power signal terminal to the first electrode of the second light-emitting element and the second electrode of the second light-emitting element respectively in a second period, and transmit a voltage at the second node and a second power voltage at the second power signal terminal to the first electrode of the third light-emitting element and the second electrode of the third light-emitting element respectively in a third period, under control of a first light-emitting control signal from the first light-emitting control terminal, a second light-emitting control signal from the second light-emitting control terminal, and a third light-emitting control signal from the third light-emitting control terminal.

In some embodiments, the light-emitting control sub-circuit includes: a first transistor having a control electrode electrically coupled to the second light-emitting control terminal, a first electrode electrically coupled to the second node, and a second electrode electrically coupled to a fourth node; a second transistor having a control electrode electrically coupled to the first light-emitting control terminal, a first electrode electrically coupled to the second node, and a second electrode electrically coupled to the first electrode of the first light-emitting element; a third transistor having a control electrode electrically coupled to the third light-emitting control terminal, a first electrode electrically coupled to the second node, and a second electrode electrically coupled to a fifth node; a fourth transistor having a control electrode electrically coupled to the first light-emitting control terminal, a first electrode electrically coupled to the fourth node, and a second electrode electrically coupled to the second power signal terminal; and a fifth transistor having a control electrode electrically coupled to the second light-emitting control terminal, a first electrode electrically coupled to the fifth node, and a second electrode electrically coupled to the second power signal terminal, wherein the second electrode of the first light-emitting element is electrically coupled to the first electrode of the second light-emitting element via the fourth node, the second electrode of the second light-emitting element is electrically coupled to the first electrode of the third light-emitting element via the fifth node, and the second electrode of the third light-emitting element is electrically coupled to the second power signal terminal.

In some embodiments, the light-emitting control sub-circuit includes: a first transistor having a control electrode electrically coupled to the second light-emitting control terminal, a first electrode electrically coupled to the second node, and a second electrode electrically coupled to a fourth node; a second transistor having a control electrode electrically coupled to the third light-emitting control terminal, a first electrode electrically coupled to the second electrode of the third light-emitting element, and a second electrode electrically coupled to the second power signal terminal; a third transistor having a control electrode electrically coupled to the third light-emitting control terminal, a first electrode electrically coupled to the second node, and a second electrode electrically coupled to a fifth node; a fourth transistor having a control electrode electrically coupled to the first light-emitting control terminal, a first electrode electrically coupled to the fourth node, and a second electrode electrically coupled to the second power signal terminal; and a fifth transistor having a control electrode electrically coupled to the second light-emitting control terminal, a first electrode electrically coupled to the fifth node, and a second electrode electrically coupled to the second power signal terminal, wherein the first electrode of the first light-emitting element is electrically coupled to the second node, the second electrode of the first light-emitting element is electrically coupled to the first electrode of the second light-emitting element via the fourth node, and the second electrode of the second light-emitting element is electrically coupled to the first electrode of the third light-emitting element via the fifth node.

In some embodiments, the driving sub-circuit includes a sixth transistor having a control electrode electrically coupled to the first node, a first electrode electrically coupled to the first power signal terminal, and a second electrode electrically coupled to the second node.

In some embodiments, the pixel circuit further includes: a storage sub-circuit electrically coupled between the first node and the third node; a charging control sub-circuit electrically coupled to a scan signal terminal, a data signal terminal, the first node, the second node and the third node, and configured to generate a voltage difference between the first node and the third node under control of a first scan voltage at the scan signal terminal; and a reset sub-circuit electrically coupled to a first reset control terminal, a second reset control terminal, the third node and a reset voltage signal terminal, and configured to, under control of a first reset control signal from the first reset control terminal or a second reset control signal from the second reset control terminal, reset the third node by using a reset voltage signal from the reset voltage signal terminal.

In some embodiments, the storage sub-circuit includes a first capacitor having a first terminal electrically coupled to the third node, and a second terminal electrically coupled to the first node.

In some embodiments, the charging control sub-circuit includes: a seventh transistor having a control electrode electrically coupled to the scan signal terminal, a first electrode electrically coupled to the data signal terminal, and a second electrode electrically coupled to the third node; and an eighth transistor having a control electrode electrically coupled to the scan signal terminal, a first electrode electrically coupled to the first node, and a second electrode electrically coupled to the second node.

In some embodiments, the reset sub-circuit includes: a ninth transistor having a control electrode electrically coupled to the first reset control terminal, a first electrode electrically coupled to the reset voltage signal terminal, and a second electrode electrically coupled to the third node; and a tenth transistor having a control electrode electrically coupled to the second reset control terminal, a first electrode electrically coupled to the reset voltage signal terminal, and a second electrode electrically coupled to the third node.

In some embodiments, the scan signal terminal is configured to receive a scan signal for a current row of pixels, the first reset control terminal is configured to receive a scan signal for a previous row of pixels, and the second reset control terminal is configured to receive a scan signal for a next row of pixels.

According to a second aspect of the present disclosure, a display panel including a plurality of pixel units is provided, wherein at least one pixel unit of the plurality of pixel units includes the pixel circuit described above

In some embodiments, each of the at least one pixel unit includes: a substrate; a control circuit layer arranged on the substrate, wherein the control circuit layer includes the driving sub-circuit and the light-emitting control sub-circuit; an intermediate layer arranged on a side of the control circuit layer away from the substrate, and configured to cover the control circuit layer; a first electrode layer, a first light-emitting layer, a second electrode layer, a second light-emitting layer, a third electrode layer, a third light-emitting layer and a fourth electrode layer sequentially stacked on the intermediate layer, wherein the first light-emitting layer, the second light-emitting layer and the third light-emitting layer are used as a first light-emitting element, a second light-emitting element and a third light-emitting element respectively.

In some embodiments, the substrate includes a first area and a second area that do not overlap each other; projections of at least a part of the driving sub-circuit and at least a part of the light-emitting control sub-circuit on the substrate are located in the first area; and projections of at least a part of the first electrode layer, the first light-emitting layer, at least a part of the second electrode layer, the second light-emitting layer, at least a part of the third electrode layer, the third light-emitting layer and at least a part of the fourth electrode layer on the substrate are located in the second area.

In some embodiments, each of the first electrode layer, the second electrode layer and the third electrode layer is electrically coupled to the light-emitting control sub-circuit through a through hole penetrating the intermediate layer.

In some embodiments, the first electrode layer comprises an opaque material, and the second electrode layer, the third electrode layer and the fourth electrode layer each comprises a transparent material.

According to a third aspect of the present disclosure, a method for driving the pixel circuit described above is provided, wherein each of the first period, the second period and the third period includes an initialization phase, a charging phase and a light-emitting phase, and the method comprises: providing a first light-emitting control signal being at a second level and providing a second light-emitting control signal and a third light-emitting control signal each being at a first level in the light-emitting phase of the first period; providing a second light-emitting control signal being at a second level and providing a first light-emitting control signal and a third light-emitting control signal each being at a first level in the light-emitting phase of the second period; providing a third light-emitting control signal being at a second level and providing a first light-emitting control signal and a second light-emitting control signal each being at a first level in the light-emitting phase of the third period; and providing a first light-emitting control signal, a second light-emitting control signal and a third light-emitting control signal each being at a first level in the initialization phase and the charging phase of each of the first period, the second period and the third period.

According to a fourth aspect of the present disclosure, a display panel including a plurality of pixel units is provided, wherein each of the plurality of pixel units includes: a substrate; a control circuit layer arranged on the substrate; an intermediate layer arranged on a side of the control circuit layer away from the substrate; a first electrode layer, a first light-emitting layer, a second electrode layer, a second light-emitting layer, a third electrode layer, a third light-emitting layer and a fourth electrode layer sequentially stacked on the intermediate layer, wherein the first light-emitting layer, the second light-emitting layer and the third light-emitting layer are used as a first light-emitting element, a second light-emitting element and a third light-emitting element, respectively.

In some embodiments, the substrate includes a first area and a second area that do not overlap each other; and projections of at least a part of the first electrode layer, the first light-emitting layer, at least a part of the second electrode layer, the second light-emitting layer, at least a part of the third electrode layer, the third light-emitting layer and at least a part of the fourth electrode layer on the substrate are located in the second area.

In some embodiments, each of the first electrode layer, the second electrode layer and the third electrode layer is electrically coupled to the control circuit layer through a through hole penetrating the intermediate layer.

In some embodiments, the first electrode layer comprises an opaque material, and the second electrode layer, the third electrode layer and the fourth electrode layer each comprises a transparent material.

In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or in the related art, the accompanying drawings required in the description of the embodiments are briefly introduced below. Obviously, the accompanying drawings in the following description are some embodiments of the present disclosure. For those ordinary skilled in the art, other accompanying drawings may be obtained from these accompanying drawings without carrying out any inventive effort.

FIG. 1 shows a schematic cross-sectional view of a pixel unit of a display panel according to the related art.

FIG. 2A shows a schematic cross-sectional view of a pixel unit of a display panel according to the embodiments of the present disclosure.

FIG. 2B shows a schematic cross-sectional view of another pixel unit of a display panel according to the embodiments of the present disclosure.

FIG. 3 shows a more detailed layer-structure diagram of a pixel unit according to the embodiments of the present disclosure.

FIG. 4 shows a circuit structure diagram of a pixel circuit in a pixel unit according to the embodiments of the present disclosure.

FIG. 5 shows a further circuit structure diagram of the pixel circuit in FIG. 4 .

FIG. 6 shows a detailed circuit diagram of the pixel circuit shown in FIG. 5 .

FIG. 7A shows a signal timing diagram of the pixel circuit shown in FIG. 6 .

FIGS. 7B-7F show schematic diagrams of the principle in each phase in the pixel circuit shown in FIG. 6 .

FIG. 8 shows another detailed circuit diagram of the pixel circuit shown in FIG. 5 .

FIG. 9 shows a schematic block diagram of a display panel according to the embodiments of the present disclosure.

FIG. 10 shows a flowchart of a method for driving a pixel circuit according to the embodiments of the present disclosure.

In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the technical solutions of the present disclosure are clearly and completely described below with reference to the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are only a part but not all of the embodiments of the present disclosure. Based on the described embodiments of the present disclosure, all other embodiments obtained by those ordinary skilled in the art without carrying out inventive effort fall within the protection scope of the present disclosure. It should be noted that throughout the accompanying drawings, the same elements are represented by the same or similar reference signs. In the following description, some specific embodiments are only used for descriptive purposes, and should not be construed as limiting the present disclosure. They are merely examples of the embodiments of the present disclosure. When it may cause confusion in the understanding of the present disclosure, conventional structures or configurations will be omitted. It should be noted that the shape and size of each component in the figure do not reflect the actual size and ratio, but merely illustrate the content of the embodiments of the present disclosure.

Unless otherwise defined, the technical or scientific terms used in the embodiments of the present disclosure should have the usual meanings understood by those skilled in the art. The words “first,” “second,” and the like used in the embodiments of the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different composition parts.

In addition, in the description of the embodiments of the present disclosure, the term “electrically coupled” may mean that two components are electrically coupled directly, or that two components are electrically coupled via one or more other components. In addition, these two components may be electrically coupled or coupled by wired or wireless means.

In the following embodiments, the specific type of display is not limited, but those skilled in the art should understand that any display that emits light by providing a light-emitting layer and applying a voltage across the light-emitting layer (for example, OLED display, quantum dot light-emitting diode (QLED) display) is covered by the present disclosure.

Transistors used in the embodiments of the present disclosure may all be thin film transistors (TFT) or field effect transistors or other devices with the same characteristics. According to the functions in the circuit, the transistors used in the embodiments of the present disclosure are mainly switching transistors. Since source and drain electrodes of the thin film transistor used here are symmetrical, the source and drain electrodes may be interchanged. In the embodiments of the present disclosure, one of the source electrode and the drain electrode is called a first electrode, and the other is called a second electrode. In the following examples, the driving transistor is described as a P-type thin film transistor, and other transistors are of the same or different type as the driving transistor according to circuit designs. Similarly, in other embodiments, the driving transistor may also be shown as an N-type thin film transistor. Those skilled in the art may understand that by correspondingly changing the types of other transistors and inverting the driving signals and level signals (and/or making other additional adaptive modifications), the technical solutions of the present disclosure may also be implemented.

In addition, in the description of the embodiments of the present disclosure, the terms “first level” and “second level” are only used to distinguish an amplitude difference between the two levels. In some embodiments, the “first level” may be an invalid level that turns off the relevant transistor, and the “second level” may be a valid level that turns on the relevant transistor. Hereinafter, since the driving transistor is exemplified as a P-type thin film transistor, the “first level” is exemplified as a high level, and the “second level” is exemplified as a low level.

The present disclosure will be described in detail below with reference to the accompanying drawings.

FIG. 1 shows a schematic cross-sectional view of a pixel unit 100 of a display panel according to the related art.

The display panel includes a plurality of pixel units 100 . As shown in FIG. 1 , the pixel unit 100 includes a substrate 110 , a control circuit layer 120 , a first electrode layer 130 , a light-emitting layer 140 , and a second electrode layer 150 .

The substrate 110 may be, for example, a glass substrate.

Pixel circuits are formed in the control circuit layer 120 . For example, the control circuit layer 120 may include a plurality of pixel circuits configured to control different light-emitting elements (sub-pixels).

The first electrode layer 130 is arranged on a side of the control circuit layer 120 away from the substrate 110 . The first electrode layer 130 may include a plurality of driving electrodes coupled to different pixel circuits in the control circuit layer 120 , respectively, so as to receive, from the respective pixel circuits, driving voltages for driving different light-emitting elements in the light-emitting layer 140 . A part of the first electrode layer 130 is arranged in a light-emitting area in the pixel unit 100 , and the first electrode layer 130 may include an opaque material (for example, Al and Ag).

In some embodiments, one or more intermediate layers may be further provided. The intermediate layer may be located between the control circuit layer 120 and the first electrode layer 130 , or may surround the first electrode layer 130 outside the light-emitting area. The first electrode layer 130 is electrically coupled to the pixel circuit in the control circuit layer 120 through a through hole penetrating the one or more intermediate layers. The intermediate layer may include an interlayer dielectric layer (ILD) and various flat layers, insulating layers or organic layers.

The light-emitting layer 140 includes three portions arranged side by side. The three portions correspond to a red light-emitting element (R), a green light-emitting element (G) and a blue light-emitting element (B) in the pixel unit 100 , respectively, so as to emit red, green and blue light. As described above, each light-emitting element corresponds to one pixel circuit in the control circuit layer 120 and one electrode in the first electrode layer 130 , so as to receive a driving voltage from a corresponding pixel circuit through a corresponding electrode. The light-emitting layer 140 is used as the light-emitting elements in the pixel circuit.

The second electrode layer 150 may include a common electrode, and each light-emitting element of each pixel unit on the panel may share a same electrode. The common electrode may be a transparent electrode (for example, may be made of indium tin oxide (ITO)).

In the pixel structure of FIG. 1 , light-emitting elements of different colors are arranged laterally on the panel, which occupy a large space of the panel and are not conducive to the realization of high PPI.

FIG. 2A shows a schematic cross-sectional view of a pixel unit 200 of a display panel according to the embodiments of the present disclosure.

As shown in FIG. 2A , the pixel unit 200 includes a substrate 210 , a control circuit layer 220 , a first electrode layer 230 , a first light-emitting layer 240 , a second electrode layer 250 , a second light-emitting layer 260 , a third electrode layer 270 , a third light-emitting layer 280 and a fourth electrode layer 290 .

The substrate 210 may be, for example, a glass substrate.

Pixel circuits are formed in the control circuit layer 220 . For example, a single pixel circuit may be formed in the control circuit layer 220 . The single pixel circuit is configured to control the light-emitting layers in the pixel unit 200 to emit light in different periods.

The first electrode layer 230 is arranged on a side of the control circuit layer 220 away from the substrate 210 . The first electrode layer 230 may include a single driving electrode, which is electrically coupled to the pixel circuit in the control circuit layer 220 , so as to receive a driving voltage for driving the first light-emitting layer 240 from the pixel circuit in a first period of a frame time. A part of the first electrode layer 230 is arranged in a light-emitting area of the pixel unit 200 , and the driving electrode may include an opaque material (for example, Al and Ag).

In some embodiments, as shown in FIG. 2B , one or more intermediate layers 225 may be further provided. The intermediate layer 225 may be provided between the control circuit layer 220 and the first electrode layer 230 , or may surround the first electrode layer 230 and a layer structure thereon outside the light-emitting area. The first electrode layer 230 is electrically coupled to the pixel circuit in the control circuit layer 220 through a through hole penetrating the intermediate layer. The intermediate layer may include an interlayer dielectric layer (ILD) and various flat layers, insulating layers or organic layers.

The first light-emitting layer 240 includes a single portion corresponding to a red light-emitting element (R) in the pixel unit 200 to emit red light. The first light-emitting layer 240 receives a driving voltage from the pixel circuit in the control circuit layer 220 through a driving electrode in the first electrode layer 230 .

The second electrode layer 250 is arranged on a side of the first light-emitting layer 240 away from the substrate 210 . The second electrode layer 250 may include a single electrode, which is electrically coupled to the pixel circuit in the control circuit layer 220 , so as to receive a common voltage in the first period of a frame time, and to receive, from the pixel circuit, a driving voltage for driving the second light-emitting layer 260 to emit light in the second period of a frame time. The driving electrode in the second electrode layer 250 may be a transparent electrode. In order to achieve electrical coupling between the second electrode layer 250 and the pixel circuit in the control circuit layer 220 , a through hole is provided in the intermediate layer.

The second light-emitting layer 260 includes a single portion corresponding to a green light-emitting element (G) in the pixel unit 200 to emit green light. The second light-emitting layer 260 receives a driving voltage from the pixel circuit in the control circuit layer 220 through a driving electrode in the second electrode layer 250 .

The third electrode layer 270 is arranged on a side of the second light-emitting layer 260 away from the substrate 210 . The third electrode layer 270 may include a single electrode, which is electrically coupled to the pixel circuit in the control circuit layer 220 , so as to receive the common voltage in the second period of a frame time, and to receive, from the pixel circuit, the driving voltage for driving the third light-emitting layer 280 to emit light in the third period of a frame time. The driving electrode in the third electrode layer 270 may be a transparent electrode. In order to achieve electrical coupling between the third electrode layer 270 and the pixel circuit in the control circuit layer 220 , a through hole is provided in the intermediate layer.

The third light-emitting layer 280 includes a single portion corresponding to the blue light-emitting element (G) in the pixel unit 200 to emit blue light. The third light-emitting layer 280 receives a driving voltage from the pixel circuit in the control circuit layer 220 through a driving electrode in the third electrode layer 270 .

The fourth electrode layer 290 is arranged on a side of the third light-emitting layer 280 away from the substrate 210 . The fourth electrode layer 290 may include a single electrode, which is electrically coupled to the pixel circuit in the control circuit layer 220 to receive the common voltage in a third period of a frame time. The driving electrode in the fourth electrode layer 290 may be a transparent electrode. In order to achieve electrical coupling between the fourth electrode layer 290 and the pixel circuit in the control circuit layer 220 , a through hole is provided in the intermediate layer.

FIG. 3 shows a more detailed layer-structure diagram of a pixel unit according to the embodiments of the present disclosure.

As shown in FIG. 3 , the pixel unit 300 includes a substrate 310 , a buffer layer 320 , a control circuit layer 330 , a first intermediate layer 340 , a second intermediate layer 350 , a third intermediate layer 360 , a first electrode layer 370 , a first light-emitting layer 371 , a second electrode layer 372 , a second light-emitting layer 373 , a third electrode layer 374 , a third light-emitting layer 375 , and a fourth electrode layer 376 stacked in sequence. The first light-emitting layer 371 , the second light-emitting layer 373 and the third light-emitting layer 375 are located in the light-emitting area of the pixel unit. Parts of the first electrode layer 370 , the second electrode layer 372 , the third electrode layer 374 and the fourth electrode layer 376 are located in the light-emitting area, and the other parts of the first electrode layer 370 , the second electrode layer 372 , the third electrode layer 374 and the fourth electrode layer 376 are located in a TFT area, so as to facilitate electrical coupling to the pixel circuit or a common power line. It should be understood that in other embodiments, some layers (for example, the buffer layer 320 ) in the structure shown in FIG. 3 may be removed or new layers may be added, and structures of some layers may be changed, which is not limited in the present disclosure.

Exemplarily, the substrate 310 in FIG. 3 includes a TFT area (a first area) and a light-emitting area (a second area) that do not overlap each other.

Exemplarily, the first intermediate layer 340 and the second intermediate layer 350 in FIG. 3 are arranged between the control circuit layer 330 and the first electrode layer 370 , and the third intermediate layer 360 surrounds the first electrode layer 370 outside the light-emitting area.

Exemplarily, the control circuit layer 330 in FIG. 3 includes two transistors M 1 and M 2 in the pixel circuit. One of source electrode and drain electrode of the transistor M 1 is electrically coupled to the first electrode layer 370 through a through hole V 1 , and a portion of the first electrode layer 370 is formed in the through hole V 1 . The transistor M 2 is electrically coupled to the second electrode layer 372 through a through hole V 2 , and the second electrode layer 372 is electrically coupled to an electrical coupling layer 3721 provided in the through hole V 2 . The electrical coupling layer 3721 is arranged in a same layer as the first electrode layer 370 and is made of a material different from that of the second electrode layer 372 . The third electrode layer 374 is also electrically coupled to a transistor in the pixel circuit. FIG. 3 takes a part of a specific cross-sectional view of the pixel unit, and the transistor coupled to the third electrode layer 374 is not shown.

As shown in the schematic diagrams of FIGS. 2A-2B and the schematic layer structure diagram of FIG. 3 , by sequentially stacking three light-emitting elements in a vertical direction in an area where a single light-emitting element is originally provided, and by driving the three light-emitting elements separately by using the pixel circuit originally used to drive the single light-emitting element, a space of the panel occupied by each pixel unit is saved, which is more conducive to the realization of high PPI.

In order to realize a normal display of the display panel, it is necessary to design the pixel circuit and the signal timing so that the three light-emitting elements emit light in different periods, and each light-emitting element may not be affected by the driving of the other light-emitting elements.

FIG. 4 shows a circuit structure diagram of a pixel circuit 400 in a pixel unit according to the embodiments of the present disclosure.

As shown in FIG. 4 , the pixel circuit 400 includes a driving sub-circuit 410 , a light-emitting control sub-circuit 420 , a first light-emitting element R, a second light-emitting element G, and a third light-emitting element B.

The driving sub-circuit 410 is electrically coupled to a first node N 1 , a first power signal terminal VDD and a second node N 2 . The driving sub-circuit 410 is configured to transmit a first power voltage at the first power signal terminal VDD to the second node N 2 under control of a voltage at the first node N 1 .

The light-emitting control sub-circuit 420 is electrically coupled to the second node N 2 , a second power signal terminal VSS, a first light-emitting control terminal EM 1 , a second light-emitting control terminal EM 2 , a third light-emitting control terminal EM 3 , a first electrode of the first light-emitting element R, a second electrode of the first light-emitting element R, a first electrode of the second light-emitting element G, a second electrode of the second light-emitting element G, and a first electrode of the third light-emitting element B, and a second electrode of the third light-emitting element B. The light-emitting control sub-circuit 420 is configured to: transmit a voltage at the second node N 2 and a second power voltage at the second power signal terminal VSS to the first electrode and the second electrode of the first light-emitting element R respectively in a first period, to the first electrode and the second electrode of the second light-emitting element G respectively in the second period, and to the first electrode and the second electrode of the third light-emitting element B respectively in the third period, under control of a first light-emitting control signal from the first light-emitting control terminal EM 1 , a second light-emitting control signal from the second light-emitting control terminal EM 2 , and a third light-emitting control signal from the third light-emitting control terminal EM 3 .

In this way, the circuit structure in FIG. 4 may achieve a time-sharing driving of three different light-emitting elements R, G and B in different periods of a frame time, so that the pixel unit in FIGS. 2A, 2B and 3 may display.

FIG. 5 shows a further circuit structure diagram of the pixel circuit in FIG. 4 .

On the basis of FIG. 4 , a pixel circuit 500 in FIG. 5 further includes a storage sub-circuit 430 , a charging control sub-circuit 440 and a reset sub-circuit 450 .

The storage sub-circuit 430 is electrically coupled between the first node N 1 and the third node N 3 .

The charging control sub-circuit 440 is electrically coupled to a scan signal terminal Scan, a data signal terminal Data, the first node N 1 , the second node N 2 and the third node N 3 , and is configured to generate a voltage difference between the first node N 1 and the third node N 3 under control a first scan voltage from the scan signal terminal Scan.

The reset sub-circuit 450 is electrically coupled to a first reset control terminal Reset 1 , a second reset control terminal Reset 2 , the third node N 3 and a reset voltage signal terminal Vini, and is configured to reset the third node N 3 by using a reset voltage signal from the reset voltage signal terminal Vini, under control of a first reset control signal from the first reset control terminal Reset 1 or a second reset control signal from the second reset control terminal Reset 2 .

FIG. 6 shows a detailed circuit diagram of the pixel circuit shown in FIG. 5 .

As shown in FIG. 6 , the light-emitting control sub-circuit 420 may include a first transistor T 1 , a second transistor T 2 , a third transistor T 3 , a fourth transistor T 4 , and a fifth transistor T 5 .

The first transistor T 1 has a control electrode electrically coupled to the second light-emitting control terminal EM 2 , a first electrode electrically coupled to the second node N 2 , and a second electrode electrically coupled to a fourth node N 4 .

The second transistor T 2 has a control electrode electrically coupled to the first light-emitting control terminal EM 1 , a first electrode electrically coupled to the second node N 2 , and a second electrode electrically coupled to the first electrode of the first light-emitting element R.

The third transistor T 3 has a control electrode electrically coupled to the third light-emitting control terminal EM 3 , a first electrode electrically coupled to the second node N 2 , and a second electrode electrically coupled to a fifth node N 5 .

The fourth transistor T 4 has a control electrode electrically coupled to the first light-emitting control terminal EM 1 , a first electrode electrically coupled to the fourth node N 4 , and a second electrode electrically coupled to a second power signal terminal VSS.

The fifth transistor T 5 has a control electrode electrically coupled to the second light-emitting control terminal EM 2 , a first electrode electrically coupled to the fifth node N 5 , and a second electrode electrically coupled to the second power signal terminal VSS.

The second electrode of the first light-emitting element R is electrically coupled to the first electrode of the second light-emitting element G via the fourth node N 4 , the second electrode of the second light-emitting element G is electrically coupled to the first electrode of the third light-emitting element B via the fifth node N 5 , and the second electrode of the third light-emitting element B is electrically coupled to the second power signal terminal VSS.

The driving sub-circuit 410 includes a sixth transistor T 6 .

The sixth transistor T 6 has a control electrode electrically coupled to the first node N 1 , a first electrode electrically coupled to the first power signal terminal VDD, and a second electrode electrically coupled to the second node N 2 .

The storage sub-circuit 430 includes a first capacitor C 1 .

The first capacitor C 1 has first terminal electrically coupled to the third node N 3 , and a second terminal electrically coupled to the first node N 1 .

The charging control sub-circuit 440 includes a seventh transistor T 7 and an eighth transistor T 8 .

The seventh transistor T 7 has a control electrode electrically coupled to the scan signal terminal Scan, a first electrode electrically coupled to the data signal terminal Data, and a second electrode electrically coupled to the third node N 3 .

The eighth transistor T 8 has a control electrode electrically coupled to the scan signal terminal Scan, a first electrode electrically coupled to the first node N 1 , and a second electrode electrically coupled to the second node N 2 .

The reset sub-circuit 450 includes a ninth transistor T 9 and a tenth transistor T 10 .

The ninth transistor T 9 has a control electrode electrically coupled to the first reset control terminal Reset 1 , a first electrode electrically coupled to the reset voltage signal terminal Vini, and a second electrode electrically coupled to the third node N 3 .

The tenth transistor T 10 has a control electrode electrically coupled to the second reset control terminal Reset 2 , a first electrode electrically coupled to the reset voltage signal terminal Vini, and a second electrode electrically coupled to the third node N 3 .

In some embodiments, the scan signal terminal Scan is configured to receive a scan signal for a current row of pixels, the first reset control terminal Reset 1 is configured to receive a scan signal for a previous row of pixels, and the second reset control terminal Reset 2 is configured to receive a scan signal for a next row of pixels. In the following description, this case is illustrated by way of example.

FIG. 7A shows a signal timing diagram of the pixel circuit shown in FIG. 6 . FIGS. 7B-7F show schematic diagrams of the principle of each phase in the pixel circuit shown in FIG. 6 .

For example, referring to FIG. 7A , each frame time includes three periods tp 1 , tp 2 and tp 3 . In each period, one light-emitting element (that is, one sub-pixel) is driven to emit light. For example, the first light-emitting element R is driven in the period tp 1 , the second light-emitting element G is driven in the period tp 2 , and the third light-emitting element B is driven in the period tp 3 . Each period is divided into three phases, that is, an initialization phase, a charging phase and a light-emitting phase.

Firstly described is the first period tp 1 , in which the first light-emitting element R is driven to emit light.

In an initialization phase P 1 , the first light-emitting control terminal EM 1 , the second light-emitting control terminal EM 2 and the third light-emitting control terminal EM 3 each provide a signal being at a high level, so that all of T 1 to T 5 are turned off.

The first reset control terminal Reset 1 provides a signal being at a low level, and the second reset control terminal Reset 2 and the scan signal terminal Scan each provide a signal being at a high level. Thus, T 7 , T 8 and T 10 are turned off, and T 9 is turned on. The third node N 3 is reset by Vini. Assuming that a voltage at the Vini is VGL, the third node N 3 is reset to the VGL. Moreover, due to the function of the capacitor C 1 , the voltage at the third node N 3 changes a floating voltage at the first node N 1 to be the VGL, so that T 6 is turned on, and a voltage Vdd at the first power terminal VDD is transmitted to the second node N 2 .

In the initialization phase P 1 , the schematic diagram of the principle of the pixel circuit is shown in FIG. 7B . It should be noted that in FIG. 7B , each of the transistors that are turned off in this phase is marked with an oblique cross “x”.

In a charging phase P 2 , the first light-emitting control terminal EM 1 , the second light-emitting control terminal EM 2 and the third light-emitting control terminal EM 3 each keep providing a signal being at a high level, so that T 1 to T 5 remain off.

The scan signal terminal Scan provides a signal being at a low level, and the first reset control terminal Reset 1 and the second reset control terminal Reset 2 each provide a signal being at a high level. Thus, T 7 and T 8 are turned on, and T 9 and T 10 are turned off. Then, a data voltage Vdata being at a high level is input to the third node N 3 from the data signal terminal Data, and a level at the first terminal of the first capacitor C 1 becomes Vdata. On the other hand, the first node N 1 and the second node N 2 are electrically coupled, and the first power signal terminal VDD starts to charge the first node, a balance is reached until a level at the node N 1 becomes Vdd+Vth, and Vth is a threshold voltage of the sixth transistor T 6 .

In this phase, through the charging of the data voltage terminal Data and the first power terminal VDD, a voltage applied to one terminal of the first capacitor C 1 is different from a voltage applied to another terminal of the first capacitor C 1 , and a voltage difference Vdd+Vth-Vdata is generated.

In the charging phase P 2 , the schematic diagram of the principle of the pixel circuit is shown in FIG. 7C . It should be noted that in FIG. 7C , each of the transistors that are turned off in this phase is marked with an oblique cross “x”.

In a light-emitting phase P 3 , the second light-emitting control terminal EM 2 and the third light-emitting control terminal EM 3 each keep providing a signal being at a high level, and the first light-emitting control terminal EM 1 provides a signal being at a low level, so that T 1 , T 3 and T 5 remain off, and T 2 and T 4 are turned on, which makes both terminals of the first light-emitting element R coupled to the second node N 2 and the second power terminal VSS, respectively.

The scan signal terminal Scan and the first reset control terminal Reset 1 each provides a signal being at a high level, and the second reset control terminal Reset 2 provides a signal being at a low level. Thus, T 10 is turned on, and T 7 to T 9 are turned off. Then, the reset signal terminal Vini changes the voltage at the third node N 3 to the VGL. Since the first node N 1 becomes floating again, the first capacitor C 1 maintains the previously generated voltage difference. Thus, the voltage at the first node N 1 becomes Vdd+Vth−Vdata+VGL. At this time, the sixth transistor T 6 is in a saturated state. For the P-type transistor T 6 , a source-gate voltage Vsg of the transistor T 6 is:

Vsg=Vdd −( Vdd+Vth−V data+ VGL )= V data− VGL−Vth.

Therefore, the expression of the driving current Id is:

Id=K ·( Vgs−Vth ) 2

= K ·(− V data+ VGL+Vth−Vth ) 2

= K ·( V data− VGL ) 2

where K is a current constant associated with the sixth transistor T 6 , and is related to process parameters and geometric dimensions of the sixth transistor T 6 . According to the above equation, the driving current Id used to drive the first light-emitting element R to emit light has nothing to do with the threshold voltage Vth of the sixth transistor T 6 , thereby eliminating brightness unevenness of the light-emitting element caused by the difference in the threshold voltage Vth of the sixth transistor T 6 .

In the light-emitting phase P 3 , the schematic diagram of the principle of the pixel circuit is shown in FIG. 7D . It should be noted that in FIG. 7D , each of the transistors that are turned off in this phase is marked with an oblique cross “x”.

Next described is the second period tp 2 , in which the second light-emitting element G is driven to emit light.

According to the timing diagram of FIG. 7A , operations in an initialization phase P 4 and a charging phase P 5 of the second period tp 2 are exactly the same as the operations in the initialization phase P 1 and the charging phase P 2 of the first period tp 1 , which will not be repeated here.

A difference between the second period tp 2 and the first period tp 1 lies in the light-emitting phase. In a light-emitting phase P 6 , the first light-emitting control terminal EM 1 and the third light-emitting control terminal EM 3 each keep providing a signal being at a high level, and the second light-emitting control terminal EM 2 provides a signal being at a low level, so that T 2 , T 3 and T 4 are turned off, and T 1 and T 5 are turned on, which makes both terminals of the second light-emitting element G coupled to the second node N 2 and the second power terminal VSS, respectively.

The scan signal terminal Scan and the first reset control terminal Reset 1 each provides a signal being at a high level, and the second reset control terminal Reset 2 provides a signal being at a low level. Thus, T 10 is turned on, and T 7 to T 9 are turned off. Then, the reset signal terminal Vini changes the voltage at the third node N 3 to the VGL. Since the first node N 1 becomes floating again, the first capacitor C 1 maintains the previously generated voltage difference. Thus, the voltage at the first node N 1 becomes Vdd+Vth-Vdata+VGL. At this time, the sixth transistor T 6 is in a saturated state. For the P-type transistor T 6 , a source-gate voltage Vsg of the transistor T 6 is:

Vsg=Vdd −( Vdd+Vth−V data+ VGL )= V data− VGL−Vth.

Therefore, the expression of the driving current Id is:

Id=K ·( Vgs−Vth ) 2

= K ·(− V data+ VGL+Vth−Vth ) 2

= K ·( V data− VGL ) 2

where K is a current constant associated with the sixth transistor T 6 , and is related to process parameters and geometric dimensions of the sixth transistor T 6 . According to the above equation, the driving current Id used to drive the second light-emitting element G to emit light has nothing to do with the threshold voltage Vth of the sixth transistor T 6 , thereby eliminating brightness unevenness of the light-emitting element caused by the difference in the threshold voltage Vth of the sixth transistor T 6 .

In the light-emitting phase P 6 , the schematic diagram of the principle of the pixel circuit is shown in FIG. 7E . It should be noted that in FIG. 7E , each of the transistors that are turned off in this phase is marked with an oblique cross “x”.

Finally described is the third period tp 3 , in which the third light-emitting element B is driven to emit light.

According to the timing diagram of FIG. 7A , operations in an initialization phase P 7 and a charging phase P 8 of the third period tp 3 are exactly the same as the operations in the initialization phase P 1 and the charging phase P 2 of the first period tp 1 , which will not be repeated here.

A difference between the third period tp 3 and the first period tp 1 lies in the light-emitting phase. In a light-emitting phase P 9 , the first light-emitting control terminal EM 1 and the second light-emitting control terminal EM 2 each keep providing a signal being at a high level, and the third light-emitting control terminal EM 3 provides a signal being at a low level, so that T 1 , T 2 , T 4 and T 5 are turned off, and T 3 is turned on, which makes both terminals of the third light-emitting element B coupled to the second node N 2 and the second power terminal VSS, respectively.

The scan signal terminal Scan and the first reset control terminal Reset 1 each provide a signal being at a high level, and the second reset control terminal Reset 2 provides a signal being at a low level. Thus, T 10 is turned on, and T 7 to T 9 are turned off. Then, the reset signal terminal Vini changes the voltage at the third node N 3 to the VGL. Since the first node N 1 becomes floating again, the first capacitor C 1 maintains the previously generated voltage difference. Thus, the voltage at the first node N 1 becomes Vdd+Vth−Vdata+VGL. At this time, the sixth transistor T 6 is in a saturated state. For the P-type transistor T 6 , a source-gate voltage Vsg of the sixth transistor T 6 is:

Vsg=Vdd −( Vdd+Vth −Vdata+ VGL )=Vdata− VGL−Vth.

Therefore, the expression of the driving current Id is:

Id=K ·( Vgs−Vth ) 2

= K ·(− V data+ VGL+Vth−Vth ) 2

= K ·( V data− VGL ) 2

where K is a current constant associated with the sixth transistor T 6 , and is related to process parameters and geometric dimensions of the sixth transistor T 6 . According to the above equation, the driving current Id used to drive the third light-emitting element B to emit light has nothing to do with the threshold voltage Vth of the sixth transistor T 6 , thereby eliminating brightness unevenness of the light-emitting element caused by the difference in the threshold voltage Vth of the sixth transistor T 6 .

In the light-emitting phase P 9 , the schematic diagram of the principle of the pixel circuit is shown in FIG. 7F . It should be noted that in FIG. 7F , each of the transistors that are turned off in this phase is marked with an oblique cross “x”.

FIG. 8 shows another detailed circuit diagram of the pixel circuit shown in FIG. 5 . A pixel circuit 800 in FIG. 8 differs from the pixel circuit 600 in FIG. 6 in the circuit structure of the light-emitting control sub-circuit 420 . The circuit structure of the other sub-circuits may not be repeated here.

As shown in FIG. 8 , the light-emitting control sub-circuit 420 may include a first transistor T 1 , a second transistor T 2 , a third transistor T 3 , a fourth transistor T 4 and a fifth transistor T 5 .

The first transistor T 1 has a control electrode electrically coupled to the second light-emitting control terminal EM 2 , a first electrode electrically coupled to the second node N 2 , and a second electrode electrically coupled to a fourth node N 4 .

The second transistor T 2 has a control electrode electrically coupled to the third light-emitting control terminal EM 3 , a first electrode electrically coupled to the second electrode of the third light-emitting element B, and a second electrode electrically coupled to the second power signal terminal VSS.

The third transistor T 3 has a control electrode electrically coupled to the third light-emitting control terminal EM 3 , a first electrode electrically coupled to the second node N 2 , and a second electrode electrically coupled to the fifth node N 5 .

The fourth transistor T 4 has a control electrode electrically coupled to the first light-emitting control terminal EM 1 , a first electrode electrically coupled to the fourth node N 4 , and a second electrode electrically coupled to a second power signal terminal VSS.

The fifth transistor T 5 has a control electrode electrically coupled to the second light-emitting control terminal EM 2 , a first electrode electrically coupled to the fifth node N 5 , and a second electrode electrically coupled to the second power signal terminal VSS.

The first electrode of the first light-emitting element R is electrically coupled to the second node N 2 , the second electrode of the first light-emitting element R is electrically coupled to the first electrode of the second light-emitting element G via the fourth node N 4 , and the second electrode of the second light-emitting element G is electrically coupled to the first electrode of the third light-emitting element B via the fifth node N 5 .

FIG. 9 shows a schematic block diagram of a display panel 900 according to the embodiments of the present disclosure.

As shown in FIG. 9 , the display panel 900 may include: a plurality of scan lines SL; a plurality of data lines DL arranged to cross the plurality of scan lines SL; and a plurality of pixel units 910 arranged at intersections of each scan line and each data line in a form of a matrix, and electrically coupled to respective data lines DL and scan lines SL. Each of the plurality of pixel units 910 is provided with a pixel circuit according to the embodiments of the present disclosure, for example, the pixel circuit shown in FIGS. 2A-2B , FIG. 3 , FIG. 4 , FIG. 5 , FIG. 6 or FIG. 8 .

When the display panel 900 of FIG. 9 is implemented by the pixel circuit shown in FIG. 4 , FIG. 5 , FIG. 6 or FIG. 8 , the data signal terminal Data in the pixel circuit receives the data signal from the corresponding data line DL, and the scan signal terminal Scan in the pixel circuit receives the scan signal from the corresponding scan line SL.

The display panel 900 may be any product or component with a display function, such as an electronic paper, a mobile phone, a tablet computer, a television, a display, a notebook a computer, a digital photo frame, a navigator, etc.

FIG. 10 shows a flowchart of a method 1000 for driving a pixel circuit according to the embodiments of the present disclosure. As described above, the driving of the pixel circuit is performed in a first period, a second period and a third period, and each period includes an initialization phase, a charging phase and a light-emitting phase.

The method 1000 includes step S 1010 to step S 1030 .

In step S 1010 , in the light-emitting phase of the first period, a first light-emitting control signal being at a second level is provided, and a second light-emitting control signal and a third light-emitting control signal each being at a first level are provided.

In addition, in the initialization phase and the charging phase of the first period, a first light-emitting control signal, a second light-emitting control signal and a third light-emitting control signal each being at a first level are provided.

In the embodiments described in FIG. 6 or FIG. 8 , the transistor is a P-type transistor, the first level is a high level, and the second level is a low level.

In step S 1020 , in the light-emitting phase of the second period, a second light-emitting control signal being at a second level is provided, and a first light-emitting control signal and a third light-emitting control signal each being at a first level are provided.

In addition, in the initialization phase and the charging phase of the second period, a first light-emitting control signal, a second light-emitting control signal and a third light-emitting control signal each being at a first level are provided.

In step S 1030 , in the light-emitting phase of the third period, a third light-emitting control signal being at a second level is provided, and a first light-emitting control signal and a second light-emitting control signal each being at a first level are provided.

In addition, in the initialization phase and the charging phase of the third period, a first light-emitting control signal, a second light-emitting control signal and a third light-emitting control signal each being at a first level are provided. The above detailed description has explained a number of embodiments by using schematic diagrams, flowcharts and/or examples. In a case that such schematic diagrams, flowcharts and/or examples contain one or more functions and/or operations, those skilled in the art should understand that each function and/or operation in such schematic diagrams, flowcharts or examples may be implemented individually and/or together through various structures, hardware, software, firmware or substantially any combination of them.

Although the present disclosure is described with reference to several conventional embodiments, it should be understood that the terms used are illustrative and exemplary rather than restrictive. Since the present disclosure may be implemented in various forms without departing from the spirit or essence of the present disclosure, it should be understood that the above-mentioned embodiments are not limited to any of the foregoing details, but should be interpreted broadly within the spirit and scope defined by the appended claims. Therefore, all changes and modifications falling within the scope of the claims or their equivalents shall be covered by the appended claims.