Direct-switching h-bridge current-mode drivers

Binary communication systems represent information using just two symbols—e.g. relatively high and low currents or voltages—to alternatively represent a logical one and a logical zero (i.e. 1 or 0). The number of levels used to represent digital data is not limited to two, however. For example, a type of signaling referred to as PAM-4 (for pulse-amplitude modulation, 4-level) provides for four discrete pulse amplitudes to convey two binary bits of data per symbol (i.e., 00, 01, 10, and 11). A series of symbols can thus be communicated as a signal that transitions between levels in a manner that reflects the series. The time each level is held to represent a symbol is termed the “symbol time” and the speed with which symbols can be communicated is termed the “symbol rate.”

Transmitters, or “drivers,” convey signals using combinations of voltage and current levels, typically emphasizing one over the other. Voltage-mode drivers introduce undesirable power-supply noise and have output swing (voltage amplitude) limitations that limit switching speeds and therefore symbol rates. Current-mode drivers address some of these issues but suffer from headroom issues, especially at lower power-supply voltages, that make it difficult to distinguish between symbols.

The detailed description is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar elements and in which:

FIG. 1 depicts a serial-link transmitter 100 that amplifies a differential input signal presented as streams of alternating odd and even data symbols do and de to present a differential, current-mode output signal across output nodes Out_p/Out_m.

FIG. 2 schematically depicts multiplexing circuitry 200 with peaking circuitry 205 .

FIG. 3 schematically depicts pre-amplification circuitry 300 that drives the gates of the PMOS pull-up transistors of H-bridge 105 of FIG. 1 in accordance with one embodiment.

FIG. 4 schematically depicts pre-amplification circuitry 400 that drives the gates of the NMOS pull-down transistors of H-bridge 105 of FIG. 1 in accordance with an embodiment that mirrors circuitry 300 of FIG. 3 .

FIG. 5 depicts a two-tap PAM4 serial-link transmitter 500 in accordance with one embodiment.

FIG. 6 depicts a four-bit, digital-to-analog converter (DAC), serial-link transmitter 600 in accordance with one embodiment.

FIG. 1 depicts a serial-link transmitter 100 that amplifies a differential input signal presented as streams of alternating odd and even data symbols do and de to present a differential, current-mode output signal on complementary output nodes Out_p/Out_m. (As with other designations herein, these monikers refer both to signals and their corresponding ports, lines, or nodes; whether a given designation refers to a signal, node, or port will be clear from the context.) In comparison with a voltage-mode transmitter, current-mode transmitter 100 achieves a higher output voltage swing with reduced power-supply noise. These advantages are of particular importance for multi-PAM systems in which transmitted symbols are divided into more than two regions. Transmitter 100 achieves these advantages using an H-bridge current driver 105 that drives output signal Out_p/Out_m using less current, and thus less power, than a traditional current-mode logic (CML) transmitter to achieve the desired signal amplitude.

H-bridge 105 steers current across output nodes Out_p/Out_m responsive to voltage levels on the current-control terminals (e.g. gates) of four transistors M 1 , M 2 , M 3 , and M 4 . The first and second transistors M 1 and M 2 are P-type devices (PMOS transistors) with a first current-handling terminal (the source) connected to a 1.2V supply terminal vdrv and a second current-handling terminal (the drain) connected to respective and complementary output nodes Out_p/Out_m. The third and fourth transistors M 3 and M 4 are N-type devices (NMOS transistors) with a first current-handling terminal (the source) connected to a 0.0V supply terminal vss and a second current-handling terminal (the drain) connected to respective output nodes Out_p/Out_m. The circuitry used to derive each of the four inputs to H-bridge 105 is similar. FIG. 1 details the development of signal out_pmos_p alone for ease of illustration. Subsequent embodiments are shown in more detail.

Transmitter 100 includes a digital input stage 110 powered between supply voltages vreg_pre and vss. Stage 110 provides alternating streams of odd and even data symbols do and de—and their complements (not shown)—timed to respective complementary clock signals clkn/clkp to a small-signal differential amplifier 115 as digital data signals do′ and de′. Amplifier 115 is a split-input current-mode logic (CML) stage with two differential transistor pairs M 5 /M 6 and M 7 /M 8 connected in parallel between a current source 120 and a load 125 , one pair for each signal multiplexed in from input stage 110 . Amplifier 115 combines binary alternating data signals do′ and de′ into an analog data signal dp input to a peaking analog pre-driver 130 with bias voltage vpb_pre, which amplifies signal dp to provide signal out_pmos_p to the gate of transistor M 1 in H bridge 105 . The other differential output from amplifier 115 (signal dm at the drains of transistors M 6 and M 8 ) feeds an identical pre-driver circuit (not shown) that supplies output signal out_pmos_m to the gate of transistor M 2 . The pull-down NMOS transistors M 3 and M 4 of H-bridge 105 are controlled by a separate combination of input stage, differential amplifier, and pre-driver that mirrors what is illustrated here. Exemplary circuitry for driving pull-down NMOS transistors M 3 and M 4 is detailed below in connection with FIG. 4 .

Signals dp and out_pmos_p are small-signal analog, which allows amplifier 115 and pre-driver 130 to operate in a linear range while switching a relatively low level of current, thus reducing supply noise and jitter. In an embodiment in which driver supply voltage vdrv is 1.2V relative to supply voltage vss, for example, signal dp transitions between about 0.6V and 0.9V and signal out_pmos_p between about 0.9V and 1.2V. Pre-driver 130 , a source-follower stage, allows for smaller, more efficient components in amplifier stage 115 but can be omitted in other embodiments.

All four transistors in H-bridge 105 operate as switched current sources. The higher voltage applied to terminal out_pmos_p, for example, turns off PMOS transistor M 1 . The lower voltage applied to terminal out_pmos_p is calibrated to set the current to node Out_p through transistor M 1 to 12 mA. The remaining transistors M 2 , M 3 , and M 4 are similarly controlled to either be in an off state or pass the same 12 mA current in an on state. Assuming fifty-ohm near and far termination, the output voltage at node Out_p thus transitions between 0.3V and 0.9V. Complementary output node Out_m likewise transitions between 0.3V and 0.9V so that transmitter 100 provides a 1.2V differential amplitude with a 0.6V common-mode voltage.

H-bridge 105 switches 12 mA currents between supply terminals vdrv and vss without series devices to maintain a higher swing voltage than a voltage-mode driver at a lower current than current-mode logic. The transistors of H-bridge 105 maintain a relatively constant current and so can be connected directly to the supply terminals rather than through an intervening component or components (e.g. via one or more a current sources). Direct supply connections improve headroom, which is especially important for multi-PAM signaling. Also advantageous, using the drive transistors to establish the output swing and drive current supports the use of an analog pre-driver for signal conditioning. In the instant example, analog pre-driver 130 provides peaking that expedites switching of H-bridge 105 to enhance edges of the output signal.

Differential amplifier 115 includes two differential pairs M 5 /M 6 and M 7 /M 8 , a current source 120 , and a load 125 . Focusing on symbols do′, transistor M 5 draws a current calibrated at current source 120 through load 125 and a resistor 127 to develop the control voltage applied to the gate of PMOS transistor M 1 , and thus controls the pull-up current for output node Out_p. Transistor M 6 operates similarly to transistor M 5 responsive to the complement of symbols do′ (not shown) to develop the control voltages for PMOS transistor M 2 . More complete signal paths through exemplary amplifiers are detailed in subsequent figures.

Current source 120 includes replica bias circuitry 135 that sets the current through load 125 to calibrate a secondary power-supply terminal 140 to the voltage level that results in the desired H-bridge PMOS bias level. Bias circuitry 135 can include scaled-down replicas of amplifier 115 and pre-driver 130 to derive a bias voltage vbn that inspires the requisite output current.

FIG. 2 schematically depicts multiplexing circuitry 200 similar to what is illustrated in FIG. 1 , with like-identified elements being the same or similar but including peaking circuitry 205 for further enhancing complementary signals dp/dm from differential amplifier 115 . Circuitry 200 includes a detailed account of input stage 110 , amplifier 115 , and peaking circuitry 205 . Peaking circuitry 205 operates at bias voltage vbp_pre and can be enabled or disabled responsive to an enable signal en.

Binary input signal do (de) of FIG. 1 is shown as differential signal odd_p/odd_n (even_p/even_n). Input stage 110 and differential amplifier 115 work together as a multiplexer that selects alternating data symbols responsive to respective complementary clock signals clkp/clkn and provides a corresponding sequence of differential, analog symbols across nodes dp and dm. Peaking circuitry 205 , when enabled by assertion of enable signal en, enhances the leading edges of signal dp/dm.

FIG. 3 schematically depicts pre-amplification circuitry 300 that drives the gates of PMOS pull-up transistors M 1 and M 2 of H-bridge 105 of FIG. 1 in accordance with another embodiment. Input stage 110 is as noted previously. A peaking pre-driver is omitted, however, in favor of a differential amplifier 305 with active loads 310 that produce a peaking response from differential transistor pairs M 5 /M 6 and M 7 /M 8 . Current source 315 draws low levels of current that prevent transistors within active loads 310 from switching off entirely, and thus improves switching speeds. The circuitry for pre-driver 130 is shown for both complementary output signals out_pmos_p/out_pmos_m.

FIG. 4 schematically depicts pre-amplification circuitry 400 that drives the gates of NMOS pull-down transistors M 3 and M 4 of H-bridge 105 of FIG. 1 in accordance with an embodiment that mirrors circuitry 300 of FIG. 3 . Differential signal out_nmos_m/out_nmos_p transitions between about zero volts—to turn NMOS transistors M 3 and M 4 off—and about 0.3V to bias NMOS transistors M 3 and M 4 on such that they pass a 6 mA current. Bias circuitry (not shown) derives a bias voltage vbp that inspires the requisite output current by setting the pull-down current-source voltages for signal halves out_nmos_m/out_nmos_p. The same or different bias circuitry can establish the operating point of differential NMOS pre-drivers by setting a bias voltage vpn_pre.

FIG. 5 depicts a two-tap PAM4 serial-link transmitter 500 in accordance with one embodiment. High performance communication channels suffer from many effects that degrade symbols and consequently render them difficult to resolve. Primary among them are frequency dependent channel loss (dispersion) and reflections from impedance discontinuities. These effects cause neighboring symbols to interfere with one another and are commonly referred to collectively as Inter-Symbol Interference (ISI). For example, neighboring relatively high-voltage symbols may spread out to raise the level of neighboring lower-voltage symbols; if the resulting voltage distortion is sufficiently high, the lower-voltage symbols may be interpreted incorrectly. Lower-voltage symbols may likewise induce errors in neighboring higher-voltage symbols.

ISI becomes more pronounced at higher signaling rates, ultimately degrading signal quality such that distinctions between symbols may be lost. Transmitter 500 corrects for ISI imposed on a current symbol by a prior symbol by multiplying the value of the prior symbol by a “tap value” selected to account for the ISI and adding the resultant product to the level used to express the current symbol. ISI from a prior symbol that tends to lower (raise) the level of the current symbol is thus offset by a similar rise (fall) in the driving signal.

A pair of serializers 505 serialize respective binary bitstreams D 0 and D 1 and present the resulting data to respective serial-link transmitter 510 and 515 that amplify the data signals in the manner detailed previously to present corresponding differential signals on output nodes Out_p/Out_m. Transmitters 510 and 515 are schematically identical but sized differently so that transmitter 510 drives twice the current of transmitter 515 . The combined current between output nodes Out_p/Out_m therefore expresses four levels. That is, for a drive current x, transmitters 510 and 515 collectively provide a combined drive current of ±0.66x±0.33x across output nodes Out_p/Out_m and through a load 520 . Load 520 is labeled “T-coil/ESD/Term” to connote its inclusion of a T-coil to offset parasitic capacitance, electrostatic-discharge protection (ESD) circuitry, and a termination impedance. These structures are well known to those of skill in the art, so a detailed discussion is omitted. Transmitter 500 includes two additional, scaled-down transmitters 525 and 530 that amplify a prior symbol to counteract ISI. Additional transmitters can be included in support of additional taps to offset ISI from earlier or later symbols.

FIG. 6 depicts a four-bit, digital-to-analog converter (DAC), serial-link transmitter 600 in accordance with one embodiment. Four serializers 605 serialize four respective binary bitstream d 0 , d 1 , d 2 , and d 3 and present the resulting data symbols to respective multiplexer pairs for amplification by H bridges 105 of the type detailed in connection with FIG. 1 . Transmitters 610 are schematically identical but sized differently so that their output currents, connected in parallel across the same load 520 , collectively provide sixteen discernable current levels through a load 520 . That is, for a drive current x, transmitters 610 collectively provide a combined drive current of ±0.5x±0.25x±0.125x±0.0625x across output nodes Out_p/Out_m and through load 520 . Other levels and relative proportions may of course be used. Additional bits and serializers can be added to achieve more output levels.

In the foregoing description and in the accompanying drawings, specific terminology and drawing symbols have been set forth to provide a thorough understanding. In some instances, the terminology and symbols may imply specific details that are not required. The term “coupled” is used herein to express a direct connection as well as a connection through one or more intervening circuits or structures.

While the subject matter has been described in connection with specific embodiments, other embodiments are also envisioned. Therefore, the spirit and scope of the appended claims should not be limited to the foregoing description. Only those claims specifically reciting “means for” or “step for” should be construed in the manner required under the sixth paragraph of 35 U.S.C. § 112.