Pixel circuit and display device including the same

Embodiments according to the present invention relates to a pixel circuit and a display device including the same, and more particularly, to a pixel circuit for improving display quality and a display device including the pixel circuit.

An organic light emitting diode display device has been widely used as a display device for an electronic device.

The organic light emitting diode display device includes a plurality of pixels, and each of the pixels includes an organic light emitting diode and a pixel circuit configured to drive the organic light emitting diode. The pixel circuit includes a plurality of transistors and a plurality of capacitors.

The organic light emitting diode display device has problems such as leakage currents, afterimages, and deterioration of reliability upon the driving when the organic light emitting diode display device is driven at high luminance and high temperatures. For example, upon the driving at high temperatures, a threshold voltage of the transistor included in the pixel circuit may be shifted to increase a leakage current, resulting in a decrease in luminance. Such a decrease in luminance may degrade display quality.

Problem to be Solved

One aspect of the present invention is to provide a pixel circuit for reducing a leakage current of a transistor.

Another aspect of the present invention is to provide a display device including the pixel circuit.

Means for Solving the Problem

According to embodiments, a pixel circuit includes: an organic light emitting diode which generates light for displaying an image; a first transistor including a first gate electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node; a first capacitor including a first electrode which receives a power supply voltage and a second electrode connected to the first node; a second transistor including a first gate electrode which receives a first gate signal, a first electrode which receives a data voltage, and a second electrode connected to the second node; a third transistor including a first gate electrode which receives the first gate signal, a first electrode connected to the first node, and a second electrode connected to the third node; a fourth transistor including a first gate electrode which receives a second gate signal, a first electrode connected to the first node, a second electrode which receives a first initialization voltage, and a second gate electrode which receives the first initialization voltage; and a seventh transistor including a first gate electrode which receives a third gate signal, a first electrode which receives a second initialization voltage, and a second electrode connected to an anode electrode of the organic light emitting diode.

In embodiments, the first initialization voltage may be set as a negative voltage with respect to a reference voltage, and may be greater than the second initialization voltage.

In embodiments, the third transistor may further include a second gate electrode which receives the first initialization voltage.

In embodiments, the fourth transistor may include a fourth-first transistor and a fourth-second transistor and have a dual connection structure in which the fourth-first transistor and the fourth-second transistor are connected to each other through a fifth node.

In embodiments, the third transistor may include a third-first transistor and a third-second transistor and have a dual connection structure in which the third-first transistor and the third-second transistor are connected to each other through a fourth node.

In embodiments, the pixel circuit may further include a second capacitor including a first electrode which receives the power supply voltage and a second electrode connected to the fourth and fifth nodes.

In embodiments, the third transistor may further include a second gate electrode which receives the first gate signal.

In embodiments, the pixel circuit may further include: a fifth transistor including a first gate electrode which receives an emission control signal, a first electrode which receives the power supply voltage, and a second electrode connected to the second node; and a sixth transistor including a first gate electrode which receives the emission control signal, a first electrode connected to the third node, and a second electrode connected to the anode electrode of the organic light emitting diode.

In embodiments, each of the first, second, fifth, sixth, and seventh transistors may further include a second gate electrode overlapping the first gate electrode and which receives the same signal as a signal applied to the first gate electrode.

In embodiments, the second gate signal may be a previous signal applied before the first gate signal, and the third gate signal may be a next signal applied after the first gate signal.

According to embodiments, a display device includes a display panel and a scan driver. The display panel includes a pixel circuit that includes: an organic light emitting diode which generates light for displaying an image; a first transistor including a first gate electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node; a first capacitor including a first electrode which receives a power supply voltage and a second electrode connected to the first node; a second transistor including a first gate electrode which receives a first scan signal, a first electrode which receive a data voltage, and a second electrode connected to the second node; a third transistor including a first gate electrode which receives the first scan signal, a first electrode connected to the first node, and a second electrode connected to the third node; a fourth transistor including a first gate electrode which receives a second scan signal, a first electrode connected to the first node, a second electrode which receives a first initialization voltage, and a second gate electrode which receives the first initialization voltage; and a seventh transistor including a first gate electrode which receives a third scan signal, a first electrode which receives a second initialization voltage, and a second electrode connected to an anode electrode of the organic light emitting diode. The scan driver generates a plurality of scan signals to provide the scan signals to the display panel.

In embodiments, the first initialization voltage may be set as a negative voltage with respect to a reference voltage, and may be greater than the second initialization voltage.

In embodiments, the third transistor may further include a second gate electrode which receives the first initialization voltage.

In embodiments, the fourth transistor may include a fourth-first transistor and a fourth-second transistor and have a dual connection structure in which the fourth-first transistor and the fourth-second transistor are connected to each other through a fifth node.

In embodiments, the third transistor may include a third-first transistor and a third-second transistor and have a dual connection structure in which the third-first transistor and the third-second transistor are connected to each other through a fourth node.

In embodiments, the pixel circuit may further include a second capacitor including a first electrode which receives the power supply voltage and a second electrode connected to the fourth and fifth nodes.

In embodiments, the third transistor may further include a second gate electrode which receives the first gate signal.

In embodiments, the pixel circuit may further include a fifth transistor including a first gate electrode which receives an emission control signal, a first electrode which receives the power supply voltage, and a second electrode connected to the second node, and a sixth transistor including a first gate electrode which receives the emission control signal, a first electrode connected to the third node, and a second electrode connected to the anode electrode of the organic light emitting diode.

In embodiments, each of the first, second, fifth, sixth, and seventh transistors may further include a second gate electrode overlapping the first gate electrode and which receives the same signal as a signal applied to the first gate electrode.

In embodiments, the first scan signal may be an nth scan signal, the second scan signal may be an (n−1)th scan signal, and the third scan signal may be an (n+1)th scan signal, and n is a natural number more than 1.

Effects of the Invention

According to a pixel circuit and a display device including the same according to embodiments of the present invention, transistors of a pixel circuit have a double gate structure including a first gate electrode and a second gate electrode, and a negative bias voltage is applied to a second gate electrode of at least one transistor which control a capacitor among the transistors, so that a leakage current can be reduced upon the driving at high temperatures. Accordingly, display quality can be prevented from deteriorating due to the leakage current.

FIG. 1 is a block diagram illustrating a display device according to embodiments.

FIG. 2 is a circuit diagram illustrating a pixel circuit according to embodiments.

FIG. 3 is a waveform diagram illustrating a method of driving the pixel circuit of FIG. 2 .

FIGS. 4A and 4B are I-V curves for a transistor having a double gate structure according to embodiments.

FIGS. 5A and 5B are conceptual diagrams for describing a leakage current of a transistor having a double gate structure according to embodiments.

FIG. 6 is a circuit diagram illustrating a pixel circuit according to another embodiment.

Hereinafter, embodiments of the present inventive concept will be explained in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram illustrating a display device according to embodiments.

Referring to FIG. 1 , a display device 100 may include a display panel 110 , a timing controller 120 , a data driver 130 , a scan driver 140 , and an emission driver 150 .

The display panel 110 may include a plurality of pixels P, a plurality of scan lines SL 1 , . . . , SLn, . . . , and SLN, a plurality of data lines DL 1 , . . . , DLm, . . . , and DLM, and a plurality of emission control lines EL 1 , . . . , ELn, . . . , and ELN (where n, N, m, and M are natural numbers).

The pixels may be arranged in the form of a matrix including a plurality of pixel rows and a plurality of pixel columns. With respect to the display panel 110 , the pixel row may correspond to a group of pixels disposed in the same horizontal line, and the pixel column may correspond to a group of pixels disposed in the same vertical line.

Each of the pixels P may include a pixel circuit PC, and the pixel circuit PC may include a plurality of transistors connected to the scan lines, the data lines, and the emission control lines, and an organic light emitting diode driven by the transistors.

According to an embodiment, the transistors of the pixel circuit PC may have a double gate structure in order to improve afterimages and enhance reliability of the transistor. The transistor having the double gate structure may include a first gate electrode and a second gate electrode. The second gate electrode may be configured as a bottom metal layer with respect to the first gate electrode.

The transistors having the double gate structure may be configured such that the same gate signal is applied to the first and second gate electrodes, or at least one transistor may be configured such that a bias signal different from a gate signal applied to the first gate electrode is applied to the second gate electrode.

The data lines DL 1 , . . . , DLm, . . . , and DLM may extend in a column direction CD, and may be arranged in a row direction RD. The data lines DL 1 , . . . , DLm, . . . , and DLM may be connected to the data driver 130 to transmit data voltages to the pixels P.

The scan lines SL 1 , . . . , SLn, . . . , and SLN may extend in the row direction RD, and may be arranged in the column direction CD. The scan lines SL 1 , . . . , SLn, . . . , and SLN may be connected to the scan driver 140 to transmit scan signals to the pixels P.

The emission control lines EL 1 , . . . , ELn, . . . , and ELN may extend in the row direction RD, and may be arranged in the column direction CD. The emission control lines EL 1 , . . . , ELn, . . . , and ELN may be connected to the emission driver 150 to transmit emission control signals to the pixels P.

In addition, the pixels P may receive a first power supply voltage ELVDD and a second power supply voltage ELVSS.

Each of the pixels P may receive the data voltage in response to the scan signal, and may generate light having a gray scale corresponding to the data voltage by using the first and second power supply voltages ELVDD and ELVSS.

The timing controller 120 may receive an image signal DATA and a control signal CONT from an external device. The image signal DATA may include red, green, and blue image data. The control signal CONT may include a horizontal synchronization signal, a horizontal synchronization signal, a main clock signal, and the like.

The timing controller 120 may output image data DATA′ converted from the image signal DATA according to specifications such as a pixel structure and resolution of the display panel 110 .

The timing controller 120 may generate a first control signal CONT 1 for driving the data driver 130 , a second control signal CONT 2 for driving the scan driver 140 , and a third control signal CONT 3 for driving the emission driver 150 based on the control signal CONT.

The data driver 130 may convert the image signal DATA′ into the data voltage in response to the first control signal CONT 1 , and may output the data voltage to the data lines DL 1 , . . . , DLm, . . . , and DLM.

The scan driver 140 may generate a plurality of scan signals Si, . . . , Sn, . . . , and SN in response to the second control signal CONT 2 .

The emission driver 150 may generate a plurality of emission control signals in response to the third control signal CONT 3 . The emission driver 150 may simultaneously output a plurality of emission control signals μl, . . . , En, . . . , and EN to the emission control lines EL 1 , . . . , ELn, . . . , and ELN, respectively, or may sequentially output the emission control signals μl, . . . , En, . . . , and EN to the emission control lines EL 1 , . . . , ELn, . . . , and ELN in an order from EL 1 to ELN, according to the third control signal CONT 3 .

FIG. 2 is a circuit diagram illustrating a pixel circuit according to embodiments.

Referring to FIGS. 1 and 2 , the pixel P may include a pixel circuit PC.

The pixel circuit PC may include an organic light emitting diode OLED, a first transistor T 1 , a first capacitor CST, a second transistor T 2 , a third transistor T 3 , a fourth transistor T 4 , a second capacitor CL, a fifth transistor T 5 , a sixth transistor T 6 , and a seventh transistor T 7 .

According to an embodiment, in order to improve the afterimages and enhance the reliability of the transistor, the transistor may have a double gate structure including a first gate electrode and a second gate electrode overlapping the first gate electrode under the first gate electrode.

According to an embodiment, the transistor may be a P-type transistor, which may be turned on when a low-level voltage is applied to the gate electrode, and may be turned off when a high-level voltage is applied to the gate electrode. In another embodiment, the transistors may be implemented as N-type transistors. In this case, a turn-on voltage may be the high-level voltage, and a turn-off voltage may be the low-level voltage.

The pixel circuit PC may further include a m th data line DLm, an n th scan line SLn, an (n−1) th scan line SLn−1, an (n+1) th scan line SLn+1, an n th emission control line ELn, a power supply voltage line PVL, a first initialization voltage line IVI 1 , and a second initialization voltage line IVL 2 .

For example, the first transistor T 1 may include a first gate electrode and a second gate electrode which are connected to a first node N 1 , a first electrode connected to a second node N 2 , and a second electrode connected to a third node N 3 .

The first capacitor CST may include a first electrode connected to the power supply voltage line PVL and a second electrode connected to the first node N 1 . The power supply voltage line PVL may provide a high-power supply voltage ELVDD.

The second transistor T 2 may include a first gate electrode and a second gate electrode configured to receive a first gate signal, a first electrode connected to the m th data line DLm, and a second electrode connected to the second node N 2 . The m th data line DLm may transmit a data voltage Vdata corresponding to the pixel P. The first gate signal may be an n th scan signal Sn provided from the scan driver 140 , and may be transmitted through the n th scan line SLn.

The third transistor T 3 may include a third-first transistor T 3 - 1 and a third-second transistor T 3 - 2 and have a dual connection structure in which the third-first transistor T 3 - 1 and the third-second transistor T 3 - 2 are connected to each other through a fourth node N 4 .

According to an embodiment, the third transistor T 3 may have the dual connection structure in order to reduce a leakage current occurred upon the driving at high luminance and high temperatures.

The third-first transistor T 3 - 1 may include a first gate electrode configured to receive the first gate signal (i.e., n th scan signal Sn), a first electrode connected to the first node N 1 , a second electrode connected to the fourth node N 4 , and a second gate electrode connected to the first initialization voltage line IVL 1 . The first initialization voltage line IVL 1 may transmit a first initialization voltage Vinit 1 for initializing a charging voltage of the first capacitor CST. The first initialization voltage Vinit 1 may be a negative voltage with respect to a reference voltage. That is, the first initialization voltage Vinit 1 may have a value less than a value of the reference voltage.

The third-second transistor T 3 - 2 may include a first gate electrode configured to receive the first gate signal, a first electrode connected to the fourth node N 4 , a second electrode connected to the third node N 3 , and a second gate electrode connected to the first initialization voltage line IVL 1 .

The first gate signal may be the n th scan signal provided from the scan driver 140 , and may be transmitted through the n th scan line SLn.

The fourth transistor T 4 may include a fourth-first transistor T 4 - 1 and a fourth-second transistor T 4 - 2 and have a dual connection structure in which the fourth-first transistor T 4 - 1 and the fourth-second transistor T 4 - 2 are connected to each other through a fifth node N 5 .

According to an embodiment, the fourth transistor T 4 may have the dual connection structure in order to reduce the leakage current occurred upon the driving at high luminance and high temperatures.

The fourth-first transistor T 4 - 1 may include a first gate electrode configured to receive a second gate signal, a first electrode connected to the first node N 1 , a second electrode connected to the fifth node N 5 , and a second gate electrode connected to the first initialization voltage line IVL 1 .

The fourth-second transistor T 4 - 2 may include a first gate electrode configured to receive the second gate signal, a first electrode connected to the fifth node N 5 , and a second electrode and a second gate electrode which are connected to the first initialization voltage line IVL 1 .

The second gate signal may be an (n−1) th scan signal Sn−1 provided from the scan driver 140 , and may be transmitted through the (n−1) th scan line SLn−1.

The second capacitor CL may include a first electrode, and a second electrode. The first electrode connected to the power supply voltage line PVL. The second electrode is connected to the third transistor T 3 and the fourth transistor T 4 through the fourth node N 4 and the fifth node N 5 , respectively. The second capacitor CL may control leakage currents of the third transistor T 3 and the fourth transistor T 4 .

The fifth transistor T 5 may include a first gate electrode and a second gate electrode connected to the n th emission control line ELn, a first electrode connected to the power supply voltage line PVL, and a second electrode connected to the second node N 2 . The n th emission control line ELn may receive an n th emission control signal En provided from the emission driver 150 .

The sixth transistor T 6 may include a first gate electrode and a second gate electrode connected to the n th emission control line ELn, a first electrode connected to the third node N 3 , and a second electrode connected to an anode electrode of the organic light emitting diode OLED.

The seventh transistor T 7 may include a first gate electrode and a second gate electrode configured to receive a third gate signal, a first electrode connected to the second initialization voltage line IVL 2 , and a second electrode connected to the anode electrode of the organic light emitting diode OLED. The second initialization voltage line IVL 2 may transmit a second initialization voltage Vinit 2 to the seventh transistor T 7 for initializing the anode electrode. The second initialization voltage Vinit 2 may be a negative voltage with respect to the reference voltage. That is, the second initialization voltage Vinit 2 may have a value less than a value of the reference voltage.

According to an embodiment, the first initialization voltage Vinit 1 may be set as a negative voltage greater than the second initialization voltage Vinit 2 .

The third gate signal may be an (n+1) th scan signal Sn+1 provided from the scan driver 140 , and may be transmitted through the (n+1) th scan line SLn+1.

FIG. 3 is a waveform diagram illustrating a method of driving the pixel circuit of FIG. 2 .

Referring to FIGS. 2 and 3 , a method of driving the pixel circuit PC will be described as follows.

During a first interval a of a frame, in response to a low voltage of the (n−1) th scan signal Sn−1 applied to the (n−1) th scan line SLn−1, the fourth-first transistor T 4 - 1 and the fourth-second transistor T 4 - 2 having the dual connection structure may be turned on, and the remaining transistors T 1 , T 2 , T 3 , T 5 , T 6 , and T 7 may be turned off. Accordingly, the first capacitor CST may be charged to the first initialization voltage Vinit 1 applied by the first initialization voltage line IVl 1 . The first initialization voltage Vinit 1 may be a negative bias voltage, and may be greater than the second initialization voltage Vinit 2 .

During a second interval b of the frame, in response to a low voltage of the n th scan signal Sn applied to the n th scan line SLn, the second transistor T 2 , and the third-first transistor T 3 - 1 and the third-second transistor T 3 - 2 having the dual connection structure may be turned on, and the remaining transistors T 1 , T 4 , T 5 , T 6 , and T 7 may be turned off.

As the third-first transistor T 3 - 1 and the third-second transistor T 3 - 2 are turned on, the first transistor T 1 may be diode-connected. A difference value in voltage between a voltage applied to the second node N 2 and corresponding to the data voltage Vdata applied to the m th data line DLm and a threshold voltage Vth of the first transistor T 1 may be applied to the first node N 1 . Accordingly, a difference value in voltage between absolute values of the voltage corresponding to the data voltage Vdata and the threshold voltage Vth may be applied to the first node N 1 to compensate for the threshold voltage of the first transistor T 1 .

In addition, the first capacitor CST may be charged with the voltage corresponding to the data voltage Vdata applied to the m th data line DLm.

As described above, during the second interval b of the frame, the threshold voltage Vth of the first transistor T 1 may be compensated, and the voltage corresponding to the data voltage Vdata may be stored in the first capacitor CST.

During a third interval c of the frame, in response to a low voltage of the (n+1) th scan signal Sn+1 applied to the (n+1) th scan line SLn+1, the seventh transistor T 7 may be turned on, and the remaining transistors T 1 , T 2 , T 3 , T 4 , T 5 , and T 6 may be turned off.

As the seventh transistor T 7 is turned on, the second initialization voltage Vinit 2 applied to the second initialization voltage line IVL 2 may be applied to the anode electrode of the organic light emitting diode OLED to initialize the anode electrode of the organic light emitting diode OLED.

As described above, during the third interval c of the frame, the anode electrode of the organic light emitting diode OLED may be initialized.

During a fourth interval d of the frame, when a low-level n th emission-on voltage is applied to the n th emission control line ELn, the fifth and sixth transistors T 5 and T 6 may be turned on, and the remaining transistors T 1 , T 2 , T 3 , T 4 , and T 7 may be turned off.

Accordingly, the first transistor T 1 may be turned on by the voltage stored in the first capacitor CST and corresponding to the data voltage Vdata, and a driving current corresponding to the data voltage Vdata may flow through the organic light emitting diode OLED. As a result, the organic light emitting diode OLED may generate light having a gray scale corresponding to an image.

FIGS. 4A and 4B are I-V curves for a transistor having a double gate structure according to embodiments.

Referring to FIGS. 4A and 4B , curves show I-V characteristics of a transistor when the transistor is driven at a high temperature of 85 degrees Celsius (° C.).

Referring to FIG. 4A , upon the driving at high temperatures, when a positive bias voltage +VG is applied to a second gate electrode of a transistor having a double gate structure, the threshold voltage Vth may move to a negative side so that the leakage current may be increased. On the contrary, when a negative bias voltage −VG is applied to the second gate electrode of the transistor having the double gate structure, the threshold voltage Vth may move to a positive side so that the leakage current may be reduced.

Referring to FIG. 4B , in a transistor having a double gate structure according to Comparative Example 1 (BML G-Sync), a gate signal that is the same as a signal applied to a first gate electrode may be applied to a second gate electrode.

In a transistor having a single gate structure according to Comparative Example 2 (Single), a gate signal may be applied to only a first gate electrode.

In a transistor having a double gate structure according to an embodiment (BML Vinit-Sync), a negative (−) gate signal different from a gate signal applied to a first gate electrode may be applied to a second gate electrode.

As a result of measuring an off-leakage current at a gate/source voltage VGS (i.e., voltage between gate electrode and source electrode of a transistor) of about 7.9 voltages (V), the transistor having the double gate structure according to Comparative Example 1 (BML G-Sync) had a leakage current Ids of about 2.07 picoamperes (pA), the transistor having the single gate structure according to Comparative Example 2 (Single) had a leakage current Ids of about 76.9 femtoamperes (fA), and the transistor having the double gate structure according to the embodiment (BML Vinit-Sync) had a leakage current Ids of about 66.6 fA.

Accordingly, in the transistor having the double gate structure, when the negative (−) gate signal different from the signal applied to the first gate electrode is applied to the second gate electrode, it was found that the off-leakage current is reduced.

As described above, in the pixel circuit, the negative bias voltage may be applied to the second gate electrodes of the fourth transistor T 4 configured to control the initialization of the previous data voltage charged in the capacitor CST and the third transistor T 3 configured to control the charging of the capacitor CST with the data voltage thereof, so that the leakage currents may be reduced when the third and fourth transistors T 3 and T 4 are driven at high temperatures (e.g., 85° C.). Accordingly, deterioration of display quality due to the leakage current may be improved.

FIGS. 5A and 5B are conceptual diagrams for describing a leakage current of a transistor having a double gate structure according to embodiments.

Referring to FIGS. 2, 5A, and 5B , a deviation ΔV G of a gate signal due to a leakage current of a transistor was measured in an emission-on interval in which the organic light emitting diode emits light.

In the transistor having the double gate structure according to Comparative Example 1 (BML G-Sync), a gate signal that is the same as a first gate signal applied to the first gate electrode may be applied to the second gate electrode BML.

In the transistor having the single gate structure according to Comparative Example 2 (Single), the gate signal may be applied to only the first gate electrode.

In the transistor having the double gate structure according to the embodiment (BML Vinit-Sync), a second gate signal, which is a negative bias signal different from a first gate signal applied to the first gate electrode, may be applied.

First, when an operating temperature is a room temperature RT, the transistor having the double gate structure according to Comparative Example 1 (BML G-Sync) had a deviation ΔV G of the first gate signal that is about 0.66 percentages (%), the transistor having the single gate structure according to Comparative Example 2 (Single) had a deviation ΔV G of a first gate signal that is about 0.50%, and the transistor having the double gate structure according to the embodiment (BML Vinit-Sync) had a deviation ΔV G of the first gate signal that is about 0.49%.

It was found that the leakage current is the minimum in the embodiment (BML Vinit-Sync) in which a negative bias signal Vinit different from the signal applied to the first gate electrode is applied to the second gate electrode.

When the operating temperature is a high temperature (85 degrees Celsius), the transistor having the double gate structure according to Comparative Example 1 (BML G-Sync) had a deviation ΔV G of the first gate signal that is about 3.21%, the transistor having the single gate structure according to Comparative Example 2 (Single) had a deviation ΔV G of the first gate signal that is about 0.68%, and the transistor having the double gate structure according to the embodiment (BML Vinit-Sync) had a deviation ΔV G of the first gate signal that is about 0.66%.

It was found that the leakage current is remarkably small in the embodiment (BML Vinit-Sync) in which the negative bias signal Vinit different from the first gate signal applied to the first gate electrode is applied to the second gate electrode.

Therefore, according to the present embodiment, when the negative bias signal different from the first gate signal applied to the first gate electrode is applied to the second gate electrode of the transistor having the double gate structure, the leakage current may be reduced at high temperatures.

As described above, in the pixel circuit, the negative bias voltage may be applied to the second gate electrodes of the fourth transistor T 4 configured to control the initialization of the previous data voltage charged in the capacitor CST and the third transistor T 3 configured to control the charging of the capacitor CST with the data voltage thereof, so that the leakage currents may be reduced when the third and fourth transistors T 3 and T 4 are driven at high temperatures (e.g., 85° C.). Accordingly, the deterioration of display quality due to the leakage current may be improved.

FIG. 6 is a circuit diagram illustrating a pixel circuit according to another embodiment.

Referring to FIGS. 1 and 6 , the pixel P may include a pixel circuit PC 1 .

The pixel circuit PC 1 may further include a m th data line DLm, an n th scan line SLn, an (n−1) th scan line SLn−1, an (n+1) th scan line SLn+1, an n th emission control line ELn, a power supply voltage line PVL, a first initialization voltage line IVL 1 , and a second initialization voltage line IVL 2 .

According to an embodiment, a transistor may have a double gate structure having two gate electrodes. The transistor may be a P-type transistor, which may be turned on when a low-level voltage is applied to the gate electrode, and may be turned off when a high-level voltage is applied to the gate electrode. In another embodiment, transistors may be implemented as N-type transistors. In this case, a turn-on voltage may be the high-level voltage, and a turn-off voltage may be the low-level voltage.

According to an embodiment, a first transistor T 1 may include a first gate electrode and a second gate electrode which are connected to a first node N 1 , a first electrode connected to a second node N 2 , and a second electrode connected to a third node N 3 .

A capacitor CST may include a first electrode connected to the power supply voltage line PVL and a second electrode connected to the first node N 1 . The power supply voltage line PVL may provide a high-power supply voltage ELVDD.

The second transistor T 2 may include a first gate electrode and a second gate electrode configured to receive a first gate signal, a first electrode connected to the m th data line DLm, and a second electrode connected to the second node N 2 . The m th data line DLm may transmit a data voltage Vdata corresponding to the pixel P. The first gate signal may be an n th scan signal Sn provided from the scan driver 140 , and may be transmitted through the n th scan line SLn.

The third transistor T 3 may have a dual connection structure, and may include a third-first transistor T 3 - 1 and a third-second transistor T 3 - 2 connected to each other through a fourth node N 4 .

The third-first transistor T 3 - 1 may include a first gate electrode and a second gate electrode which are configured to receive the first gate signal, a first electrode connected to the first node N 1 , and a second electrode connected to the fourth node N 4 .

The third-second transistor T 3 - 2 may include a first gate electrode and a second gate electrode which are configured to receive the first gate signal (i.e., n th scan signal Sn), a first electrode connected to the fourth node N 4 , and a second electrode connected to the third node N 3 .

The first gate signal may be the n th scan signal Sn provided from the scan driver 140 , and may be transmitted through the n th scan line SLn.

The fourth transistor T 4 may have a dual connection structure, and may include a fourth-first transistor T 4 - 1 and a fourth-second transistor T 4 - 2 connected to each other through a fifth node N 5 .

The fourth-first transistor T 4 - 1 may include a first gate electrode configured to receive a second gate signal, a first electrode connected to the first node N 1 , a second electrode connected to the fifth node N 5 , and a second gate electrode connected to the first initialization voltage line IVL 1 .

The fourth-second transistor T 4 - 2 may include a first gate electrode configured to receive the second gate signal, a first electrode connected to the fifth node N 5 , and a second electrode and a second gate electrode connected to the first initialization voltage line IVL 1 .

The second gate signal GI may be an (n−1) th scan signal Sn−1 provided from the scan driver 140 , and may be transmitted through the (n−1) th scan line SLn−1.

A second capacitor CL may include a first electrode and a second electrode. The first electrode connected to the power supply voltage line PVL. The second electrode may be connected to the third transistor T 3 and the fourth transistor T 4 through the fourth node N 4 and the fifth node N 5 , respectively. The second capacitor CL may control leakage currents of the third transistor T 3 and the fourth transistor T 4 .

The fifth transistor T 5 may include a first gate electrode and a second gate electrode connected to the n th emission control line ELn, a first electrode connected to the power supply voltage line PVL, and a second electrode connected to the second node N 2 . The n th emission control line ELn may receive an n th emission control signal En provided from the emission driver 150 .

The sixth transistor T 6 may include a first gate electrode and a second gate electrode connected to the n th emission control line ELn, a first electrode connected to the third node N 3 , and a second electrode connected to an anode electrode of the organic light emitting diode OLED.

The seventh transistor T 7 may include a first gate electrode and a second gate electrode configured to receive a third gate signal, a first electrode connected to the second initialization voltage line IVL 2 , and a second electrode connected to the anode electrode of the organic light emitting diode OLED. The second initialization voltage line IVL 2 may transmit a second initialization voltage Vinit 2 to the seventh transistor T 7 for initializing the anode electrode.

The third gate signal may be an (n+1) th scan signal Sn+1 provided from the scan driver 140 , and may be transmitted through the (n+1) th scan line SLn+1.

According to the present embodiment, a first initialization voltage Vinit 1 , which is a negative bias signal different from the second gate signal Sn−1 applied to the first gate electrode of the fourth transistor T 4 , may be applied to the second gate electrode of the fourth transistor T 4 among the third transistor T 3 and the fourth transistor T 4 .

Although not shown, in another embodiment, the first initialization voltage Vinit 1 , which is a negative bias signal different from the first gate signal Sn applied to the first gate electrode of the third transistor T 3 , may be applied to the second gate electrode of the third transistor T 3 among the third transistor T 3 and the fourth transistor T 4 .

As described above, in the pixel circuit, the negative bias voltage may be applied to at least one of the second gate electrodes of the fourth transistor T 4 and the third transistor T 3 , so that the leakage currents may be reduced upon the driving at high temperatures. Here, the fourth transistor T 4 is configured to control the initialization of the previous data voltage charged in the capacitor CST, and the third transistor T 3 is configured to control the charging of the capacitor CST with the data voltage thereof. Accordingly, the deterioration of display quality due to the leakage current may be improved.

According to the above embodiments, transistors of a pixel circuit have a double gate structure including a first gate electrode and a second gate electrode, and a negative bias voltage is applied to a second gate electrode of at least one transistor configured to control the charging of a capacitor among the transistors, so that a leakage current can be reduced upon the driving at high temperatures. Accordingly, display quality can be prevented from deteriorating due to the leakage current.

The present invention may be applied to a display device and various devices and systems including the display device. For example, the present invention may be applied to a smart phone, a cellular phone, a personal digital assistant (′PDA″), a portable multimedia player (“PMP”), a digital camera, a camcorder, a personal computer (“PC”), a server computer, a workstation, a laptop, a digital TV, a set top box, a music player, a portable game console, a car navigation system, a smart card, a printer, and the like.

The foregoing is illustrative of embodiments and is not to be construed as limiting thereof. Although a few embodiments have been described, those skilled in the art will readily appreciate that many modifications are possible in the embodiments without materially departing from the novel teachings and advantages of the present inventive concept. Accordingly, all such modifications are intended to be included within the scope of the present inventive concept as defined in the claims. Therefore, it is to be understood that the foregoing is illustrative of various embodiments and is not to be construed as limited to the specific embodiments disclosed, and that modifications to the disclosed embodiments, as well as other embodiments, are intended to be included within the scope of the appended claims.