Three-dimensional semiconductor memory device

This U.S. non-provisional patent application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2020-0107326, filed on Aug. 25, 2020, in the Korean Intellectual Property Office, the entire contents of which are hereby incorporated by reference.

1. Field

The present disclosure relates to a three-dimensional semiconductor memory device, and in particular, to a three-dimensional semiconductor memory device with improved reliability and an increased integration density.

2. Description of the Related Art

Higher integration of semiconductor devices is required to satisfy consumer demands for superior performance and inexpensive prices. In the case of semiconductor devices, since their integration is an important factor in determining product prices, increased integration is especially required. In the case of two-dimensional or planar semiconductor devices, since their integration is mainly determined by the area occupied by a unit memory cell, integration is greatly influenced by the level of a fine pattern forming technology. However, the extremely expensive process equipment needed to increase pattern fineness sets a practical limitation on increasing integration for two-dimensional or planar semiconductor devices. To overcome such a limitation, there have been recently proposed three-dimensional semiconductor memory devices including three-dimensionally arranged memory cells.

It is an aspect to provide a three-dimensional semiconductor memory device with improved reliability and an increase integration density.

According to an aspect of an example embodiment, a three-dimensional semiconductor memory device may include a first substrate including a bit-line connection region and a word-line connection region, a cell array structure on the first substrate, a second substrate including a first core region and a second core region, which are respectively overlapped with the bit-line connection region and the word-line connection region, and a peripheral circuit structure on the second substrate. The cell array structure may include word lines stacked on the first substrate, bit lines crossing the word lines in a first direction perpendicular to a top surface of the first substrate, first lower metal pads provided on the bit-line connection region and connected to the bit lines, and second lower metal pads provided on the word-line connection region and connected to the word lines. The peripheral circuit structure may include sense amplifiers provided on the first core region, sub-word line drivers provided on the second core region, first upper metal pads provided on the first core region and connected to the sense amplifiers, and second upper metal pads provided on the second core region and connected to the sub-word line drivers. The first lower metal pads may be bonded to the first upper metal pads, and the second lower metal pads may be bonded to the second upper metal pads.

According to another aspect of an example embodiment, a three-dimensional semiconductor memory device may include a first substrate including a bit-line connection region, a word-line connection region, and a first peripheral region, a cell array structure including a memory cell array, which includes memory cells three-dimensionally arranged on the bit-line connection region and the word-line connection region of the first substrate, and the cell array structure including lower control circuits, which are provided on the first peripheral region of the first substrate, a second substrate including a first core region, a second core region, and a second peripheral region, which are overlapped with the bit-line connection region, the word-line connection region, and the first peripheral region, respectively, and a peripheral circuit structure including sense amplifiers provided on the first core region of the second substrate, sub-word line drivers provided on the second core region of the second substrate, and upper control circuits provided on the second peripheral region of the second substrate.

According to yet another aspect of an example embodiment, a three-dimensional semiconductor memory device may include a first substrate including a bit-line connection region, a word-line connection region, and a first peripheral region, a cell array structure on the first substrate, the cell array structure including bit lines, which are extended in a first direction perpendicular to a top surface of the first substrate, word lines, which are extended in a second direction to cross the bit lines, memory cells, which are provided at intersections of the bit lines and the word lines, first lower metal pads, which are provided on the bit-line connection region and are connected to the bit lines, second lower metal pads, which are provided on the word-line connection region and are connected to the word lines, and third lower metal pads, which are provided on the first peripheral region and are connected to lower control circuits, a second substrate including a first core region, a second core region, and a second peripheral region, which are overlapped with the bit-line connection region, the word-line connection region, and the first peripheral region, respectively, and a peripheral circuit structure on the second substrate. The peripheral circuit structure may include first upper metal pads provided on the first core region and connected to sense amplifiers, second upper metal pads provided on the second core region and connected to sub-word line drivers, and third upper metal pads provided on the second peripheral region and connected to upper control circuits. The first lower metal pads may be bonded to the first upper metal pads, the second lower metal pads may be bonded to the second upper metal pads, and the third lower metal pads may be bonded to the third upper metal pads.

Example embodiments will be more clearly understood from the following brief description taken in conjunction with the accompanying drawings, in which:

FIG. 1 is a block diagram illustrating a three-dimensional semiconductor memory device according to an example embodiment;

FIG. 2 is a sectional view schematically illustrating a three-dimensional semiconductor memory device according to an example embodiment;

FIG. 3 is a perspective view schematically illustrating a three-dimensional semiconductor memory device according to an example embodiment;

FIG. 4 is a diagram illustrating an example of a cell array structure and a peripheral circuit structure that are disposed in a three-dimensional semiconductor memory device according to an example embodiment;

FIGS. 5A and 5B are plan views illustrating a cell array structure of a three-dimensional semiconductor memory device according to example embodiments;

FIGS. 6A and 6B are sectional views, each of which illustrates sections taken along lines I-I′, and of FIGS. 5A and 5B , respectively;

FIG. 7 is a diagram exemplarily illustrating a connection structure between bit lines and bit-line connection lines in a three-dimensional semiconductor memory device according to an example embodiment;

FIG. 8 is a diagram exemplarily illustrating a connection structure between bit lines and metal pads in a three-dimensional semiconductor memory device according to an example embodiment;

FIG. 9 is a plan view schematically illustrating a three-dimensional semiconductor memory device according to an example embodiment;

FIG. 10 is a diagram illustrating a connection structure between the cell array structure and the peripheral circuit structure in a region A of FIG. 9 ;

FIGS. 11A and 11B are diagrams illustrating connection structures between the cell array structure and the peripheral circuit structure in a region B of FIG. 9 , according to various example embodiments;

FIGS. 12 to 16 are sectional views illustrating a three-dimensional semiconductor memory device according to various example embodiments; and

FIGS. 17 to 22 are diagrams illustrating an example of lower and upper metal pads that are arranged in a three-dimensional semiconductor memory device according to various example embodiments.

Example embodiments will now be described more fully with reference to the accompanying drawings, in which example embodiments are shown. The accompanying drawings represent non-limiting, example embodiments as described herein.

FIG. 1 is a block diagram illustrating a three-dimensional semiconductor memory device according to an example embodiment.

Referring to FIG. 1 , a three-dimensional semiconductor memory device may include a memory cell array 1 , a row decoder 2 , a sensing amplifier (Sense Amp) 3 , a column decoder 4 , and a control logic 5 .

The memory cell array 1 may include a plurality of memory cells MC, which are three-dimensionally arranged. Each of the memory cells MC may be provided between and connected to a word line WL and a bit line BL, which are disposed to cross each other.

Each of the memory cells MC may include a selection element TR and a data storing element CAP, which are electrically connected to each other in series. The data storing element CAP may be connected to the bit line BL through the selection element TR, and the selection element TR may be provided between and connected to the data storing element CAP and the word line WL. The selection element TR may be a field effect transistor (FET), and the data storing element CAP may be realized with a capacitor, a variable resistor, or the like. As an example, the selection element TR may include a transistor, which has a gate electrode connected to the word line WL and drain/source terminals connected to the bit line BL and the data storing element CAP, respectively.

The row decoder 2 may be configured to decode address information, which is input from outside the three-dimensional semiconductor memory device, and to select one of the word lines WL of the memory cell array 1 , based on the decoded address information. The address information decoded by the row decoder 2 may be provided to a row driver (not shown), and in this case, the row driver may provide predetermined voltages to the selected one of the word lines WL and the unselected ones of the word lines WL, respectively, in response to the control of a control circuit.

The sensing amplifier (Sense Amp) 3 may be configured to sense, amplify, and output a difference in voltage between one of the bit lines BL, which is selected based on address information decoded by the column decoder 4 , and a reference bit line.

The column decoder 4 may provide a data transmission path between the sensing amplifier 3 and an external device (e.g., a memory controller). The column decoder 4 may be configured to decode address information, which is input from outside the three-dimensional semiconductor memory device, and to select one of the bit lines BL, based on the decoded address information.

The control logic 5 may be configured to generate control signals, which are used to control data writing or reading operations on the memory cell array 1 .

FIG. 2 is a sectional view schematically illustrating a three-dimensional semiconductor memory device according to an example embodiment.

Referring to FIG. 2 , a three-dimensional semiconductor memory device may include a cell array structure CS and a peripheral circuit structure PS on the cell array structure CS.

The cell array structure CS may include a memory cell array including memory cells, which are three-dimensionally arranged on a first substrate 100 . For example, the cell array structure CS may include the memory cell array 1 including the memory cells MC described with reference to FIG. 1 . The memory cell array may include horizontal patterns, which are sequentially stacked on the first substrate 100 , vertical patterns, which are provided to vertically cross the horizontal patterns, and memory elements, which are interposed between the horizontal and vertical patterns. For example, the horizontal patterns may be provided in a first direction D 1 and/or a second direction D 2 , and the vertical patterns may be provided in a third direction D 3 , as discussed later. However, this is only an example.

The peripheral circuit structure PS may include core and peripheral circuits, which are formed on a second substrate 200 . The core and peripheral circuits may include the row and column decoders 2 and 4 , the sensing amplifier (Sense Amp) 3 , and the control logic 5 described with reference to FIG. 1 .

Lower metal pads LMP may be provided at the topmost level of the cell array structure CS. The lower metal pads LMP may be electrically connected to the memory cell array. Upper metal pads UMP may be provided at the topmost level of the peripheral circuit structure PS. The upper metal pads UMP may be electrically connected to the core and peripheral circuits.

The lower and upper metal pads LMP and UMP may have substantially the same size and arrangement. The lower and upper metal pads LMP and UMP may be formed of or include at least one of, for example, copper (Cu), aluminum (Al), nickel (Ni), cobalt (Co), tungsten (W), titanium (Ti), tin (Sn), or alloys thereof.

According to an example embodiment, the three-dimensional semiconductor memory device may be fabricated by forming the cell array structure CS including the memory cells, which are three-dimensionally arranged on the first substrate 100 , forming the peripheral circuit structure PS including the core and peripheral circuits, which are formed on the second substrate 200 different from the first substrate 100 , and then, connecting the first substrate 100 to the second substrate 200 in a bonding manner. That is, the lower metal pads LMP of the cell array structure CS and the upper metal pads UMP of the peripheral circuit structure PS may be electrically and physically connected to each other in the bonding manner. In other words, the lower metal pads LMP may be in direct contact with the upper metal pads UMP.

FIG. 3 is a perspective view schematically illustrating a three-dimensional semiconductor memory device according to an example embodiment.

Referring to FIG. 3 , the cell array structure CS may include a memory cell array region MCA and a first peripheral region PR 1 . The peripheral circuit structure PS may include a first core region CR 1 , a second core region CR 2 , and a second peripheral region PR 2 . The first and second core regions CR 1 and CR 2 may be overlapped with the memory cell array region MCA, when viewed in a plan view. The first peripheral region PR 1 may be provided at a side of the memory cell array region MCA, and the second peripheral region PR 2 may be provided at a side of the second core region CR 2 . The second peripheral region PR 2 may be overlapped with the first peripheral region PR 1 , when viewed in a plan view.

A memory cell array including three-dimensionally arranged memory cells may be provided in the memory cell array region MCA. In other words, word and bit lines, which are disposed to cross each other, and memory cells, which are disposed between the word and bit lines, may be provided in the memory cell array region MCA.

A plurality of sense amplifiers may be provided in the first core region CR 1 , and a plurality of sub-word line drivers may be provided in the second core region CR 2 .

A control signal generating circuit that controls the sub-word line driver and a control signal generating circuit that controls the sense amplifier may be provided in the first and second peripheral regions PR 1 and PR 2 . In addition, voltage generators that provide operation voltages to the sense amplifier and the sub-word line driver may be disposed in the first and second peripheral regions PR 1 and PR 2 .

FIG. 4 is a sectional view schematically illustrating an example of a cell array structure and a peripheral circuit structure that are disposed in a three-dimensional semiconductor memory device according to an example embodiment.

Referring to FIG. 4 , in the cell array structure CS, the memory cell array region may include a bit-line connection region BLB and word-line connection regions WLB, which are provided at both sides of the bit-line connection region BLB.

The cell array structure CS may include the word lines WL, which are provided to be parallel to a top surface of the first substrate 100 , and the bit lines BL, which are provided to be perpendicular to the top surface of the first substrate 100 . The memory cells MC may be provided at respective intersections of the word and bit lines WL and BL.

The bit lines BL may be provided in the bit-line connection region BLB, and the word lines WL may be extended from the bit-line connection region BLB to the word-line connection regions WLB.

The cell array structure CS may include first lower metal pads LMP 1 , which are provided in the bit-line connection region BLB, and second lower metal pads LMP 2 , which is provided in the word-line connection regions WLB. The first lower metal pads LMP 1 may be electrically connected to the bit lines BL, and the second lower metal pads LMP 2 may be electrically connected to the word lines WL.

The peripheral circuit structure PS may include the first core region CR 1 and the second core regions CR 2 , which are provided at both sides of the first core region CR 1 as shown in the example illustrated in FIG. 4 . When viewed in a plan view, the first core region CR 1 may be overlapped with the bit-line connection region BLB, and the second core regions CR 2 may be overlapped with the word-line connection regions WLB, respectively.

A plurality of sense amplifiers SA 0 -SAn may be provided in the first core region CR 1 , and each of the sense amplifiers SA 0 -SAn may be provided corresponding to a pair of the bit lines BL. That is, each of the sense amplifiers SA 0 -San may be provided corresponding to two of the bit lines BL. A plurality of sub-word line drivers SWD 0 -SWDn may be provided in each of the second core regions CR 2 .

The peripheral circuit structure PS may include first upper metal pads UMP 1 , which are provided in the first core region CR 1 , and second upper metal pads UMP 2 , which are provided in the second core regions CR 2 . The first upper metal pads UMP 1 may be connected to the sense amplifiers SA 0 -SAn, and the second upper metal pads UMP 2 may be connected to the sub-word line drivers SWD 0 -SWDn.

The first upper metal pads UMP 1 may be directly connected to the first lower metal pads LMP 1 , and the second upper metal pads UMP 2 may be directly connected to the second lower metal pads LMP 2 . The first upper metal pads UMP 1 may have substantially the same size and arrangement as the first lower metal pads LMP 1 . The second upper metal pads UMP 2 may have substantially the same size and arrangement as the second lower metal pads LMP 2 . The first and second lower and upper metal pads LMP 1 , LMP 2 , UMP 1 , and UMP 2 may include the same metallic material and may have substantially the same size or area. The first and second lower and upper metal pads LMP 1 , LMP 2 , UMP 1 , and UMP 2 may be formed of or include at least one of, for example, copper (Cu), aluminum (Al), nickel (Ni), cobalt (Co), tungsten (W), titanium (Ti), tin (Sn), or alloys thereof.

FIGS. 5A and 5B are plan views illustrating a cell array structure of a three-dimensional semiconductor memory device according to example embodiments. FIGS. 6A and 6B are sectional views, each of which illustrates sections taken along lines I-I′, II-II′, and III-III′ of FIGS. 5A and 5B , respectively. FIG. 7 is a diagram exemplarily illustrating a connection structure between bit lines and bit-line connection lines in a three-dimensional semiconductor memory device according to an example embodiment. FIG. 8 is a diagram exemplarily illustrating a connection structure between bit lines and lower metal pads in a three-dimensional semiconductor memory device according to an example embodiment.

Referring to FIGS. 5A and 6A , the cell array structure of the three-dimensional semiconductor memory device may include the bit-line connection region BLB and the word-line connection region WLB.

Word line structures may be disposed on the first substrate 100 , and in an example embodiment, the word line structures may include the word lines WL, which are vertically stacked on the first substrate 100 . The first substrate 100 may be formed of or include a semiconductor material. For example, the first substrate 100 may be a single crystalline silicon substrate or a silicon-on-insulator (SOI) substrate.

The word line structures may be extended from the bit-line connection region BLB to the word-line connection region WLB. The word line structures may be extended in the first direction D 1 and may be spaced apart from each other the second direction D 2 crossing the first direction D 1 . The first and second directions D 1 and D 2 may be parallel to the top surface of the first substrate 100 .

Each of the word line structures may include interlayer insulating layers and the word lines WL, which are alternately stacked in the third direction D 3 (i.e., a vertical direction) that is perpendicular to the first and second directions D 1 and D 2 .

Referring to FIG. 5A , a pair of the word line structures may be connected to each other in the bit-line connection region BLB. For example, two of the word lines WL, which are located at the same level, may be connected to each other in the bit-line connection region BLB.

Word-line pads WLP may be provided in the word-line connection region WLB. Each of the word-line pads WLP may be shared in common by a corresponding pair of the word lines WL. The word-line pads WLP may be stacked on the first substrate 100 such that the word-line pads WLP form a stepwise structure in the word-line connection region WLB. The word-line pads WLP may be placed at positions that are horizontally and vertically different from each other.

In another example embodiment, each word line in each of the word line structures may have the word-line pad WLP in the word-line connection region WLB, as shown in FIG. 5B . For example, the word-line pads WLP, which are located at the same level and are adjacent to each other in the second direction D 2 , may be spaced apart from each other. Each of the word line structures may have a stepwise structure in the word-line connection region WLB, and the stepwise structure may include the word-line pads WLP of the word lines WL, which are located at different levels.

As illustrated in FIGS. 5A and 5B , each of the word lines WL may include a line portion, which is extended in the first direction D 1 , and gate electrode portions GE, which are extended from the line portion in the second direction D 2 to have a protruding shape. When viewed in a plan view, each pair of the word lines WL may be provided such that the gate electrode portions GE thereof have the mirror symmetry. The word lines WL may be formed of or include at least one of doped semiconductor materials (e.g., doped silicon, doped germanium, and so forth), conductive metal nitrides (e.g., titanium nitride, tantalum nitride, and so forth), metallic materials (e.g., tungsten, titanium, tantalum, and so forth), or metal-semiconductor compounds (e.g., tungsten silicide, cobalt silicide, titanium silicide, and so forth).

Semiconductor patterns SP, which are three-dimensionally arranged, may be disposed in the bit-line connection region BLB. The semiconductor patterns SP may be stacked in the third direction D 3 and may be spaced apart from each other in both of the first and second directions D 1 and D 2 .

Each of the semiconductor patterns SP may be a bar-shaped pattern, which is elongated in the second direction D 2 . Each of the semiconductor patterns SP may include a first end portion and a second end portion, which are spaced apart from each other, and a channel portion, which is provided between the first and second end portions. The semiconductor patterns SP may be formed of or include at least one of silicon or germanium. The first and second end portions of each semiconductor pattern SP may be doped with impurities. In an example embodiment, the semiconductor patterns SP may be formed of or include an oxide semiconductor material. As an example, the oxide semiconductor material may include at least one of indium (In), gallium (Ga), zinc (Zn), or tin (Sn). The oxide semiconductor material may be indium-gallium-zinc-oxide (IGZO) containing indium (In), gallium (Ga), and zinc (Zn).

The semiconductor patterns SP may be respectively provided to penetrate the gate electrode portions GE of the word lines WL in the second direction D 2 . Each word line WL may be provided to fully surround the channel portion of the semiconductor pattern SP (for example, to have a gate-all-around structure). Gate insulating layers GI may be interposed between the channel portions of the semiconductor patterns SP and the word lines WL.

In the bit-line connection region BLB, the bit lines BL may be extended in the third direction D 3 to cross the word line structures. The bit lines BL may have substantially the same length, when measured in the third direction D 3 . The bit lines BL may be arranged to be spaced apart from each other in the first and second directions D 1 and D 2 .

A lower insulating layer 101 may be disposed between the bit lines BL and the first substrate 100 . Each of the bit lines BL may be connected to the first end portions of the semiconductor patterns SP, which are stacked in the third direction D 3 . The bit lines BL may be formed of or include at least one of doped semiconductor materials (e.g., doped silicon, doped germanium, and so forth), conductive metal nitrides (e.g., titanium nitride, tantalum nitride, and so forth), metallic materials (e.g., tungsten, titanium, tantalum, and so forth), or metal-semiconductor compounds (e.g., tungsten silicide, cobalt silicide, titanium silicide, and so forth).

The data storing element CAP may be connected to the second end portion of each semiconductor pattern SP. In an example embodiment, the data storing element CAP may be a capacitor. In other words, a storage electrode SE of the capacitor may be connected to the second end portion of each semiconductor pattern SP.

Referring to FIG. 6A , the data storing elements CAP may be provided at substantially the same level as the semiconductor patterns SP. In other words, the storage electrodes SE may be stacked in the third direction D 3 and may be elongated in the second direction D 2 . In some example embodiments, the storage electrode SE of each data storing element CAP may have a hollow cylinder shape. Alternatively, in other example embodiments, the storage electrode SE may be a pillar-shaped pattern, which is elongated in the second direction D 2 . The storage electrode SE may be formed of or include at least one of metallic materials, metal nitrides, or metal silicides.

A dielectric layer IL may be provided to conformally cover a surface of each storage electrode SE, and a plate electrode PE may be provided on the dielectric layer IL. The plate electrode PE may be provided to cover inner and outer surfaces of the storage electrode SE provided with the dielectric layer IL. The dielectric layer IL may be formed of or include at least one of metal oxides (e.g., hafnium oxide, zirconium oxide, aluminum oxide, lanthanum oxide, tantalum oxide, and titanium oxide) or perovskite dielectric materials (e.g., SrTiO 3 (STO), (Ba,Sr)TiO 3 (BST), BaTiO 3 , PZT, and PLZT).

The plate electrode PE may be provided to fill an inner space of the storage electrode SE provided with the dielectric layer IL. In addition, the plate electrode PE may be provided to cover an outer side surface of the storage electrode SE, and here, the dielectric layer IL may be interposed between the plate electrode PE and the storage electrode SE. The plate electrodes PE may be connected in common to a common conductive line CL. The common conductive line CL may be extended in the first and third directions D 1 and D 3 . In other words, the common conductive line CL may be connected in common to the plate electrodes PE, which are arranged in the first and third directions D 1 and D 3 . Furthermore, the plate electrodes PE, which are adjacent to each other in the second direction D 2 , may be connected in common to the common conductive line CL. In an example embodiment, the plate electrodes PE and the common conductive line CL may be formed at the same time and may be formed of the same material, without any internal interface.

According to the embodiment shown in FIG. 6B , each data storing element CAP may include a first storage electrode SE 1 , which is in contact with a top surface of the second end portion of the semiconductor pattern SP, and a second storage electrode SE 2 , which is in contact with a bottom surface of the second end portion of the semiconductor pattern SP. In other words, the second end portion of the semiconductor pattern SP may be disposed between the first and second storage electrodes SE 1 and SE 2 in the third direction D 3 .

The dielectric layer IL may be provided to conformally cover surfaces of the first and second storage electrodes SE 1 and SE 2 . The plate electrode PE may be provided to fill inner spaces of the first and second storage electrodes SE 1 and SE 2 provided with the dielectric layer IL. In addition, the plate electrode PE may be provided to cover outer side surfaces of the first and second storage electrodes SE 1 and SE 2 .

Referring back to FIGS. 6A and 6B , bit line contact plugs BCP may be coupled to the bit lines BL, respectively. Bit-line connection lines BCL may be extended in the second direction D 2 to be parallel to each other and may be connected to the bit lines BL through the bit line contact plugs BCP.

The connection structure between the bit lines BL and the bit-line connection lines BCL will be described in more detail with reference to FIG. 7 .

FIG. 7 is a diagram exemplarily illustrating a connection structure between bit lines and bit-line connection lines in a three-dimensional semiconductor memory device according to an example embodiment. Although the semiconductor patterns and the data storing element are briefly illustrated in FIG. 7 , the semiconductor patterns and the data storing element may be substantially the same as those described with reference to FIGS. 5A, 5B, 6A , and 6 B.

Referring to FIG. 7 , two columns of the bit lines BL may be disposed between each pair of the word lines WL. The bit lines BL may include first and second bit lines BL 0 and BL 1 , which are alternately arranged in the second direction D 2 .

The bit-line connection lines BCL may be extended in the second direction D 2 to cross the word lines WL and the common conductive line CL. Two or more bit-line connection lines BCL may cross the first and second bit lines BL 0 and BL 1 , when viewed in a plan view. For example, two or more bit-line connection lines BCL 0 -BCL 7 may be overlapped with each of the bit lines BL.

The bit-line connection lines BCL may include odd-numbered bit-line connection lines BCL 1 , BCL 3 , BCL 5 , and BCL 7 and even-numbered bit-line connection lines BCL 0 , BCL 2 , BCL 4 , and BCL 6 , which are alternately arranged in the first direction D 1 . In an example embodiment, dummy connection lines may be respectively provided between the odd-numbered bit-line connection lines BCL 1 , BCL 3 , BCL 5 , and BCL 7 and the even-numbered bit-line connection lines BCL 0 , BCL 2 , BCL 4 , and BCL 6 .

Each of the odd-numbered bit-line connection lines BCL 1 , BCL 3 , BCL 5 , and BCL 7 may be connected to the first bit lines BL 0 , which are arranged in the second direction D 2 , through the bit line contact plugs BCP.

Each of the even-numbered bit-line connection lines BCL 0 , BCL 2 , BCL 4 , and BCL 6 may be connected to the second bit lines BL 1 , which are arranged in the second direction D 2 , through the bit line contact plugs BCP.

FIG. 8 is a diagram exemplarily illustrating a connection structure between bit lines and metal pads in a three-dimensional semiconductor memory device according to an example embodiment.

Referring to FIG. 8 , landing conductive patterns LP may be provided on the bit-line connection lines BCL 0 -BCL 7 . The landing conductive patterns LP may be extended in the first direction D 1 to cross the bit-line connection lines BCL 0 -BCL 7 and may be spaced apart from each other in the second direction D 2 , on the bit-line connection lines BCL 0 -BCL 7 . Each of the landing conductive patterns LP may be overlapped with a predetermined number of the bit-line connection lines BCL 0 -BCL 7 .

The first lower metal pads LMP 1 may be disposed on the landing conductive patterns LP, respectively. In some example embodiments, the first lower metal pads LMP may be connected to the landing conductive patterns LP through landing contact plugs. Alternatively, in other example embodiments, the first lower metal pads LMP 1 may be in direct contact with top surfaces of the landing conductive patterns LP. When measured in the second direction D 2 , each of the first lower metal pads LMP 1 may have a second width Wb, which is greater than a first width Wa of the landing conductive pattern LP. When measured in the second direction D 2 , a distance between adjacent ones of the first lower metal pads LMP 1 may be smaller than a distance between adjacent ones of the landing conductive patterns LP. When measured in the first direction D 1 , each of the first lower metal pads LMP 1 may have a second length that is smaller than a first length of the landing conductive patterns LP.

According to various example embodiments, each of the first upper metal pads UMP 1 of the peripheral circuit structure PS, which were described with reference to FIG. 4 , may be bonded to a corresponding one of the first lower metal pads LMP 1 shown in FIG. 8 .

FIG. 9 is a plan view schematically illustrating a three-dimensional semiconductor memory device according to an example embodiment. FIG. 10 is a diagram illustrating a connection structure between the cell array structure and the peripheral circuit structure in a region A of FIG. 9 . FIGS. 11A and 11B are diagrams illustrating connection structures between the cell array structure and the peripheral circuit structure in a region B of FIG. 9 , according to various example embodiments.

Referring to FIGS. 9, 10, and 11A , the three-dimensional semiconductor memory device according to an example embodiment may include a plurality of memory blocks, which are disposed in the second direction D 2 . As an example, the three-dimensional semiconductor memory device may include a first memory block MB 1 and a second memory block MB 2 .

Each of the first and second memory blocks MB 1 and MB 2 may include the cell array structure CS, which includes the bit-line connection region BLB and the word-line connection region WLB, and the peripheral circuit structure PS, which includes the first and second core regions CR 1 and CR 2 , as described above. When viewed in a plan view, the first core region CR 1 may be overlapped with the bit-line connection region BLB, and the second core region CR 2 may be overlapped with the word-line connection region WLB. In the first core region CR 1 , sense amplifiers SA may be overlapped with a portion of the bit-line connection region BLB of each of the memory blocks MB 1 and MB 2 , when viewed in a plan view.

The bit lines BL, the bit-line connection lines BCL, the landing conductive patterns LP, and the lower metal pads LMP 1 and LMP 2 of the cell array structure may be provided in each of the first and second memory blocks MB 1 and MB 2 , as previously described with reference to FIGS. 5, 6A, 6B, 7, and 8 . In addition, the upper metal pads UMP 1 and UMP 2 of the peripheral circuit structure PS may be provided to correspond to the lower metal pads LMP 1 and LMP 2 .

In the bit-line connection region BLB, the first lower and upper metal pads LMP 1 and UMP 1 may be arranged to be spaced apart from each other by constant distances in the first and second directions D 1 and D 2 . However, this is only an example and in some example embodiments, the distances in the first and second directions D 1 and D 2 may be varied. In the word-line connection region WLB, the second lower and upper metal pads LMP 2 and UMP 2 may be arranged to be spaced apart from each other by constant distances in the first and second directions D 1 and D 2 . However, this is only an example and in some example embodiments, the distances in the first and second directions D 1 and D 2 may be varied. In addition, the first lower and upper metal pads LMP 1 and UMP 1 may have substantially the same size and area as each other, and the second lower and upper metal pads LMP 2 and UMP 2 may have substantially the same size and area as each other. In some example embodiments, the size and/or area of some or all of the first lower and upper metal pads LMP 1 and UMP 1 may be different than a size and/or area of some or all of the second lower and upper metal pads LMP 2 and UMP 2 .

Referring to FIGS. 9 and 10 , bit-line connection lines BCL 0 a -BCL 7 a of the first memory block MB 1 may be spaced apart from bit-line connection lines BCL 0 b -BCL 7 b of the second memory block MB 2 . In other words, the bit-line connection lines BCL 0 a -BCL 7 a of the first memory block MB 1 may be separated from the bit-line connection lines BCL 0 b -BCL 7 b of the second memory block MB 2 .

As an example, even-numbered sense amplifiers SA 0 , SA 2 , SA 4 , and SA 6 may be provided in the first memory block MB 1 , and odd-numbered sense amplifiers SA 1 , SA 3 , SA 5 , and SA 7 may be provided in the second memory block MB 2 . The bit-line connection lines BCL 0 a -BCL 7 a and BCL 0 b -BCL 7 b of the first and second memory blocks MB 1 and MB 2 , which are adjacent to each other, may share the sense amplifiers SA 0 -SA 7 .

Referring to FIGS. 9 and 11A , as previously described with reference to FIG. 5A , the word line structures of the cell array structure may be provided so that a pair of the word lines WL, which are located at the same level, share a corresponding one of the word-line pads. The number of the word-line pads WLP may be equal to the stacking number of the word lines WL. A sub-word line driver SWD may be provided to correspond to each word-line pad WLP. In other words, the sub-word line drivers SWD may be electrically connected to the word-line pads WLP, respectively, through the second lower and upper metal pads UMP 1 and UMP 2 .

Each of the second lower and upper metal pads UMP 1 and UMP 2 may have a second width W 2 that is larger than a first width W 1 of the word-line pad WLP. The first lower and upper metal pads LMP 1 and UMP 1 may be arranged at a first pitch, and the second lower and upper metal pads LMP 2 and UMP 2 may be arranged at a second pitch that is substantially the same as the first pitch.

Referring to FIGS. 9 and 11B , in each of the word line structures of the cell array structure, the word-line pads WLP may be provided on the word lines, respectively, as previously described with reference to FIG. 5B . For example, the word-line pads WLP of the word line structures, which are adjacent to each other in the second direction D 2 , may be spaced apart from each other in the second direction D 2 . A word-line landing pad WLLP may be provided to correspond to a pair of the word-line pads WLP, which are adjacent to each other in the second direction D 2 . The number of the word-line landing pads WLLP may be equal to the stacking number of the word lines WL. The word-line landing pads WLLP may be located at substantially the same level as the landing conductive patterns LP described with reference to FIG. 8 . The word-line landing pads WLLP may be formed of or include the same conductive material as the landing conductive patterns LP. The word-line landing pads WLLP may be electrically connected to the word-line pads WLP through word line contact plugs WPLG. The sub-word line driver SWD may be provided to correspond to each of the word-line landing pads WLLP. FIG. 12 is a sectional view illustrating a three-dimensional semiconductor memory device according to an example embodiment.

Referring to FIG. 12 , the three-dimensional semiconductor memory device according to an example embodiment may include the cell array structure CS and the peripheral circuit structure PS, as described above. The cell array structure CS may include memory cells, which are three-dimensionally arranged on the first substrate 100 , and the peripheral circuit structure PS may include core and peripheral circuits, including sense amplifiers SA, sub-line word drivers SWD, and upper control circuits PP, which are formed on the second substrate 200 and are used to control a memory cell array.

A detailed structure of the memory cell array has been described with reference to FIGS. 5, 6A, 6B, 7, and 8 , and thus, only the bit lines BL and the word lines WL of the cell array structure CS are briefly illustrated in FIG. 12 .

In detail, the cell array structure CS may include the bit-line connection region BLB, the word-line connection regions WLB, which are provided at both sides of the bit-line connection region BLB, and the first peripheral region PR 1 .

The word lines WL may be stacked in the third direction D 3 that is perpendicular to the top surface of the first substrate 100 . The word lines WL may be provided on the bit-line connection region BLB and the word-line connection regions WLB. The word lines WL may be extended in the first direction D 1 that is parallel to the top surface of the first substrate 100 . Some of the word lines WL may have substantially the same length, when measured in the first direction D 1 .

The word-line pads WLP may be provided at opposite ends of each of the word lines WL. The word-line pads WLP may be stacked on the first substrate 100 such that they form a staircase structure in the word-line connection regions WLB. The word-line pads WLP may be placed at positions that are horizontally and vertically different from each other.

The bit lines BL may be extended in the third direction D 3 to cross the word lines WL in the bit-line connection region BLB. The semiconductor pattern SP (e.g., see FIGS. 5A and 5B ) and the capacitor CAP (e.g., see FIGS. 5A and 5B ) may be provided at each intersection of the word and bit lines WL and BL. The bit lines BL may have substantially the same length, when measured in the third direction D 3 .

The bit-line connection line BCL may be coupled to each bit line BL through the bit line contact plug BCP, as described above. A first lower metal pattern LM 1 may be disposed on the bit lines BL. Each of the bit lines BL may be electrically connected to the first lower metal pad LMP 1 through the first lower metal pattern LM 1 . The first lower metal pattern LM 1 may include at least two metal patterns, which are stacked vertically and are connected to each other. In an example embodiment, the first lower metal pattern LM 1 may include the bit-line connection lines BCL and the landing conductive patterns LP described above.

In the word-line connection regions WLB, the word line contact plugs WPLG may be coupled to the word-line pads WLP, respectively. A second lower metal pattern LM 2 may be coupled to the word line contact plugs WPLG. The second lower metal pattern LM 2 may include at least two metal patterns, which are stacked vertically and are connected to each other. Although the second lower metal pattern LM 2 is illustrated to be coupled to one word line contact plug WPLG by way of illustration in order to provide a clear figure, it will be understood that the second lower metal patterns LM 2 may be respectively coupled to the word line contact plugs WPLG. Each of the word-line pads WLP may be electrically connected to the second lower metal pad LMP 2 via the word line contact plug WPLG and the second lower metal pattern LM 2 .

In an example embodiment, a power capacitor PC, which is used as a part of a lower control circuit controlling the sense amplifiers and the sub-word line drivers, may be provided in the first peripheral region PR 1 of the cell array structure CS. The power capacitor PC may constitute a voltage generator, which receives a power voltage supplied through an input/output pad TOP and outputs operation voltages to operate the memory cell array. In detail, the power capacitor PC may be a metal-insulator-metal (MIM) capacitor, which includes a first electrode M 1 and a second electrode M 2 on the first substrate 100 and a dielectric layer MI therebetween. A third lower metal pattern LM 3 may be coupled to the power capacitor PC, and the third lower metal pattern LM 3 may include at least two metal patterns, which are stacked vertically and are connected to each other. The power capacitor PC may be electrically connected to a third lower metal pad LMP 3 through the third lower metal pattern LM 3 .

The first, second, and third lower metal patterns LM 1 , LM 2 , and LM 3 may be located at substantially the same level and may be formed of or include the same metallic material (hereinafter, a first metallic material). The first, second, and third lower metal pads LMP 1 , LMP 2 , and LMP 3 may be located at substantially the same level and may be formed of or include the same metallic material (hereinafter, a second metallic material). In some example embodiments, the upper surfaces of the first, second, and third lower metal pads LMP 1 , LMP 2 , and LMP 3 may be coplanar. The second metallic material may be different from the first metallic material.

The peripheral circuit structure PS may include the core and peripheral circuits SA, SWD, and PP, which are formed on the second substrate 200 and are used to control the memory cell array.

In detail, the peripheral circuit structure PS may include the first core region CR 1 , the second core region CR 2 , and the second peripheral region PR 2 .

The sense amplifiers SA may be provided in the first core region CR 1 . Each of the sense amplifiers SA may include NMOS and PMOS transistors, which are formed on the second substrate 200 , and may be electrically connected to a pair of the bit lines BL. Each sense amplifier SA may be configured to amplify a difference between voltages, which are sensed through the pair of the bit lines BL, and to provide the amplified voltage difference to a pair of local input/output lines.

Each sense amplifier SA may be electrically connected to a first upper metal pattern UM 1 . The first upper metal pattern UM 1 may include at least two metal patterns, which are stacked vertically and are connected to each other. Each sense amplifier SA may be electrically connected to the first upper metal pad UMP 1 through the first upper metal pattern UM 1 .

The sub-word line drivers SWD, which are used to drive the word lines WL, respectively, may be disposed in the second core region CR 2 . Each of the sub-word line drivers SWD may include NMOS and PMOS transistors. A second upper metal pattern UM 2 may be electrically connected to each of the sub-word line drivers SWD.

Each of the sub-word line drivers SWD may be electrically connected to the second upper metal pattern UM 2 . The second upper metal pattern UM 2 may include at least two metal patterns, which are stacked vertically and are connected to each other. Each of the sub-word line drivers SWD may be electrically connected to the second upper metal pad UMP 2 through the second upper metal pattern UM 2 .

Furthermore, the upper control circuits PP to control the sub-word line drivers SWD and the sense amplifiers SA may be disposed in in the second peripheral region PR 2 of the peripheral circuit structure PS. The upper control circuits PP may be electrically connected to a third upper metal pattern UM 3 . The third upper metal pattern UM 3 may include at least two metal patterns, which are stacked vertically and are connected to each other. The upper control circuits PP may be electrically connected to third upper metal pads UMP 3 through the third upper metal pattern UM 3 .

The input/output pad TOP may be disposed in the second peripheral region PR 2 of the peripheral circuit structure PS. In detail, a passivation layer 201 may be disposed on a bottom surface of the second substrate 200 , and the input/output pad TOP may be disposed on the passivation layer 201 . The input/output pad TOP may be coupled to a portion of the third upper metal pattern UM 3 through a penetration plug TSV penetrating the second substrate 200 . A sidewall insulating layer TSI may be disposed between a sidewall of the penetration plug TSV and the second substrate 200 . The input/output pad TOP may be electrically connected to the upper control circuits PP through the penetration plug TSV and the third upper metal pattern UM 3 .

The first, second, and third upper metal patterns UM 1 , UM 2 , and UM 3 may be located at substantially the same level and may be formed of or include the same metallic material (hereinafter, a first metallic material). The first, second, and third upper metal pads UMP 1 , UMP 2 , and UMP 3 may be located at substantially the same level and may be formed of or include the same metallic material (hereinafter, a second metallic material). In some example embodiments, lower surfaces of the first, second, and third upper metal pads UMP 1 , UMP 2 , and UMP 3 may be coplanar. The second metallic material may be different from the first metallic material.

The first, second, and third upper metal pads UMP 1 , UMP 2 , and UMP 3 may be in direct contact with the first, second, and third lower metal pads LMP 1 , LMP 2 , and LMP 3 . The first, second, and third upper metal pads UMP 1 , UMP 2 , and UMP 3 may be formed of or include the same metallic material as the first, second, and third lower metal pads LMP 1 , LMP 2 , and LMP 3 . The first, second, and third upper metal pads UMP 1 , UMP 2 , and UMP 3 may have substantially the same width or the same area as the first, second, and third lower metal pads LMP 1 , LMP 2 , and LMP 3 .

FIGS. 13 to 16 are sectional views illustrating a three-dimensional semiconductor memory device according to various example embodiments. For concise description, an element previously described with reference to FIG. 12 may be identified by the same reference number without repeating an overlapping description thereof for conciseness.

Referring to FIG. 13 , the first, second, and third lower metal pads LMP 1 , LMP 2 , and LMP 3 of the cell array structure CS may have different sizes from the first, second, and third upper metal pads UMP 1 , UMP 2 , and UMP 3 . As an example, the sizes of the first, second, and third lower metal pads LMP 1 , LMP 2 , and LMP 3 may be smaller than the sizes of the first, second, and third upper metal pads UMP 1 , UMP 2 , and UMP 3 .

Referring to FIG. 14 , the cell array structure CS may be bonded to the peripheral circuit structure PS in such a way that the first, second, and third lower metal pads LMP 1 , LMP 2 , and LMP 3 are slightly misaligned from the first, second, and third upper metal pads UMP 1 , UMP 2 , and UMP 3 . For example, portions of the first, second, and third lower metal pads LMP 1 , LMP 2 , and LMP 3 may be in direct contact with portions of the first, second, and third upper metal pads UMP 1 , UMP 2 , and UMP 3 .

Referring to FIG. 15 , the input/output pad IOP may be disposed in the first peripheral region PR 1 of the cell array structure CS. In detail, a passivation layer 102 may be disposed on a bottom surface of the first substrate 100 , and the input/output pad IOP may be disposed on the passivation layer 102 . The input/output pad IOP may be coupled to a portion of the third lower metal pattern LM 3 through the penetration plug TSV penetrating the first substrate 100 . The sidewall insulating layer TSI may be disposed between a sidewall of the penetration plug TSV and the first substrate 100 . The input/output pad IOP may be electrically connected to the lower control circuits (e.g., the power capacitor PC) through the penetration plug TSV and the third lower metal pattern LM 3 .

Referring to FIG. 16 , a lower input/output pad IOPa may be disposed on a rear surface of the first substrate 100 and in the first peripheral region PR 1 . An upper input/output pad IOPb may be disposed on a rear surface of the second substrate 200 and in the second peripheral region PR 2 .

A lower penetration plug TSVa may be provided to penetrate the first substrate 100 and to connect the third lower metal pattern LM 3 to the lower input/output pad IOPa. The upper penetration plug TSVb may be provided to penetrate the second substrate 200 and to connect the third upper metal pattern UM 3 to the upper input/output pad IOPb. A lower sidewall insulating layer TSIa may be provided to enclose a sidewall of the lower penetration plug TSVa, and an upper sidewall insulating layer TSIb may be provided to enclose a sidewall of the upper penetration plug TSVb.

In the example embodiments described with reference to FIGS. 12 to 16 , the power capacitor PC is illustrated to be provided on the first substrate 100 , but example embodiments are not limited to this example. For example, in some example embodiments, the power capacitor PC may be provided on the second substrate 200 , and the peripheral circuit PP may be provided on the first substrate 100 .

FIGS. 17 to 22 are diagrams illustrating an example of lower and upper metal pads that are arranged in a three-dimensional semiconductor memory device according to various example embodiments. FIGS. 17 to 22 illustrate examples of second lower and upper metal pads, which are arranged in the word-line connection region of the three-dimensional semiconductor memory device according to an example embodiment. Although only the word-line connection region is illustrated in FIGS. 17 to 22 , the first lower and upper metal pads in the bit-line connection region may be provided to have a similar arrangement to the second lower and upper metal pads to be described with reference to FIGS. 17 to 22 .

In detail, referring to FIGS. 17 to 22 , the word-line pads WLP may be arranged to form a stepwise structure in the word-line connection region WLB, as previously described with reference to FIG. 12 . The word-line pads WLP may be arranged in the first direction D 1 and may be spaced apart from each other in the second direction D 2 , when viewed in a plan view. The word line contact plugs WPLG may be coupled to the word-line pads WLP, respectively.

As described above, the second lower and upper metal pads LMP 2 and UMP 2 may be electrically connected to the word-line pads WLP, respectively, through the word line contact plugs WPLG. In some example embodiments, the second lower and upper metal pads LMP 2 and UMP 2 may be connected to the word line contact plugs WPLG in a one-to-one manner. However, in other example embodiments, some the second lower and upper metal pads LMP 2 and UMP 2 may be connected to multiple word line contact plugs WPLG, as illustrated in FIG. 19 . An area of each of the second lower and upper metal pads LMP 2 and UMP 2 may be larger than an area of the word line contact plug WPLG.

Each of the second lower and upper metal pads LMP 2 and UMP 2 may have a square or rectangular shape, as shown in FIGS. 17, 18, and 19 . Alternatively, each of the second lower and upper metal pads LMP 2 and UMP 2 may have a circular shape, as shown in FIGS. 20 and 21 . Alternatively, each of the second lower and upper metal pads LMP 2 and UMP 2 may have a hexagonal shape, as shown in FIG. 22 .

Referring to FIG. 17 , when viewed in a plan view, the word line contact plugs WPLG may be arranged to be spaced apart from each other in the first and second directions D 1 and D 2 , and the second lower and upper metal pads LMP 2 and UMP 2 may be arranged to be spaced apart from each other in a direction, which is diagonal to the first and second directions D 1 and D 2 . Portions of the second lower and upper metal pads LMP 2 and UMP 2 may be in contact with the word line contact plugs WPLG, respectively.

Referring to FIG. 18 , the second lower and upper metal pads LMP 2 and UMP 2 may be provided to have substantially the same arrangement as the word line contact plugs WPLG. In other words, the second lower and upper metal pads LMP 2 and UMP 2 may be arranged to be spaced apart from each other in the first and second directions D 1 and D 2 , and a distance between the second lower and upper metal pads LMP 2 and UMP 2 may be smaller than a distance between the word line contact plugs WPLG.

Referring to FIG. 19 , the second lower and upper metal pads LMP 2 and UMP 2 may be arranged to be spaced apart from each other in a direction, which is diagonal to the first and second directions D 1 and D 2 . Some of the second lower and upper metal pads LMP 2 and UMP 2 may not be overlapped with the word line contact plugs WPLG. Such ones of the second lower and upper metal pads LMP 2 and UMP 2 , which are not overlapped with the word line contact plugs WPLG, may be connected to with the word line contact plugs WPLG through interconnection lines ICL.

Referring to FIG. 20 , the second lower and upper metal pads LMP 2 and UMP 2 may be arranged in a honeycomb shape but may not be overlapped with the word line contact plugs WPLG, when viewed in a plan view. The second lower and upper metal pads LMP 2 and UMP 2 may be electrically connected to the word line contact plugs WPLG, respectively, through interconnection lines ICL.

Referring to FIG. 21 , the second lower and upper metal pads LMP 2 and UMP 2 may be arranged in a honeycomb shape, and portions of the second lower and upper metal pads LMP 2 and UMP 2 may be coupled to the word line contact plugs WPLG, respectively, when viewed in a plan view.

Referring to FIG. 22 , each of the second lower and upper metal pads LMP 2 and UMP 2 may be provided to have a hexagonal shape. The second lower and upper metal pads LMP 2 and UMP 2 may be arranged in a direction, which is diagonal to the first and second directions D 1 and D 2 , and portions of the second lower and upper metal pads LMP 2 and UMP 2 may be coupled to the word line contact plugs WPLG, respectively.

According to various example embodiments, a bit-line connection region of a cell array structure may be vertically overlapped with a first core region of a peripheral circuit structure, and a word-line connection region of the cell array structure may be vertically overlapped with a second core region of the peripheral circuit structure. Accordingly, it may be possible to shorten signal transmission paths between bit lines and sense amplifiers and between word lines and word line drivers.

Memory cells on a first substrate and core and peripheral circuits on a second substrate may be separately fabricated, and then the first substrate may be bonded to the second substrate. Accordingly, it may be possible to increase an integration density of a three-dimensional semiconductor memory device, to reduce thermal budget, which are applied on the core and peripheral circuits during a process of forming the memory cells, and to reduce sizes of transistors.

In addition, control circuits may be vertically disposed at a side of the first substrate including the memory cells and at a side of the second substrate including the core and peripheral circuits, and thus, an area occupied by the control circuits may be reduced.

While various example embodiments have been particularly shown and described, it will be understood by one of ordinary skill in the art that variations in form and detail may be made therein without departing from the spirit and scope of the attached claims.