Active rectifier bridge circuit and on-chip integrated system

The present invention relates to a power supply system, and in particular, to an active rectifier bridge circuit and an on-chip integrated system.

A rectifier bridge is widely applied to an alternating current power supply system and a non-polar power supply system, and the rectifier bridge is configured to convert an alternating current voltage or a non-polar voltage into a direct current voltage for output.

An off-chip rectifier bridge is generally applied to the alternating current power supply system and the non-polar power supply system. As shown in FIG. 1 , the off-chip rectifier bridge is composed of four discrete device diodes, or four diode chips sealed together. However, because of existence of inherent voltage drop (approximately 0.6 V) of the diodes, there is a large power loss in a rectification solution formed based on a plurality of diodes, and a system temperature rises sharply.

Therefore, to reduce the power loss and improve the system integration degree, the technology of a small power active on-chip integrated rectifier bridge becomes very necessary.

In view of the foregoing disadvantages in the prior art, an object of the present invention is to provide an active rectifier bridge circuit and an on-chip integrated system, to resolve the problem of a relatively large power loss and a relatively low system integration degree in an existing off-chip rectifier bridge composed of four diodes.

To achieve the foregoing object and other related objects, the present invention provides an active rectifier bridge circuit, comprising: a bias module, a gate driver module, and a power switch tube rectification module, wherein

the bias module is configured to provide a first bias current source, a second bias current source, and an internal power supply for the gate driver module;

the gate driver module is connected to the bias module, is controlled by the first bias current source, the second bias current source, and the internal power supply, and is configured to: process one group of alternating current input voltages to generate two groups of control signals that are mutually inverted, and generate four gate drive signals based on the two groups of control signals that are mutually inverted; and

the power switch tube rectification module is connected to the bias module and the gate driver module, comprises two NMOS power switch tubes and two PMOS power switch tubes, and is configured to: perform a turn-on or turn-off operation on corresponding power switch tubes under the control of the four gate drive signals, and convert the one group of alternating current input voltages into a direct current output voltage for output.

Optionally, the power switch tube rectification module comprises: a first NMOS power switch tube, a second NMOS power switch tube, a first PMOS power switch tube, a second PMOS power switch tube, a first pull-down resistor, a second pull-down resistor, a first pull-up resistor, and a second pull-up resistor, wherein a gate terminal of the first NMOS power switch tube is connected to a first output end of the gate driver module and one end of the first pull-down resistor, the other end of the first pull-down resistor is grounded, a source terminal of the first NMOS power switch tube is grounded, a drain terminal of the first NMOS power switch tube is connected to a drain terminal of the first PMOS power switch tube, and is used as a first input end of the power switch tube rectification module, a gate terminal of the second NMOS power switch tube is connected to a second output end of the gate driver module and one end of the second pull-down resistor, the other end of the second pull-down resistor is grounded, a source terminal of the second NMOS power switch tube is grounded, a drain terminal of the second NMOS power switch tube is connected to a drain terminal of the second PMOS power switch tube, and is used as a second input end of the power switch tube rectification module, a gate terminal of the first PMOS power switch tube is connected to a third output end of the gate driver module and one end of the first pull-up resistor, a gate terminal of the second PMOS power switch tube is connected to a fourth output end of the gate driver module and one end of the second pull-up resistor, and the other end of the first pull-up resistor is connected to a source terminal of the first PMOS power switch tube, the other end of the second pull-up resistor, a source terminal of the second PMOS power switch tube, the bias module, and the gate driver module, and is used as an output end of the power switch tube rectification module.

Optionally, the gate driver module comprises: an alternating current level determining unit, a gate drive unit of the PMOS power switch tube, and a gate drive unit of the NMOS power switch tube, wherein

the alternating current level determining unit is controlled by the internal power supply, and is configured to: compare a first alternating current input voltage with a second alternating current input voltage in the one group of alternating current input voltages, and perform logical operation processing on a comparison result and a delay of the comparison result, to generate two groups of control signals that are mutually inverted;

the gate drive unit of the PMOS power switch tube is connected to the alternating current level determining unit and the power switch tube rectification module, is controlled by the first bias current source, and is configured to: generate gate drive signals of the two PMOS power switch tubes under the control of the two groups of control signals that are mutually inverted; and

the gate drive unit of the NMOS power switch tube is connected to the alternating current level determining unit, the gate drive unit of the PMOS power switch tube, and the power switch tube rectification module, is controlled by the second bias current source, and is configured to: generate gate drive signals of the two NMOS power switch tubes under the control of the two groups of control signals that are mutually inverted and the gate drive signals of the two PMOS power switch tubes.

Optionally, the alternating current level determining unit comprises: a first alternating current level determining part and a second alternating current level determining part, wherein

the first alternating current level determining part comprises: a first comparator, a first delayer, a first NOR gate, and a first phase inverter, wherein an in-phase input end of the first comparator accesses the first alternating current input voltage, an inverting input end of the first comparator accesses the second alternating current input voltage, an output end of the first comparator is connected to an input end of the first delayer and a first input end of the first NOR gate, an output end of the first delayer is connected to a second input end of the first NOR gate, an output end of the first NOR gate is connected to an input end of the first phase inverter, and is used as a first output end of the alternating current level determining unit, and an output end of the first phase inverter is used as a second output end of the alternating current level determining unit; and

the second alternating current level determining part comprises: a second comparator, a second delayer, a second NOR gate, and a second phase inverter, wherein an in-phase input end of the second comparator accesses the second alternating current input voltage, an inverting input end of the second comparator accesses the first alternating current input voltage, an output end of the second comparator is connected to an input end of the second delayer and a first input end of the second NOR gate, an output end of the second delayer is connected to a second input end of the second NOR gate, an output end of the second NOR gate is connected to an input end of the second phase inverter, and is used as a third output end of the alternating current level determining unit, and an output end of the second phase inverter is used as a fourth output end of the alternating current level determining unit, wherein

a delay time of the first delayer is the same as a delay time of the second delayer, and the first NOR gate, the second NOR gate, the first phase inverter, and the second phase inverter are all controlled by the internal power supply.

Optionally, the gate drive unit of the PMOS power switch tube comprises: a PMOS voltage regulation part, a gate drive part of the first PMOS power switch tube, and a gate drive part of the second PMOS power switch tube, wherein

the PMOS voltage regulation part is configured to provide a first clamping voltage for the gate drive part of the first PMOS power switch tube and the gate drive part of the second PMOS power switch tube;

the gate drive part of the first PMOS power switch tube is connected to the PMOS voltage regulation part, the alternating current level determining unit, and the power switch tube rectification module, is controlled by the first bias current source, and is configured to: generate, based on the accessed direct current output voltage, a gate drive signal that turns off the first PMOS power switch tube, or generate, based on the accessed first clamping voltage, a gate drive signal that turns on the first PMOS power switch tube, under the control of one group of control signals that are mutually inverted and that are outputted by a third output end and a fourth output end of the alternating current level determining unit; and

the gate drive part of the second PMOS power switch tube is connected to the PMOS voltage regulation part, the alternating current level determining unit, and the power switch tube rectification module, is controlled by the first bias current source, and is configured to: generate, based on the accessed direct current output voltage, a gate drive signal that turns off the second PMOS power switch tube, or generate, based on the accessed first clamping voltage, a gate drive signal that turns on the second PMOS power switch tube, under the control of one group of control signals that are mutually inverted and that are outputted by a first output end and a second output end of the alternating current level determining unit.

Optionally, the PMOS voltage regulation part comprises a first voltage regulator tube, wherein a cathode terminal of the first voltage regulator tube accesses the direct current output voltage, and an anode terminal of the first voltage regulator tube is used as an output end of the PMOS voltage regulation part.

Optionally, the gate drive part of the first PMOS power switch tube comprises: a first NMOS tube, a second NMOS tube, a third NMOS tube, a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, and a sixth PMOS tube, wherein a source terminal of the first NMOS tube, a source terminal of the second NMOS tube, and a source terminal of the third NMOS tube are all grounded, a gate terminal of the first NMOS tube is connected to the fourth output end of the alternating current level determining unit, a drain terminal of the first NMOS tube is connected to a drain terminal of the first PMOS tube, a gate terminal of the second NMOS tube is connected to a gate terminal of the third NMOS tube, and is simultaneously connected to the third output end of the alternating current level determining unit, a drain terminal of the second NMOS tube is connected to a drain terminal of the second PMOS tube, a drain terminal of the third NMOS tube is connected to a drain terminal of the third PMOS tube, a gate terminal of the first PMOS tube, a gate terminal of the second PMOS tube, and a gate terminal of the third PMOS tube are all connected to an output end of the PMOS voltage regulation part, and are controlled by the first bias current source, a source terminal of the first PMOS tube is connected to a drain terminal of the fourth PMOS tube, a source terminal of the second PMOS tube is connected to a drain terminal of the fifth PMOS tube, a source terminal of the third PMOS tube is connected to a drain terminal of the sixth PMOS tube, and is used as an output end of the gate drive part of the first PMOS power switch tube, a source terminal of the fourth PMOS tube, a source terminal of the fifth PMOS tube, and a source terminal of the sixth PMOS tube all access the direct current output voltage, a gate terminal of the fourth PMOS tube is connected to the drain terminal of the fifth PMOS tube, a gate terminal of the fifth PMOS tube is connected to the drain terminal of the fourth PMOS tube, and a gate terminal of the sixth PMOS tube is connected to the source terminal of the first PMOS tube.

Optionally, the gate drive part of the second PMOS power switch tube comprises: a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube, a seventh PMOS tube, an eighth PMOS tube, a ninth PMOS tube, a tenth PMOS tube, an eleventh PMOS tube, and a twelfth PMOS tube, wherein a source terminal of the fourth NMOS tube, a source terminal of the fifth NMOS tube, and a source terminal of the sixth NMOS tube are all grounded, a gate terminal of the fourth NMOS tube is connected to the second output end of the alternating current level determining unit, a drain terminal of the fourth NMOS tube is connected to a drain terminal of the seventh PMOS tube, a gate terminal of the fifth NMOS tube is connected to a gate terminal of the sixth NMOS tube, and is simultaneously connected to the first output end of the alternating current level determining unit, a drain terminal of the fifth NMOS tube is connected to a drain terminal of the eighth PMOS tube, a drain terminal of the sixth NMOS tube is connected to a drain terminal of the ninth PMOS tube, a gate terminal of the seventh PMOS tube, a gate terminal of the eighth PMOS tube, and a gate terminal of the ninth PMOS tube are all connected to an output end of the PMOS voltage regulation part, and are controlled by the first bias current source, a source terminal of the seventh PMOS tube is connected to a drain terminal of the tenth PMOS tube, a source terminal of the eighth PMOS tube is connected to a drain terminal of the eleventh PMOS tube, a source terminal of the ninth PMOS tube is connected to a drain terminal of the twelfth PMOS tube, and is used as an output end of the gate drive part of the second PMOS power switch tube, a source terminal of the tenth PMOS tube, a source terminal of the eleventh PMOS tube, and a source terminal of the twelfth PMOS tube all access the direct current output voltage, a gate terminal of the tenth PMOS tube is connected to the drain terminal of the eleventh PMOS tube, a gate terminal of the eleventh PMOS tube is connected to the drain terminal of the tenth PMOS tube, and a gate terminal of the twelfth PMOS tube is connected to the source terminal of the seventh PMOS tube.

Optionally, the gate drive unit of the NMOS power switch tube comprises: an NMOS voltage regulation part, a gate drive part of the first NMOS power switch tube, and a gate drive part of the second NMOS power switch tube, wherein

the NMOS voltage regulation part is configured to provide a second clamping voltage for the gate drive part of the first NMOS power switch tube and the gate drive part of the second NMOS power switch tube;

the gate drive part of the first NMOS power switch tube is connected to the NMOS voltage regulation part, the alternating current level determining unit, the gate drive unit of the PMOS power switch tube, and the power switch tube rectification module, is controlled by the second bias current source, and is configured to: generate, based on the accessed second clamping voltage, a gate drive signal that turns off or on the first NMOS power switch tube, under the control of a control signal outputted by a second output end of the alternating current level determining unit and a gate drive signal of the second PMOS power switch tube outputted by the gate drive unit of the PMOS power switch tube; and

the gate drive part of the second NMOS power switch tube is connected to the NMOS voltage regulation part, the alternating current level determining unit, the gate drive unit of the PMOS power switch tube, and the power switch tube rectification module, is controlled by the second bias current source, and is configured to: generate, based on the accessed second clamping voltage, a gate drive signal that turns off or on the second NMOS power switch tube, under the control of a control signal outputted by a fourth output end of the alternating current level determining unit and a gate drive signal of the first PMOS power switch tube outputted by the gate drive unit of the PMOS power switch tube.

Optionally, the NMOS voltage regulation part comprises: a second voltage regulator tube, wherein an anode terminal of the second voltage regulator tube is grounded, and a cathode terminal of the second voltage regulator tube is used as an output end of the NMOS voltage regulation part.

Optionally, the gate drive part of the first NMOS power switch tube comprises: a thirteenth PMOS tube, a seventh NMOS tube, an eighth NMOS tube, a ninth NMOS tube, a tenth NMOS tube, a third pull-up resistor, a third voltage regulator tube, a fourth voltage regulator tube, and a third phase inverter, wherein a gate terminal of the thirteenth PMOS tube accesses the gate drive signal of the second PMOS power switch tube outputted by the gate drive unit of the PMOS power switch tube, a source terminal of the thirteenth PMOS tube accesses the direct current output voltage, a drain terminal of the thirteenth PMOS tube is connected to a drain terminal of the seventh NMOS tube, a gate terminal of the seventh NMOS tube is connected to an output end of the NMOS voltage regulation part, and is controlled by the second bias current source, a source terminal of the seventh NMOS tube is connected to a drain terminal of the eighth NMOS tube, a cathode terminal of the third voltage regulator tube, an input end of the third phase inverter, a gate terminal of the ninth NMOS tube, and one end of the third pull-up resistor, a gate terminal of the eighth NMOS tube is connected to a second output end of the alternating current level determining unit, a source terminal of the eighth NMOS tube is grounded, an anode terminal of the third voltage regulator tube is grounded, an output end of the third phase inverter is connected to a gate terminal of the tenth NMOS tube, a drain terminal of the ninth NMOS tube is connected to the other end of the third pull-up resistor, and simultaneously accesses the second alternating current input voltage, a source terminal of the ninth NMOS tube is connected to a cathode terminal of the fourth voltage regulator tube and a drain terminal of the tenth NMOS tube, and is used as an output end of the gate drive part of the first NMOS power switch tube, and a source terminal of the tenth NMOS tube is grounded.

Optionally, the gate drive part of the second NMOS power switch tube comprises: a fourteenth PMOS tube, an eleventh NMOS tube, a twelfth NMOS tube, a thirteenth NMOS tube, a fourteenth NMOS tube, a fourth pull-up resistor, a fifth voltage regulator tube, a sixth voltage regulator tube, and a fourth phase inverter, wherein a gate terminal of the fourteenth PMOS tube accesses the gate drive signal of the first PMOS power switch tube outputted by the gate drive unit of the PMOS power switch tube, a source terminal of the fourteenth PMOS tube accesses the direct current output voltage, a drain terminal of the fourteenth PMOS tube is connected to a drain terminal of the eleventh NMOS tube, a gate terminal of the eleventh NMOS tube is connected to an output end of the NMOS voltage regulation part, and is controlled by the second bias current source, a source terminal of the eleventh NMOS tube is connected to a drain terminal of the twelfth NMOS tube, a cathode terminal of the fifth voltage regulator tube, an input end of the fourth phase inverter, a gate terminal of the thirteenth NMOS tube, and one end of the fourth pull-up resistor, a gate terminal of the twelfth NMOS tube is connected to a fourth output end of the alternating current level determining unit, a source terminal of the twelfth NMOS tube is grounded, an anode terminal of the fifth voltage regulator tube is grounded, an output end of the fourth phase inverter is connected to a gate terminal of the fourteenth NMOS tube, a drain terminal of the thirteenth NMOS tube is connected to the other end of the fourth pull-up resistor, and simultaneously accesses the first alternating current input voltage, a source terminal of the thirteenth NMOS tube is connected to a cathode terminal of the sixth voltage regulator tube and a drain terminal of the fourteenth NMOS tube, and is used as an output end of the gate drive part of the second NMOS power switch tube, and a source terminal of the fourteenth NMOS tube is grounded.

The present invention further provides an on-chip integrated system, comprising: the active rectifier bridge circuit described above and a functional circuit connected to an output end of the active rectifier bridge circuit, wherein the active rectifier bridge circuit provides a working voltage for the functional circuit, and the active rectifier bridge circuit and the functional circuit are formed on the same silicon wafer.

As described above, according to the active rectifier bridge circuit and the on-chip integrated system consistent with the present invention, the existing diodes are replaced with the four power switch tubes for the design of the rectifier bridge, thereby greatly reducing the power loss. In addition, in the present invention, the gate driver module controls the switch drive and time sequence of the four power switch tubes, to implement dead-time control on turn-on/off of the four power switch tubes, so that the active rectifier bridge circuit consistent with the present invention implements a safe and reliable rectification function, and rectification efficiency of the active rectifier bridge circuit is significantly improved. The active rectifier bridge circuit consistent with the present invention is implemented by using conventional process devices. Therefore, the active rectifier bridge circuit can be produced on the same silicon wafer as the functional circuit, thereby improving the product integration degree, and helping implement product miniaturization and intelligence.

FIG. 1 is a specific circuit diagram of an existing off-clip rectifier bridge.

FIG. 2 is a circuit diagram of the active rectifier bridge circuit consistent with the present invention.

FIG. 3 is a specific circuit diagram of an alternating current level determining unit in the gate driver module consistent with the present invention.

FIG. 4 is a specific circuit diagram of a gate drive unit of a PMOS power switch tube in the gate driver module consistent with the present invention.

FIG. 5 is a specific circuit diagram of a gate drive unit of an NMOS power switch tube in the gate driver module consistent with the present invention.

FIG. 6 is a time sequence diagram of one group of alternating current input voltages (AC 1 and AC 2 ), two control signals (COMP 1 and COMP 2 ), and four gate drive signals (GATE_N 1 GATE_N 2 GATE_P 1 , and GATE_P 2 ) in the active rectifier bridge circuit consistent with the present invention.

FIG. 7 is a circuit diagram of the on-chip integrated system consistent with the present invention.

10 active rectifier bridge circuit;

100 bias module;

200 gate driver module;

201 alternating current level determining unit;

2011 first alternating current level determining part;

2012 second alternating current level determining part;

202 gate drive unit of a PMOS power switch tube;

2021 PMOS voltage regulation part;

2022 gate drive unit of a first PMOS power switch tube;

2023 gate drive unit of a second PMOS power switch tube;

203 gate drive unit of an NMOS power switch tube;

2031 NMOS voltage regulation part;

2032 gate drive unit of a first NMOS power switch tube;

2033 gate drive unit of a second NMOS power switch tube;

300 power switch tube rectification module; and

20 functional circuit.

The following describes implementations of the present invention by using specific embodiments. A person skilled in the art may easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention may also be implemented or applied through other different specific implementations. Various details in this specification may also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

Refer to FIG. 2 to FIG. 7 . It should be noted that, the drawings provided in the embodiments of the present invention only exemplify the basic idea of the present invention. Although only the components related to the present invention are shown in the drawings, and are not drawn according to the quantities, shapes, and sizes of the components during actual implementation, during actual implementation, the patterns, quantities, and proportions of the components may be randomly changed, and the layout pattern of the components may be more complex.

As shown in FIG. 2 , this embodiment provides an active rectifier bridge circuit. The active rectifier bridge circuit 10 comprises: a bias module 100 , a gate driver module 200 , and a power switch tube rectification module 300 .

The bias module 100 is configured to provide a first bias current source I BIAS1 , a second bias current source I BIAS2 , and an internal power supply VDD to the gate driver module 200 .

The gate driver module 200 is connected to the bias module 100 , is controlled by the first bias current source I BIAS1 , the second bias current source I BIAS2 , and the internal power supply VDD, and is configured to: process one group of alternating current input voltages AC 1 and AC 2 to generate two groups of control signals COMP 1 B, COMP 1 , COMP 2 B, and COMP 2 that are mutually inverted, and generate four gate drive signals GATE_N 1 , GATE_N 2 , GATE_P 1 , and GATE_P 2 based on the two groups of control signals COMP 1 B, COMP 1 , COMP 2 B, and COMP 2 that are mutually inverted.

The power switch tube rectification module 300 is connected to the bias module 100 and the gate driver module 200 , comprises two NMOS power switch tubes NMP 1 and NMP 2 and two PMOS power switch tubes PMP 1 and PMP 2 , and is configured to: perform a turn-on or turn-off operation on the corresponding power switch tubes NMP 1 , NMP 2 , PMP 1 , and PMP 2 under the control of the four gate drive signals GATE_N 1 , GATE_N 2 , GATE_P 1 , and GATE_P 2 , and convert the one group of alternating current input voltages AC 1 and AC 2 into a direct current output voltage VCC for output.

For example, as shown in FIG. 2 , the bias module 100 is powered by an output end of the active rectifier bridge circuit 10 , that is, is powered by the direct current output voltage VCC, and is configured to provide the first bias current source I BIAS1 , the second bias current source I BIAS2 , and the internal power supply VDD to the gate driver module 200 . Specifically, the bias module 100 is any existing circuit that can generate a bias current and a power supply voltage, and a specific circuit structure of the bias module is not limited in this example.

For example, as shown in FIG. 2 , the power switch tube rectification module 300 comprises: a first NMOS power switch tube NMP 1 , a second NMOS power switch tube NMP 2 , a first PMOS power switch tube PMP 1 , a second PMOS power switch tube PMP 2 , a first pull-down resistor Rd 1 , a second pull-down resistor Rd 2 , a first pull-up resistor Ru 1 , and a second pull-up resistor Ru 2 , wherein a gate terminal of the first NMOS power switch tube NMP 1 is connected to a first output end of the gate driver module 200 and one end of the first pull-down resistor Rd 1 , the other end of the first pull-down resistor Rd 1 is grounded, a source terminal of the first NMOS power switch tube NMP 1 is grounded, a drain terminal of the first NMOS power switch tube NMP 1 is connected to a drain terminal of the first PMOS power switch tube PMP 1 , and is used as a first input end of the power switch tube rectification module 300 to input the first alternating current input voltage AC 1 , a gate terminal of the second NMOS power switch tube NMP 2 is connected to a second output end of the gate driver module 200 and one end of the second pull-down resistor Rd 2 , the other end of the second pull-down resistor Rd 2 is grounded, a source terminal of the second NMOS power switch tube NMP 2 is grounded, a drain terminal of the second NMOS power switch tube NMP 2 is connected to a drain terminal of the second PMOS power switch tube PMP 2 , and is used as a second input end of the power switch tube rectification module 300 to input the second alternating current input voltage AC 2 , a gate terminal of the first PMOS power switch tube PMP 1 is connected to a third output end of the gate driver module 200 and one end of the first pull-up resistor Ru 1 , a gate terminal of the second PMOS power switch tube PMP 2 is connected to a fourth output end of the gate driver module 200 and one end of the second pull-up resistor Ru 2 , and the other end of the first pull-up resistor Ru 1 is connected to a source terminal of the first PMOS power switch tube PMP 1 , the other end of the second pull-up resistor Ru 2 , a source terminal of the second PMOS power switch tube PMP 2 , the bias module 100 , and the gate driver module 200 , and is used as an output end of the power switch tube rectification module 300 to output the direct current output voltage VCC.

As shown in FIG. 2 , the gate terminal of the first NMOS power switch tube NMP 1 is controlled by the gate drive signal GATE_N 1 of the first NMOS power switch tube to be turned on or off. The gate terminal of the second NMOS power switch tube NMP 2 is controlled by the gate drive signal GATE_N 2 of the second NMOS power switch tube to be turned on or off. The gate terminal of the first PMOS power switch tube PMP 1 is controlled by the gate drive signal GATE_P 1 of the first PMOS power switch tube to be turned on or off. The gate terminal of the second PMOS power switch tube PMP 2 is controlled by the gate drive signal GATE_P 2 of the second PMOS power switch tube to be turned on or off.

In this example, the existing diodes are replaced with the four power switch tubes (the first NMOS power switch tube NMP 1 , the second NMOS power switch tube NMP 2 , the first PMOS power switch tube PMP 1 , and the second PMOS power switch tube PMP 2 ) for the design of the rectifier bridge, thereby greatly reducing a power loss. Compared with the design of the rectifier bridge composed of four diodes, this example uses two NMOS power switch tubes and two PMOS power switch tube for the design of the rectifier bridge, so that a case that the voltage of the gate drive signal is greater than the alternating current input voltage does not occur, thereby reducing design complexity of the gate driver module, and simplifying circuit layout design (that is, simplifying the circuit layout design by avoiding the processing of gate drive signals, a voltage withstand problem of a chip substrate, and an isolation problem of surrounding devices). The active rectifier bridge circuit in this example not only reduces the power loss, but also reduces the design complexity, and simplifies the circuit layout design, and is applicable to an application scenario with a relatively small current. Preferably, the first NMOS power switch tube NMP 1 , the second NMOS power switch tube NMP 2 , the first PMOS power switch tube PMP 1 , and the second PMOS power switch tube PMP 2 all use a gate source low voltage-withstand structure MOSFET, to implement smaller conduction internal resistance per unit area, thereby further reducing the power loss.

For example, as shown in FIG. 3 to FIG. 5 , the gate driver module 200 comprises: an alternating current level determining unit 201 , a gate drive unit 202 of the PMOS power switch tube, and a gate drive unit 203 of the NMOS power switch tube.

The alternating current level determining unit 201 is controlled by the internal power supply VDD, and is configured to: compare the first alternating current input voltage AC 1 with the second alternating current input voltage AC 2 in the one group of alternating current input voltages, and perform logical operation processing on a comparison result and a delay of the comparison result, to generate the two groups of control signals COMP 1 B, COMP 1 , COMP 2 B, and COMP 2 that are mutually inverted.

The gate drive unit 202 of the PMOS power switch tube is connected to the alternating current level determining unit 201 and the power switch tube rectification module 300 , is controlled by the first bias current source I BIAS1 , and is configured to: generate the gate drive signals GATE_P 1 and GATE_P 2 of the two PMOS power switch tubes under the control of the two groups of control signals COMP 1 B, COMP 1 , COMP 2 B, and COMP 2 that are mutually inverted.

The gate drive unit 203 of the NMOS power switch tube is connected to the alternating current level determining unit 201 , the gate drive unit 202 of the PMOS power switch tube, and the power switch tube rectification module 300 , is controlled by the second bias current source I BIAS2 , and is configured to: generate the gate drive signals GATE_N 1 and GATE_N 2 of the two NMOS power switch tubes under the control of the two groups of control signals COMP 1 B, COMP 1 , COMP 2 B, and COMP 2 that are mutually inverted and the gate drive signals GATE_P 1 and GATE_P 2 of the two PMOS power switch tubes.

Specifically, as shown in FIG. 3 , the alternating current level determining unit 201 comprises: a first alternating current level determining part 2011 and a second alternating current level determining part 2012 .

The first alternating current level determining part 2011 comprises: a first comparator CMP 1 , a first delayer Td 1 , a first NOR gate NOR 1 , and a first phase inverter In 1 , wherein an in-phase input end of the first comparator CMP 1 accesses the first alternating current input voltage AC 1 , an inverting input end of the first comparator CMP 1 accesses the second alternating current input voltage AC 2 , an output end of the first comparator CMP 1 is connected to an input end of the first delayer Td 1 and a first input end of the first NOR gate NOR 1 , an output end of the first delayer Td 1 is connected to a second input end of the first NOR gate NOR 1 , an output end of the first NOR gate NOR 1 is connected to an input end of the first phase inverter In 1 , and is used as a first output end of the alternating current level determining unit 201 to output the first control signal COMP 1 B, and an output end of the first phase inverter In 1 is used as a second output end of the alternating current level determining unit 201 to output the second control signal COMP 1 .

The second alternating current level determining part 2012 comprises: a second comparator CMP 2 , a second delayer Td 2 , a second NOR gate NOR 2 , and a second phase inverter In 2 , wherein an in-phase input end of the second comparator CMP 2 accesses the second alternating current input voltage AC 2 , an inverting input end of the second comparator CMP 2 accesses the first alternating current input voltage AC 1 , an output end of the second comparator CMP 2 is connected to an input end of the second delayer Td 2 and a first input end of the second NOR gate NOR 2 , an output end of the second delayer Td 2 is connected to a second input end of the second NOR gate NOR 2 , an output end of the second NOR gate NOR 2 is connected to an input end of the second phase inverter In 2 , and is used as a third output end of the alternating current level determining unit 201 to output the third control signal COMP 2 B, and an output end of the second phase inverter In 2 is used as a fourth output end of the alternating current level determining unit 201 to output the fourth control signal COMP 2 .

A delay time of the first delayer Td 1 is the same as a delay time of the second delayer Td 2 , and both are td. The first NOR gate NOR 1 , the second NOR gate NOR 2 , the first phase inverter In 1 , and the second phase inverter In 2 are all controlled by the internal power supply VDD.

As shown in FIG. 3 , when the first alternating current input voltage AC 1 is higher than the second alternating current input voltage AC 2 , an output of the first comparator CMP 1 is converted from a low level to a high level. In this case, the first NOR gate NOR 1 outputs the low level. That is, the first control signal COMP 1 B is converted from the high level to the low level, and the second control signal COMP 1 is converted from the low level to the high level. An output of the second comparator CMP 2 is converted from the high level to the low level, and after the delay time td of the second delayer Td 2 , an output of the second NOR gate NOR 2 is converted from the low level to the high level. That is, the third control signal COMP 2 B is converted from the low level to the high level, and the fourth control signal COMP 2 is converted from the high level to the low level. When the first alternating current input voltage AC 1 is lower than the second alternating current input voltage AC 2 , an output of the first comparator CMP 1 is converted from a high level to a low level, and after the delay time td of the first delayer Td 1 , an output of the first NOR gate NOR 1 is converted from the low level to the high level. That is, the first control signal COMP 1 B is converted from the low level to the high level, and the second control signal COMP 1 is converted from the high level to the low level. An output of the second comparator CMP 2 is converted from the low level to the high level. In this case, the second NOR gate NOR 2 outputs the low level. That is, the third control signal COMP 2 B is converted from the high level to the low level, and the fourth control signal COMP 2 is converted from the low level to the high level (for related signal time sequences, refer to FIG. 6 ).

Specifically, as shown in FIG. 4 , the gate drive unit 202 of the PMOS power switch tube comprises: a PMOS voltage regulation part 2021 , a gate drive part 2022 of the first PMOS power switch tube, and a gate drive part 2023 of the second PMOS power switch tube.

The PMOS voltage regulation part 2021 is configured to provide a first clamping voltage V DZ1 for the gate drive part 2022 of the first PMOS power switch tube and the gate drive part 2023 of the second PMOS power switch tube.

The gate drive part 2022 of the first PMOS power switch tube is connected to the PMOS voltage regulation part 2021 , the alternating current level determining unit 201 , and the power switch tube rectification module 300 , is controlled by the first bias current source I BIAS1 , and is configured to: generate, based on the accessed direct current output voltage VCC, a gate drive signal GATE_P 1 that turns off the first PMOS power switch tube, or generate, based on the accessed first clamping voltage V DZ1 , a gate drive signal GATE_P 1 that turns on the first PMOS power switch tube, under the control of one group of control signals COMP 2 B and COMP 2 that are mutually inverted and that are outputted by a third output end and a fourth output end of the alternating current level determining unit 201 .

The gate drive part 2023 of the second PMOS power switch tube is connected to the PMOS voltage regulation part 2021 , the alternating current level determining unit 201 , and the power switch tube rectification module 300 , is controlled by the first bias current source I BIAS1 , and is configured to: generate, based on the accessed direct current output voltage VCC, a gate drive signal GATE_P 2 that turns off the second PMOS power switch tube, or generate, based on the accessed first clamping voltage V DZ1 , a gate drive signal GATE_P 2 that turns on the second PMOS power switch tube, under the control of one group of control signals COMP 1 B and COMP 1 that are mutually inverted and that are outputted by a first output end and a second output end of the alternating current level determining unit 201 .

As shown in FIG. 4 , the PMOS voltage regulation part 2021 comprises a first voltage regulator tube DZ 1 , wherein a cathode terminal of the first voltage regulator tube DZ 1 accesses the direct current output voltage VCC, and an anode terminal of the first voltage regulator tube DZ 1 is used as an output end of the PMOS voltage regulation part 2021 to output the first clamping voltage V DZ1 .

As shown in FIG. 4 , the gate drive part 2022 of the first PMOS power switch tube comprises: a first NMOS tube NM 1 , a second NMOS tube NM 2 , a third NMOS tube NM 3 , a first PMOS tube PM 1 , a second PMOS tube PM 2 , a third PMOS tube PM 3 , a fourth PMOS tube PM 4 , a fifth PMOS tube PM 5 , and a sixth PMOS tube PM 6 , wherein a source terminal of the first NMOS tube NM 1 , a source terminal of the second NMOS tube NM 2 , and a source terminal of the third NMOS tube NM 3 are all grounded, a gate terminal of the first NMOS tube NM 1 is connected to the fourth output end of the alternating current level determining unit 201 to access the fourth control signal COMP 2 , a drain terminal of the first NMOS tube NM 1 is connected to a drain terminal of the first PMOS tube PM 1 , a gate terminal of the second NMOS tube NM 2 is connected to a gate terminal of the third NMOS tube NM 3 , and is simultaneously connected to the third output end of the alternating current level determining unit 201 to access the third control signal COMP 2 B, a drain terminal of the second NMOS tube NM 2 is connected to a drain terminal of the second PMOS tube PM 2 , a drain terminal of the third NMOS tube NM 3 is connected to a drain terminal of the third PMOS tube PM 3 , a gate terminal of the first PMOS tube PM 1 , a gate terminal of the second PMOS tube PM 2 , and a gate terminal of the third PMOS tube PM 3 are all connected to an output end of the PMOS voltage regulation part 2021 , and are controlled by the first bias current source I BIAS1 , a source terminal of the first PMOS tube PM 1 is connected to a drain terminal of the fourth PMOS tube PM 4 , a source terminal of the second PMOS tube PM 2 is connected to a drain terminal of the fifth PMOS tube PM 5 , a source terminal of the third PMOS tube PM 3 is connected to a drain terminal of the sixth PMOS tube PM 6 , and is used as an output end of the gate drive part 2022 of the first PMOS power switch tube to output the gate drive signal GATE_P 1 of the first PMOS power switch tube, a source terminal of the fourth PMOS tube PM 4 , a source terminal of the fifth PMOS tube PM 5 , and a source terminal of the sixth PMOS tube PM 6 all access the direct current output voltage VCC, a gate terminal of the fourth PMOS tube PM 4 is connected to the drain terminal of the fifth PMOS tube PM 5 , a gate terminal of the fifth PMOS tube PM 5 is connected to the drain terminal of the fourth PMOS tube PM 4 , and a gate terminal of the sixth PMOS tube PM 6 is connected to the source terminal of the first PMOS tube PM 1 . In this example, the first PMOS tube PM 1 and the second PMOS tube PM 2 are high-voltage isolation tubes.

As shown in FIG. 4 , the gate drive part 2023 of the second PMOS power switch tube comprises: a fourth NMOS tube NM 4 , a fifth NMOS tube NM 5 , a sixth NMOS tube NM 6 , a seventh PMOS tube PM 7 , an eighth PMOS tube PM 8 , a ninth PMOS tube PM 9 , a tenth PMOS tube PM 10 , an eleventh PMOS tube PM 11 , and a twelfth PMOS tube PM 12 , wherein a source terminal of the fourth NMOS tube NM 4 , a source terminal of the fifth NMOS tube NM 5 , and a source terminal of the sixth NMOS tube NM 6 are all grounded, a gate terminal of the fourth NMOS tube NM 4 is connected to the second output end of the alternating current level determining unit 201 to access the second control signal COMP 1 , a drain terminal of the fourth NMOS tube NM 4 is connected to a drain terminal of the seventh PMOS tube PM 7 , a gate terminal of the fifth NMOS tube NM 5 is connected to a gate terminal of the sixth NMOS tube NM 6 , and is simultaneously connected to the first output end of the alternating current level determining unit 201 to access the first control signal COMP 1 B, a drain terminal of the fifth NMOS tube NM 5 is connected to a drain terminal of the eighth PMOS tube PM 8 , a drain terminal of the sixth NMOS tube NM 6 is connected to a drain terminal of the ninth PMOS tube PM 9 , a gate terminal of the seventh PMOS tube PM 7 , a gate terminal of the eighth PMOS tube PM 8 , and a gate terminal of the ninth PMOS tube PM 9 are all connected to an output end of the PMOS voltage regulation part 2021 , and are controlled by the first bias current source I BIAS1 , a source terminal of the seventh PMOS tube PM 7 is connected to a drain terminal of the tenth PMOS tube PM 10 , a source terminal of the eighth PMOS tube PM 8 is connected to a drain terminal of the eleventh PMOS tube PM 11 , a source terminal of the ninth PMOS tube PM 9 is connected to a drain terminal of the twelfth PMOS tube PM 12 , and is used as an output end of the gate drive part of the second PMOS power switch tube 2023 to output the gate drive signal GATE_P 2 of the second PMOS power switch tube, a source terminal of the tenth PMOS tube PM 10 , a source terminal of the eleventh PMOS tube PM 11 , and a source terminal of the twelfth PMOS tube PM 12 all access the direct current output voltage VCC, a gate terminal of the tenth PMOS tube PM 10 is connected to the drain terminal of the eleventh PMOS tube PM 11 , a gate terminal of the eleventh PMOS tube PM 11 is connected to the drain terminal of the tenth PMOS tube PM 10 , and a gate terminal of the twelfth PMOS tube PM 12 is connected to the source terminal of the seventh PMOS tube PM 7 . In this example, the seventh PMOS tube PM 7 and the eighth PMOS tube PM 8 are high-voltage isolation tubes.

As shown in FIG. 4 , when the third control signal COMP 2 B is at the low level, and the fourth control signal COMP 2 is at the high level, the first NMOS tube NM 1 is turned on, the second NMOS tube NM 2 and the third NMOS tube NM 3 are turned off, and the first PMOS tube PM 1 , the second PMOS tube PM 2 , and the third PMOS tube PM 3 are controlled by the first bias current source I BIAS1 to be turned on. In this case, a gate terminal voltage of the sixth PMOS tube PM 6 is pulled to the low level by the first PMOS tube PM 1 to be turned on. In this case, a voltage of the gate drive signal GATE_P 1 of the first PMOS power switch tube is pulled up to VCC by the sixth PMOS tube PM 6 , to quickly turn off the first PMOS power switch tube PMP 1 . When the third control signal COMP 2 B is at the high level, and the fourth control signal COMP 2 is at the low level, the first NMOS tube NM 1 is turned off, the second NMOS tube NM 2 and the third NMOS tube NM 3 are turned on, and the first PMOS tube PM 1 , the second PMOS tube PM 2 , the third PMOS tube PM 3 are controlled by the first bias current source I BIAS1 to be turned on. In this case, the fourth PMOS tube PM 4 and the fifth PMOS tube PM 5 are turned on, and the gate terminal voltage of the sixth PMOS tube PM 6 is pulled up to VCC by the fourth PMOS tube PM 4 to be turned off. In this case, the voltage of the gate drive signal GATE_P 1 of the first PMOS power switch tube is pulled down to (VCC−V DZ1 +V TH3 ) by the third PMOS tube PM 3 , to quickly turn on the first PMOS power switch tube PMP 1 , and V TH3 is a threshold voltage of the third PMOS tube PM 3 . When the first control signal COMP 1 B is at the low level, and the second control signal COMP 1 is at the high level, the fourth NMOS tube NM 4 is turned on, the fifth NMOS tube NM 5 and the sixth NMOS tube NM 6 are turned off, and the seventh PMOS tube PM 7 , the eighth PMOS tube PM 8 , and the ninth PMOS tube PM 9 are controlled by the first bias current source I BIAS1 to be turned on. In this case, a gate terminal voltage of the twelfth PMOS tube PM 12 is pulled to the low level by the seventh PMOS tube PM 7 to be turned on. In this case, a voltage of the gate drive signal GATE_P 2 of the second PMOS power switch tube is pulled up to VCC by the twelfth PMOS tube PM 12 , to quickly turn off the second PMOS power switch tube PMP 2 . When the first control signal COMP 1 B is at the high level, and the second control signal COMP 1 is at the low level, the fourth NMOS tube NM 4 is turned off, the fifth NMOS tube NM 5 and the sixth NMOS tube NM 6 are turned on, and the seventh PMOS tube PM 7 , the eighth PMOS tube PM 8 , and the ninth PMOS tube PM 9 are controlled by the first bias current source I BIAS1 to be turned on. In this case, the tenth PMOS tube PM 10 and the eleventh PMOS tube PM 11 are turned on, and the gate terminal voltage of the twelfth PMOS tube PM 12 is pulled up to VCC by the tenth PMOS tube PM 10 to be turned off. In this case, the voltage of the gate drive signal GATE_P 2 of the second PMOS power switch tube is pulled down to (VCC−V DZ1 +V TH9 ) by the ninth PMOS tube PM 9 , to quickly turn on the second PMOS power switch tube PMP 2 , and V TH9 is a threshold voltage of the ninth PMOS tube PM 9 (for related signal time sequences, refer to FIG. 6 ).

Specifically, as shown in FIG. 5 , the gate drive unit 203 of the NMOS power switch tube comprises: an NMOS voltage regulation part 2031 , a gate drive part 2032 of the first NMOS power switch tube, and a gate drive part 2033 of the second NMOS power switch tube.

The NMOS voltage regulation part 2031 is configured to provide a second clamping voltage V DZ2 for the gate drive part 2032 of the first NMOS power switch tube and the gate drive part 2033 of the second NMOS power switch tube.

The gate drive part 2032 of the first NMOS power switch tube is connected to the NMOS voltage regulation part 2031 , the alternating current level determining unit 201 , the gate drive unit 202 of the PMOS power switch tube, and the power switch tube rectification module 300 , is controlled by the second bias current source I BIAS2 , and is configured to: generate, based on the accessed second clamping voltage V DZ2 , a gate drive signal GATE_N 1 that turns off or on the first NMOS power switch tube, under the control of a control signal COMP 1 outputted by a second output end of the alternating current level determining unit 201 and a gate drive signal GATE_P 2 of the second PMOS power switch tube outputted by the gate drive unit 202 of the PMOS power switch tube.

The gate drive part 2033 of the second NMOS power switch tube is connected to the NMOS voltage regulation part 2031 , the alternating current level determining unit 201 , the gate drive unit 202 of the PMOS power switch tube, and the power switch tube rectification module 300 , is controlled by the second bias current source I BIAS2 , and is configured to: generate, based on the accessed second clamping voltage V DZ2 , a gate drive signal GATE_N 2 that turns off or on the second NMOS power switch tube, under the control of a control signal COMP 2 outputted by a fourth output end of the alternating current level determining unit 201 and a gate drive signal GATE_P 1 of the first PMOS power switch tube outputted by the gate drive unit 202 of the PMOS power switch tube.

As shown in FIG. 5 , the NMOS voltage regulation part 2031 comprises: a second voltage regulator tube DZ 2 , wherein an anode terminal of the second voltage regulator tube DZ 2 is grounded, and a cathode terminal of the second voltage regulator tube DZ 2 is used as an output end of the NMOS voltage regulation part 2031 to output the second clamping voltage V DZ2 .

As shown in FIG. 5 , the gate drive part 2032 of the first NMOS power switch tube comprises: a thirteenth PMOS tube PM 13 , a seventh NMOS tube NM 7 , an eighth NMOS tube NMB, a ninth NMOS tube NM 9 , a tenth NMOS tube NM 10 , a third pull-up resistor Ru 3 , a third voltage regulator tube DZ 3 , a fourth voltage regulator tube DZ 4 , and a third phase inverter In 3 , wherein a gate terminal of the thirteenth PMOS tube PM 13 accesses the gate drive signal GATE_P 2 of the second PMOS power switch tube outputted by the gate drive unit 202 of the PMOS power switch tube, a source terminal of the thirteenth PMOS tube PM 13 accesses the direct current output voltage VCC, a drain terminal of the thirteenth PMOS tube PM 13 is connected to a drain terminal of the seventh NMOS tube NM 7 , a gate terminal of the seventh NMOS tube NM 7 is connected to an output end of the NMOS voltage regulation part 2031 , and is controlled by the second bias current source I BIAS2 , a source terminal of the seventh NMOS tube NM 7 is connected to a drain terminal of the eighth NMOS tube NM 8 , a cathode terminal of the third voltage regulator tube DZ 3 , an input end of the third phase inverter In 3 , a gate terminal of the ninth NMOS tube NM 9 , and one end of the third pull-up resistor Ru 3 , a gate terminal of the eighth NMOS tube NM 8 is connected to a second output end of the alternating current level determining unit 201 to access the second control signal COMP 1 , a source terminal of the eighth NMOS tube NM 8 is grounded, an anode terminal of the third voltage regulator tube DZ 3 is grounded, an output end of the third phase inverter In 3 is connected to a gate terminal of the tenth NMOS tube NM 10 , a drain terminal of the ninth NMOS tube NM 9 is connected to the other end of the third pull-up resistor Ru 3 , and simultaneously accesses the second alternating current input voltage AC 2 , a source terminal of the ninth NMOS tube NM 9 is connected to a cathode terminal of the fourth voltage regulator tube DZ 4 and a drain terminal of the tenth NMOS tube NM 10 , and is used as an output end of the gate drive part 2032 of the first NMOS power switch tube to output the gate drive signal GATE_N 1 of the first NMOS power switch tube, and a source terminal of the tenth NMOS tube NM 10 is grounded.

As shown in FIG. 5 , the gate drive part 2033 of the second NMOS power switch tube comprises: a fourteenth PMOS tube PM 14 , an eleventh NMOS tube NM 11 , a twelfth NMOS tube NM 12 , a thirteenth NMOS tube NM 13 , a fourteenth NMOS tube NM 14 , a fourth pull-up resistor Ru 4 , a fifth voltage regulator tube DZ 5 , a sixth voltage regulator tube DZ 6 , and a fourth phase inverter In 4 , wherein a gate terminal of the fourteenth PMOS tube PM 14 accesses the gate drive signal GATE_P 1 of the first PMOS power switch tube outputted by the gate drive unit 202 of the PMOS power switch tube, a source terminal of the fourteenth PMOS tube PM 14 accesses the direct current output voltage VCC, a drain terminal of the fourteenth PMOS tube PM 14 is connected to a drain terminal of the eleventh NMOS tube NM 11 , a gate terminal of the eleventh NMOS tube NM 11 is connected to an output end of the NMOS voltage regulation part 2031 , and is controlled by the second bias current source I BIAS2 , a source terminal of the eleventh NMOS tube NM 11 is connected to a drain terminal of the twelfth NMOS tube NM 12 , a cathode terminal of the fifth voltage regulator tube DZ 5 , an input end of the fourth phase inverter In 4 , a gate terminal of the thirteenth NMOS tube NM 13 , and one end of the fourth pull-up resistor Ru 4 , a gate terminal of the twelfth NMOS tube NM 12 is connected to a fourth output end of the alternating current level determining unit 201 to access the fourth control signal COMP 2 , a source terminal of the twelfth NMOS tube NM 12 is grounded, an anode terminal of the fifth voltage regulator tube DZ 5 is grounded, an output end of the fourth phase inverter In 4 is connected to a gate terminal of the fourteenth NMOS tube NM 14 , a drain terminal of the thirteenth NMOS tube NM 13 is connected to the other end of the fourth pull-up resistor Ru 4 , and simultaneously accesses the first alternating current input voltage AC 1 , a source terminal of the thirteenth NMOS tube NM 13 is connected to a cathode terminal of the sixth voltage regulator tube DZ 6 and a drain terminal of the fourteenth NMOS tube NM 14 , and is used as an output end of the gate drive part 2033 of the second NMOS power switch tube to output the gate drive signal GATE_N 2 of the second NMOS power switch tube, and a source terminal of the fourteenth NMOS tube NM 14 is grounded.

As shown in FIG. 5 , when the first alternating current input voltage AC 1 is higher than the second alternating current input voltage AC 2 , the first control signal COMP 1 B outputted by the alternating current level determining unit 201 is converted from the high level to the low level, the second control signal COMP 1 outputted by the alternating current level determining unit 201 is converted from the low level to the high level. In this case, a voltage of the gate drive signal GATE_P 2 of the second PMOS power switch tube is pulled up to VCC by the twelfth PMOS transistor PM 12 to control the second PMOS power switch tube PMP 2 to be turned off, and the gate driving signal GATE_P 2 of the second PMOS power switch tube controls the thirteenth PMOS transistor PM 13 to be turned off. The second control signal COMP 1 controls the eighth NMOS tube NM 8 to be turned on, to pull a gate terminal voltage of the ninth NMOS tube NM 9 to the low level for turn-off, and pull a gate terminal voltage of the tenth NMOS tube NM 10 to the high level for turn-on by using the eighth NMOS tube NMB, so that gate terminal charge of the first NMOS power switch tube NMP 1 is quickly discharged by using the tenth NMOS tube NM 10 to turn off the first NMOS power switch tube NMP 1 . After the delay time td, the third control signal COMP 2 B outputted by the alternating current level determining unit 201 is converted from the low level to the high level, and the fourth control signal COMP 2 outputted by the alternating current level determining unit 201 is converted from the high level to the low level. In this case, a voltage of the gate drive signal GATE_P 1 of the first PMOS power switch tube is pulled down to (VCC−V DZ1 +V TH3 ) by the third PMOS tube PM 3 to control the first PMOS power switch tube PMP 1 to be turned on, the gate drive signal GATE_P 1 of the first PMOS power switch tube controls the fourteenth PMOS tube PM 14 to be turned on, the fourth control signal COMP 2 controls the twelfth NMOS tube NM 12 to be turned off, and the eleventh NMOS tube NM 11 is controlled by the second bias current source I BIAS2 to be turned on, so that a gate terminal voltage of the thirteenth NMOS tube NM 13 is finally pulled up to a clamping voltage V DZ5 of the fifth voltage regulator tube by the fifth voltage regulator tube DZ 5 for turn-on, a gate terminal voltage of the fourteenth NMOS tube NM 14 is pulled to the low level for turn-off, and further, a voltage of the gate drive signal GATE_N 2 of the second NMOS power switch tube is clamped at (V DZ6 −V TH12 ) to turn on the second NMOS power switch tube NMP 2 . V DZ6 is a clamping voltage of the sixth voltage regulator tube DZ 6 , and V TH12 is a threshold voltage of the twelfth NMOS tube NM 12 . When the first alternating current input voltage AC 1 is lower than the second alternating current input voltage AC 2 , the third control signal COMP 2 B outputted by the alternating current level determining unit 201 is converted from the high level to the low level, and the fourth control signal COMP 2 is converted from the low level to the high level. In this case, the voltage of the gate drive signal GATE_P 1 of the first PMOS power switch tube is pulled up to VCC by the sixth PMOS tube PM 6 to control the first PMOS power switch tube to be turned off, the gate drive signal GATE_P 1 of the first PMOS power switch tube controls the fourteenth PMOS tube PM 14 to be turned off, and the fourth control signal COMP 2 controls the twelfth NMOS tube NM 12 to be turned on, to pull a gate terminal voltage of the thirteenth NMOS tube NM 13 to the low level for turn-off, and pull a gate terminal voltage of the fourteenth NMOS tube NM 14 to the high level for turn-on by using the twelfth NMOS tube NM 12 , so that gate terminal charge of the second NMOS power switch tube NMP 2 is quickly discharged by using the fourteenth NMOS tube NM 14 to turn off the second NMOS power switch tube NMP 2 . After the delay time td, the first control signal COMP 1 B outputted by the alternating current level determining unit 201 is converted from the low level to the high level, and the second control signal COMP 1 outputted by the alternating current level determining unit 201 is converted from the high level to the low level. In this case, a voltage of the gate drive signal GATE_P 2 of the second PMOS power switch tube is pulled down to (VCC−V DZ1 +V TH9 ) by the ninth PMOS tube PM 9 to control the second PMOS power switch tube PMP 2 to be turned on, the gate drive signal GATE_P 2 of the second PMOS power switch tube controls the thirteenth PMOS tube PM 13 to be turned on, the second control signal COMP 1 controls the eighth NMOS tube NM 8 to be turned off, and the seventh NMOS tube NM 7 is controlled by the second bias current source I BIAS2 to be turned on, so that the gate terminal voltage of the ninth NMOS tube NM 9 is finally pulled up to a clamping voltage V DZ3 of the third voltage regulator tube by the third voltage regulator tube DZ 3 for turn-on, the gate terminal voltage of the tenth NMOS tube NM 10 is pulled to the low level for turn-off, and further, the voltage of the gate drive signal GATE_N 1 of the first NMOS power switch tube is clamped at (V DZ4 −V TH9 ) to turn on the first NMOS power switch tube NMP 1 . V DZ4 is a clamping voltage of the fourth voltage regulator tube DZ 4 , and V TH9 is a threshold voltage of the ninth NMOS tube NM 9 (for related signal time sequences, refer to FIG. 6 ).

In this example, the alternating current level determining unit 201 generates, by using the first delayer Td 1 and the second delayer Td 2 , two groups of control signals that are mutually inverted and that have the delay time td, and the gate drive unit 202 of the PMOS power switch tube and the gate drive unit 203 of the NMOS power switch tube generate the gate drive signals of the four power switch tubes based on the two groups of control signals, thereby implementing dead-time control on turn-on/off of the four power switch tubes. Specifically, when the first alternating current input voltage AC 1 is higher than the second alternating current input voltage AC 2 , the second NMOS power switch tube NMP 2 and the first PMOS power switch tube PMP 1 are turned on, and the first NMOS power switch tube NMP 1 and the second PMOS power switch tube PMP 2 are turned off. When the first alternating current input voltage AC 1 is lower than the second alternating current input voltage AC 2 , the first NMOS power switch tube NMP 2 and the second PMOS power switch tube PMP 1 are turned on, and the second NMOS power switch tube NMP 1 and the first PMOS power switch tube PMP 2 are turned off, so that the active rectifier bridge circuit in this example implements a safe and reliable rectification function, and rectification efficiency of the active rectifier bridge circuit is significantly improved.

As shown in FIG. 7 , this embodiment provides an on-chip integrated system, comprising: the active rectifier bridge circuit 10 according to Embodiment 1 and a functional circuit 20 connected to an output end of the active rectifier bridge circuit 10 , wherein the active rectifier bridge circuit 10 provides a working voltage VCC for the functional circuit 20 , and the active rectifier bridge circuit 10 and the functional circuit 20 are formed on the same silicon wafer.

In this example, because the active rectifier bridge circuit 10 and the functional circuit 20 are formed on the same silicon wafer, to reduce circuit production costs, the MOS tubes (comprising PMOS tubes and NMOS tubes) in the gate drive unit of the PMOS power switch tube and the MOS tubes (comprising PMOS tubes and NMOS tubes) in the gate drive unit of the NMOS power switch tube of the active rectifier bridge circuit 10 all use a gate source low voltage-withstand structure MOSFET. It should be noted that, the active rectifier bridge circuit in this example is the same as that in Embodiment 1, and details are not described herein again.

For example, the functional circuit 20 is any existing circuit that can be connected to the output end of the active rectifier bridge circuit 10 , and a specific circuit structure of the functional circuit is not limited in this example.

As described above, according to the active rectifier bridge circuit and the on-chip integrated system consistent with the present invention, the existing diodes are replaced with the four power switch tubes for the design of the rectifier bridge, thereby greatly reducing a power loss. In addition, in the present invention, the gate driver module controls the switch drive and time sequence of the four power switch tubes, to implement dead-time control on turn-on/off of the four power switch tubes, so that the active rectifier bridge circuit consistent with the present invention implements a safe and reliable rectification function, and rectification efficiency of the active rectifier bridge circuit is significantly improved. The active rectifier bridge circuit consistent with the present invention is implemented by using conventional process devices. Therefore, the active rectifier bridge circuit can be produced on the same silicon wafer as the functional circuit, thereby improving the product integration degree, and helping implement product miniaturization and intelligence. Therefore, the present invention effectively overcomes various defects in the prior art, and has a high value in industrial use.

The foregoing embodiments merely exemplify the principles and effects of the present invention, but are not intended to limit the present invention. Any person skilled in the art may make modifications or changes on the foregoing embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by a person of ordinary skill in the art without departing from the spirit and technical idea of the present invention shall be covered by the claims of the present invention.