Power amplifier circuit

This is a continuation of U.S. patent application Ser. No. 16/521,006 filed on Jul. 24, 2019, which claims priority from Japanese Patent Application No. 2018-150968 filed on Aug. 10, 2018. The contents of these applications are incorporated herein by reference in their entireties.

The present disclosure relates to a power amplifier circuit. In a power amplifier circuit that is mounted in a mobile communication device such as a mobile phone, a bipolar transistor is typically used as an amplifier. The bipolar transistor has a thermal positive feedback characteristic in which if the temperature of the element increases, the collector current increases, which further raises the temperature of the element, leading to a further increase in the collector current. To suppress the increase in the collector current caused by the temperature increase, a configuration is known in which, for example, a resistance element (hereinafter also referred to as a ballast resistor) is disposed between the base of the bipolar transistor and a base bias voltage supply terminal. In this configuration, a voltage drop across the ballast resistor suppresses the increase in the base current, and, as a result, the increase in the collector current is also suppressed.

In a configuration including a ballast resistor, if the base current increases with an increase in the power level of an input signal, a voltage drop across the ballast resistor increases, which results in a decrease in the base voltage. Thus, the amplitude of the collector current is not proportionate to the amplitude of the base current, and the power gain decreases, which may deteriorate the linearity of the amplifier. To prevent the deterioration of the linearity, for example, Japanese Unexamined Patent Application Publication No. 2003-324325 discloses a power amplifier that includes a capacitance element between a signal input terminal and a base bias voltage supply terminal. With this configuration, power supplied from the signal input terminal can be transmitted to the base bias voltage supply terminal. Thus, a reduction in the base voltage is suppressed, and the linearity is improved.

In the configuration disclosed in Japanese Unexamined Patent Application Publication No. 2003-324325, the capacitance element connected between the signal input terminal and the base bias voltage supply terminal may be part of a matching circuit seen from the signal input terminal. That is, the capacitance element affects matching between the input impedance of an amplifier and the output impedance of a circuit preceding the amplifier.

Accordingly, the present disclosure provides a power amplifier circuit that matches impedances of an amplifier and the preceding circuit, with improved linearity of power gain.

According to embodiments of the present disclosure, a power amplifier circuit includes an amplifier transistor having a base or gate to which an input signal is supplied, and a collector or drain from which an amplified signal obtained by amplifying the input signal is output, a bias circuit that supplies a bias current or bias voltage to the base or gate of the amplifier transistor, and a resistance element connected in series between the base or gate of the amplifier transistor and the bias circuit. The bias circuit includes a voltage generation circuit that generates a first direct-current voltage in accordance with a control signal, a first transistor having a base or gate to which the first direct-current voltage is supplied, and an emitter or source from which the bias current or bias voltage is supplied to the base or gate of the amplifier transistor via the resistance element, a second transistor having a base or gate to which a second direct-current voltage is supplied, and an emitter or source connected to the emitter or source of the first transistor, a signal supply circuit disposed between the base or gate of the amplifier transistor and the base or gate of the second transistor and configured to supply the input signal to the base or gate of the second transistor, and an impedance circuit disposed between the base or gate of the first transistor and the base or gate of the second transistor. When the power amplifier circuit operates in a first mode, the voltage generation circuit is controlled by the control signal so that the voltage generation circuit is kept in an on state. When the power amplifier circuit operates in a second mode in which a power level of the amplified signal is lower than a power level of the amplified signal in the first mode, the voltage generation circuit is controlled by the control signal so that the voltage generation circuit is kept in an off state.

According to embodiments of the present disclosure, it may be possible to provide a power amplifier circuit that matches impedances of an amplifier and the preceding circuit, with improved linearity of power gain.

Other features, elements, characteristics and advantages of the present disclosure will become more apparent from the following detailed description of embodiments of the present disclosure with reference to the attached drawings.

FIG. 1 is a diagram illustrating an example configuration of a power amplifier circuit according to a first embodiment of the present disclosure;

FIG. 2A is a graph depicting a relationship between input power and voltage when a bias circuit is used;

FIG. 2B is a graph depicting a gain characteristic when the bias circuit is used;

FIG. 2C is a graph depicting a change in voltage with time at an input power when the bias circuit is used;

FIG. 3A is a graph depicting a relationship between input power and voltage when another bias circuit is used;

FIG. 3B is a graph depicting a gain characteristic when the other bias circuit is used;

FIG. 3C is a graph depicting a change in voltage with time at an input power when the other bias circuit is used;

FIG. 4 is a diagram illustrating an example configuration of a power amplifier circuit according to a second embodiment of the present disclosure;

FIG. 5 is a graph depicting simulation results of the power gain of the power amplifier circuit according to the second embodiment of the present disclosure and simulation results of power gain in a comparative example;

FIG. 6 is a diagram illustrating an example configuration of a power amplifier circuit according to a third embodiment of the present disclosure;

FIG. 7 is a diagram illustrating an example configuration of a power amplifier circuit according to a fourth embodiment of the present disclosure;

FIG. 8A is a graph depicting a relationship between input power and voltage in the power amplifier circuit according to the fourth embodiment of the present disclosure;

FIG. 8B is a graph depicting a change in voltage with time at an input power in the power amplifier circuit according to the fourth embodiment of the present disclosure; and

FIG. 9 is a diagram illustrating an example configuration of a power amplifier circuit according to a fifth embodiment of the present disclosure.

The following describes embodiments of the present disclosure with reference to the drawings. The same or substantially the same elements are denoted by the same numerals, and will not be repeatedly described.

FIG. 1 is a diagram illustrating an example configuration of a power amplifier circuit 100 A according to a first embodiment of the present disclosure. The power amplifier circuit 100 A illustrated in FIG. 1 is mounted in a mobile phone, for example, and is used to amplify the power of a radio-frequency (RF) signal to be transmitted to a base station. The power amplifier circuit 100 A amplifies the power of signals complying with communication standards such as the second generation mobile communication system (2G), the third generation mobile communication system (3G), the fourth generation mobile communication system (4G), the fifth generation mobile communication system (5G), Long Term Evolution Frequency Division Duplex (LTE-FDD), LTE Time Division Duplex (LTE-TDD), LTE-Advanced, and LTE-Advanced Pro. The power amplifier circuit 100 A may amplify the power of signals complying with other communication standards.

The power amplifier circuit 100 A includes a transistor Q 1 , bias circuits 110 A and 120 A, a capacitor C 1 , and a resistance element R 1 . The power amplifier circuit 100 A amplifies an input signal RFin supplied to an input terminal and outputs an amplified signal RFout from an output terminal. These components will be described in detail hereinafter.

The transistor Q 1 (amplifier transistor) has a collector to which a power supply voltage (not illustrated) is supplied, a base connected in series with the capacitor C 1 , and an emitter grounded. The input signal RFin is supplied to the base of the transistor Q 1 from outside the power amplifier circuit 100 A via the capacitor C 1 , and a bias current or bias voltage is further supplied to the base of the transistor Q 1 from the bias circuit 110 A or the bias circuit 120 A via the resistance element R 1 . Accordingly, the amplified signal RFout, which is obtained by amplifying the input signal RFin, is output from the collector of the transistor Q 1 . The gain of the transistor Q 1 is controlled in accordance with the bias current or bias voltage supplied from the bias circuit 110 A or 120 A.

The transistor Q 1 may be a transistor group including a configuration in which a plurality of unit transistors (fingers) are connected in parallel (i.e., a multi-finger configuration). The term “unit transistor” refers to a minimum element that functions as a transistor.

The transistor Q 1 will be described herein as, but not limited to, a bipolar transistor such as a heterojunction bipolar transistor (HBT). A field effect transistor (FET) may be used instead of a bipolar transistor. Examples of the FET include a metal-oxide-semiconductor field effect transistor (MOSFET), a junction field effect transistor (JFET), and a metal-semiconductor field effect transistor (MESFET). When an FET is used instead of a bipolar transistor, the terms “collector”, “base”, and “emitter” are changed to the terms “drain”, “gate”, and “source”, respectively. The same applies to other transistors described below.

Each of the bias circuits 110 A and 120 A generates a bias current or bias voltage and supplies the bias current or bias voltage to the base of the transistor Q 1 . The configuration of the bias circuits 110 A and 120 A will be described in detail below.

One end of the capacitor C 1 is connected to the input terminal. The other end of the capacitor C 1 is connected to the base of the transistor Q 1 . The capacitor C 1 removes the direct-current (DC) component of the input signal RFin.

The resistance element R 1 is connected in series between the base of the transistor Q 1 and the output of the bias circuits 110 A and 120 A. Specifically, one end of the resistance element R 1 is connected to the base of the transistor Q 1 . The other end of the resistance element R 1 is connected to emitters of transistors Q 2 a , Q 3 a , and Q 2 b described below. The resistance element R 1 is a ballast resistor for preventing a thermal positive feedback of the transistor Q 1 . That is, the transistor Q 1 has a thermal positive feedback characteristic in which if the temperature of the transistor element increases, the collector current increases, which further raises the temperature of the transistor element, leading to a further increase in the collector current. Thus, for example, if the resistance element R 1 is not included in a multi-finger configuration in which a plurality of unit transistors are connected in parallel, the flow of the collector current concentrates on some transistors, which may produce thermal runaway. As a result, the transistors may be broken. In the power amplifier circuit 100 A, which includes the resistance element R 1 , if the base current of the transistor Q 1 increases, a voltage drop occurs across the resistance element R 1 , which suppresses the increase in the base current. Accordingly, an increase in the collector current of the transistor Q 1 is suppressed.

Next, the configuration of the bias circuits 110 A and 120 A will be described in detail. The bias circuit 110 A includes, for example, a voltage generation circuit 200 a , the transistors Q 2 a and Q 3 a , a capacitor C 2 a , and a resistance element R 2 a.

The voltage generation circuit 200 a includes, for example, a resistance element R 3 a , transistors Q 4 a and Q 5 a , and a capacitor C 3 a . The resistance element R 3 a has an end to which a control current Icont 1 is supplied from a terminal Ta, and another end connected to the collector of the transistor Q 4 a . The transistors Q 4 a and Q 5 a are connected in series. Specifically, the collector and base of the transistor Q 4 a are connected (hereinafter also referred to as diode-connected). The collector of the transistor Q 4 a is connected to the other end of the resistance element R 3 a , and the emitter of the transistor Q 4 a is connected to the collector of the transistor Q 5 a . The transistor Q 5 a is diode-connected, and the emitter of the transistor Q 5 a is grounded. One end of the capacitor C 3 a is connected to the base of the transistor Q 4 a , and the other end of the capacitor C 3 a is grounded. The capacitor C 3 a is used to alternating current (AC) ground the base of the transistor Q 2 a.

In the voltage generation circuit 200 a , with the configuration described above, a voltage V 1 (first direct-current voltage) having a predetermined level (e.g., about 2.8 V) is generated at the collector of the transistor Q 4 a . Each of the transistors Q 4 a and Q 5 a may be replaced with a diode element.

The transistor Q 2 a (first transistor) has a collector to which a power supply voltage Vbatt is supplied, a base to which the voltage V 1 is supplied, and an emitter connected to the other end of the resistance element R 1 . The transistor Q 2 a supplies a bias current or bias voltage to the base of the transistor Q 1 via the resistance element R 1 . The emitter voltage of the transistor Q 2 a is represented as a voltage Vbias.

One end of the resistance element R 2 a is connected to the base of the transistor Q 2 a , and the other end of the resistance element R 2 a is connected to the base of the transistor Q 3 a . The resistance element R 2 a outputs, from the other end thereof, a voltage V 2 (second direct-current voltage) responsive to the voltage V 1 supplied to the one end thereof, and supplies the voltage V 2 to the base of the transistor Q 3 a as a bias voltage. The voltage V 2 is, for example, a voltage lower than the voltage V 1 . The bias voltage of the transistor Q 3 a can be adjusted by adjusting the resistance value of the resistance element R 2 a . The resistance element R 2 a is a specific example of an impedance circuit.

The capacitor C 2 a (signal supply circuit) is connected in series between the base of the transistor Q 1 and the base of the transistor Q 3 a . Specifically, one end of the capacitor C 2 a is connected to a node between the input terminal and the one end of the capacitor C 1 , and the other end of the capacitor C 2 a is connected to the base of the transistor Q 3 a and the other end of the resistance element R 2 a . The capacitor C 2 a removes the DC component of the input signal RFin, detects the AC component of the input signal RFin, and supplies the AC component of the input signal RFin to the base of the transistor Q 3 a . The capacitor C 2 a is a specific example of a signal supply circuit. The one end of the capacitor C 2 a may be connected to a node between the other end of the capacitor C 1 and the one end of the resistance element R 1 .

The transistor Q 3 a (second transistor) has a collector to which the power supply voltage Vbatt is supplied, a base to which the voltage V 2 (second direct-current voltage) responsive to the voltage V 1 is supplied, and an emitter connected to the emitter of the transistor Q 2 a . The AC component of the input signal RFin is further supplied to the base of the transistor Q 3 a via the capacitor C 2 a . Accordingly, the transistor Q 3 a is biased by the voltage V 2 and outputs a signal obtained by amplifying the input signal RFin to the emitter of the transistor Q 2 a . By adjusting the bias voltage to be supplied to the transistor Q 3 a , the transistor Q 3 a can be biased such that, for example, the transistor Q 3 a is turned off when the power level of the input signal RFin is comparatively low and is turned on when the power level of the input signal RFin is comparatively high.

The bias circuit 120 A (second bias circuit) includes, for example, a voltage generation circuit 200 b (second voltage generation circuit) and the transistor Q 2 b (third transistor). The voltage generation circuit 200 b includes, for example, a resistance element R 3 b , transistors Q 4 b and Q 5 b , and a capacitor C 3 b . The configuration and operation of the voltage generation circuit 200 b and the transistor Q 2 b are similar to those of the voltage generation circuit 200 a and the transistor Q 2 a in the bias circuit 110 A, and thus will not be described in detail. In the bias circuit 120 A, the transistor Q 2 b supplies a bias current or bias voltage to the base of the transistor Q 1 via the resistance element R 1 .

The on and off states of the bias circuits 110 A and 120 A are respectively controlled by the control currents Icont 1 and Icont 2 , which are supplied to the terminals Ta and Tb, respectively. The control currents Icont 1 and Icont 2 are specific examples of a control signal. The on and off states of the bias circuits 110 A and 120 A may be controlled by a control voltage.

The power amplifier circuit 100 A operates in two power modes that differ depending on the level of the output power, and the bias circuit to be used is switched in accordance with the power mode in which the power amplifier circuit 100 A operates. Specifically, when the power amplifier circuit 100 A operates in a high power mode (first mode) in which the output power is greater than or equal to a predetermined level, the control current Icont 1 for turning on the voltage generation circuit 200 a is supplied to the terminal Ta, and the control current Icont 2 for turning off the voltage generation circuit 200 b is supplied to the terminal Tb. Accordingly, a bias current or bias voltage is supplied from the bias circuit 110 A to the base of the transistor Q 1 . When the power amplifier circuit 100 A operates in a low power mode (second mode) in which the output power is less than the predetermined level, in contrast, the control current Icont 1 for turning off the voltage generation circuit 200 a is supplied to the terminal Ta, and the control current Icont 2 for turning on the voltage generation circuit 200 b is supplied to the terminal Tb. Accordingly, a bias current or bias voltage is supplied from the bias circuit 120 A to the base of the transistor Q 1 .

Next, the difference between the bias circuit 110 A and the bias circuit 120 A will be described with reference to FIGS. 2A to 2C and 3A to 3C . The emitter voltage of the transistor Q 2 b when the bias circuit 120 A is used is denoted by Vbias′ (second bias voltage), and the base voltage of the transistor Q 2 b when the bias circuit 120 A is used is denoted by V 1 ′ (third direct-current voltage).

FIG. 2A is a graph depicting a relationship between input power Pin and the voltage Vbias′ when the bias circuit 120 A is used, FIG. 2B is a graph depicting a gain characteristic when the bias circuit 120 A is used, and FIG. 2C is a graph depicting a change in the voltage Vbias′ with time at an input power Pa when the bias circuit 120 A is used. FIG. 3A is a graph depicting a relationship between the input power Pin and the voltage Vbias when the bias circuit 110 A is used, FIG. 3B is a graph depicting a gain characteristic when the bias circuit 110 A is used, and FIG. 3C is a graph depicting a change in the voltage Vbias with time at the input power Pa when the bias circuit 110 A is used.

As illustrated in FIG. 2A , the voltage Vbias′ in the bias circuit 120 A remains constant within a region where the input power Pin is comparatively low, and rapidly decreases when the input power Pin exceeds a predetermined level. Such a rapid decrease in the voltage Vbias′ is caused by the following reason. In accordance with an increase in the base current of the transistor Q 1 , a voltage drop occurs across the resistance element R 1 , which causes a decrease in the base voltage of the transistor Q 1 . Thus, the amplitude of the collector current is not proportionate to the amplitude of the base current, and, as illustrated in FIG. 2B , a decrease in power gain (hereinafter also referred to as gain compression) may occur.

FIG. 2C illustrates the waveform of the voltage Vbias′ when the input power Pin has a comparatively high level (the input power Pa illustrated in FIG. 2B ). Since the input signal RFin is propagated to the emitter of the transistor Q 2 b via the resistance element R 1 , the voltage Vbias′ has a waveform that changes in amplitude. When the emitter voltage of the transistor Q 2 b decreases in accordance with the signal amplitude of the input signal RFin, the transistor Q 2 b is brought into an on state. During a period in which the transistor Q 2 b remains in the on state (time t 1 ), the waveform of the voltage Vbias′ is kept at a predetermined value. Specifically, the voltage Vbias′ is kept at a value obtained by subtracting the base-emitter voltage (Vbe 2 ) of the transistor Q 2 b from the base voltage (V 1 ′) of the transistor Q 2 b (i.e., at a value given by V 1 ′−Vbe 2 ).

In the bias circuit 110 A, in contrast, the input signal RFin, which is detected by the capacitor C 2 a , is supplied to the base of the transistor Q 3 a , and the transistor Q 3 a amplifies the input signal RFin and outputs the amplified signal to the emitter of the transistor Q 2 a . Accordingly, particularly when the power level of the input signal RFin is comparatively high, the voltage amplitude on the emitter of the transistor Q 2 a is greater than that in the bias circuit 120 A (see FIGS. 2C and 3C ). In the bias circuit 110 A, therefore, a time period t 2 during which the transistor Q 2 a remains in the on state (i.e., a time period during which the voltage Vbias is kept at a predetermined value (V 1 −Vbe 2 )) is longer than that in the bias circuit 120 A (i.e., t 1 <t 2 ). Accordingly, the average value Vbias_ave of the voltage Vbias is larger than the average value Vbias′_ave of the voltage Vbias′. Thus, as illustrated in FIG. 3A , during the use of the bias circuit 110 A, the decrease in the voltage Vbias and the decrease in the base voltage of the transistor Q 1 are suppressed in a region where the power level of the input power Pin is comparatively high.

As described above, the power amplifier circuit 100 A includes the two bias circuits 110 A and 120 A having different characteristics. The bias circuit 120 A is used in the low power mode, and the bias circuit 110 A is used in the high power mode. This configuration can improve linearity within a region where the output power is comparatively high, compared to a configuration in which, for example, the bias circuit 120 A is used regardless of the level of the output power. In addition, if the bias circuit 110 A is used regardless of the output power, an increase in the emitter voltage of the transistors Q 2 a and Q 3 a increases the base current of the transistor Q 1 , which may lead to an unintended increase in power gain. In the power amplifier circuit 100 A according to this embodiment, the bias circuit 120 A, which does not have an input signal detection function, is used in the low power mode. This may suppress an increase in the power gain. Thus, the linearity of the power gain can be improved in the low power mode.

Referring back to FIG. 1 , a description will be given of the impedance on the bias circuit 110 A side seen from the input terminal. For example, as disclosed in Japanese Unexamined Patent Application Publication No. 2003-324325, in a configuration that does not include the transistor Q 3 a or the resistance element R 2 a , an impedance mismatch occurs between the input terminal and the transistor Q 1 due to the influence of the capacitor C 2 a , which may lead to a reduction in power-added efficiency or a decrease in power gain. For example, in a power amplifier circuit including two stages of amplifiers such that the amplifier in the last stage is constituted by the transistor Q 1 , an impedance mismatch between the stages may occur. In the power amplifier circuit 100 A, in contrast, the base of the transistor Q 3 a and the resistance element R 2 a are connected to the end of the capacitor C 2 a that is farther from the input terminal. The base of a transistor typically has a comparatively high impedance. In the power amplifier circuit 100 A, accordingly, the impedance on the capacitor C 2 a side relative to the impedance on the capacitor C 1 side seen from the input terminal is higher than that in the configuration disclosed in Japanese Unexamined Patent Application Publication No. 2003-324325. This can prevent or reduce the effect of the capacitor C 2 a on impedance matching between an amplifier and a circuit preceding the amplifier. In other words, the power amplifier circuit 100 A can match impedances of an amplifier and the preceding circuit, with improved linearity of power gain.

FIG. 4 is a diagram illustrating an example configuration of a power amplifier circuit 100 B according to a second embodiment of the present disclosure. The same or substantially the same elements as those of the power amplifier circuit 100 A are denoted by the same numerals and will not be described. In the second and subsequent embodiments, features common to the first embodiment will not be described, and only the differences will be described. In particular, similar operations and effects achieved with similar configurations will not be described again in the individual embodiments.

As illustrated in FIG. 4 , in the power amplifier circuit 100 B, amplifier paths, each including the transistor Q 1 , the capacitor C 1 , and the resistance element R 1 of the power amplifier circuit 100 A, are connected in parallel. The power amplifier circuit 100 B further includes a bias circuit 120 B instead of the bias circuit 120 A.

One of the two amplifier paths connected in parallel includes a transistor Q 1 x , a capacitor C 1 x , and a resistance element R 1 x , and the other amplifier path includes a transistor Q 1 y (second amplifier transistor), a capacitor C 1 y , and a resistance element R 1 y (second resistance element). The connection relationships and the operations of these elements are similar to those of the transistor Q 1 , the capacitor C 1 , and the resistance element R 1 in the power amplifier circuit 100 A, and thus will not be described in detail. A bias current or bias voltage is supplied to the base of the transistor Q 1 x from the bias circuit 110 A via the resistance element R 1 x , and a bias current or bias voltage is supplied to the base of the transistor Q 1 y from the bias circuit 120 B via the resistance element R 1 y.

Unlike the bias circuit 120 A, the bias circuit 120 B further includes a transistor Q 3 b (fourth transistor). Similarly to the transistor Q 3 a in the bias circuit 110 A, the transistor Q 3 b has a collector to which the power supply voltage Vbatt is supplied, a base to which the voltage V 2 responsive to the voltage V 1 is supplied, and an emitter connected to the emitter of the transistor Q 2 b . The AC component of the input signal RFin is further supplied to the base of the transistor Q 3 b via the capacitor C 2 a . Accordingly, the transistor Q 3 b is biased by the voltage V 2 , and outputs a signal obtained by amplifying the input signal RFin to the emitter of the transistor Q 2 b.

In this embodiment, when the power amplifier circuit 100 B operates in the high power mode, the control currents Icont 1 and Icont 2 for respectively turning on the voltage generation circuits 200 a and 200 b are supplied to the terminals Ta and Tb, respectively. Accordingly, a bias current is supplied from the bias circuit 110 A to the transistor Q 1 x , and a bias current is supplied from the bias circuit 120 B to the transistor Q 1 y , thereby allowing both transistors to operate. At this time, the input signal RFin, which is detected by the capacitor C 2 a , is also supplied to the transistor Q 3 b in addition to the transistor Q 3 a . Accordingly, like the bias circuit 110 A, the bias circuit 120 B operates as a circuit having an input signal detection function. When the power amplifier circuit 100 B operates in the low power mode, in contrast, the control current Icont 1 for turning off the voltage generation circuit 200 a is supplied to the terminal Ta, and the control current Icont 2 for turning on the voltage generation circuit 200 b is supplied to the terminal Tb. Accordingly, a bias current is supplied from the bias circuit 120 B, to the transistor Q 1 y and the transistor Q 1 y operates. At this time, the voltage generation circuit 200 a is in an off state. Thus, no DC voltage is supplied to the base of the transistor Q 3 b , and the transistor Q 3 b is brought into an off state. Accordingly, like the bias circuit 120 A, the bias circuit 120 B operates as a circuit having no input signal detection function.

With the configuration described above, like the power amplifier circuit 100 A, the power amplifier circuit 100 B can also match impedances of an amplifier and the preceding circuit, with improved linearity of power gain. In the power amplifier circuit 100 B, furthermore, the transistor size for amplification is switched in accordance with the power mode. The transistors Q 1 x and Q 1 y can thus be designed in accordance with each power mode.

FIG. 5 is a graph depicting simulation results of the power gain of the power amplifier circuit 100 B according to the second embodiment of the present disclosure and simulation results of power gain in a comparative example. Specifically, the graph illustrated in FIG. 5 depicts results of simulation of the relationship between output power and power gain when the frequency of the input signal RFin is set to 824 MHz or 915 MHz. In the comparative example, a configuration similar to the configuration of the power amplifier circuit 100 B is used, and results are obtained when the bias circuit 110 A is turned on (i.e., the detection function is enabled) in both the high power mode and the low power mode. In FIG. 5 , the horizontal axis represents output power Pout (dBm) and the vertical axis represents gain (dB).

As illustrated in FIG. 5 , in the comparative example, the power gain largely increases with an increase in output power regardless of the frequency. In the power amplifier circuit 100 B, in contrast, the power gain slightly increases with an increase in output power, with the amount of the increase being smaller than that in the comparative example. This indicates that the linearity of the power gain of the power amplifier circuit 100 B is improved, compared to the comparative example.

FIG. 6 is a diagram illustrating an example configuration of a power amplifier circuit 100 C according to a third embodiment of the present disclosure. The same or substantially the same elements as those of the power amplifier circuit 100 B are denoted by the same numerals and will not be described.

As illustrated in FIG. 6 , unlike the power amplifier circuit 100 B, the power amplifier circuit 100 C includes a bias circuit 110 B instead of the bias circuit 110 A. Specifically, unlike the bias circuit 110 A, the bias circuit 110 B further includes a resistance element R 4 .

The resistance element R 4 is connected in series with the capacitor C 2 a . By adjusting the resistance value of the resistance element R 4 , the level at which the capacitor C 2 a detects the input signal RFin can be adjusted.

With this configuration, like the power amplifier circuit 100 B, the power amplifier circuit 100 C can also match impedances of an amplifier and the preceding circuit, with improved linearity of power gain.

FIG. 7 is a diagram illustrating an example configuration of a power amplifier circuit 100 D according to a fourth embodiment of the present disclosure. The same or substantially the same elements as those of the power amplifier circuit 100 B are denoted by the same numerals and will not be described.

As illustrated in FIG. 7 , unlike the power amplifier circuit 100 B, the power amplifier circuit 100 D includes a bias circuit 110 C instead of the bias circuit 110 A. Specifically, unlike the bias circuit 110 A, the bias circuit 110 C further includes a transistor Q 6 .

The transistor Q 6 is diode-connected. The transistor Q 6 has a collector connected to the emitters of the transistors Q 2 a and Q 3 a and an emitter connected to the base of the transistor Q 5 a . That is, the emitter of the transistor Q 6 is supplied with the base-emitter voltage Vbe 5 of the transistor Q 5 a . The functions of the transistor Q 6 will be described with reference to FIGS. 8A and 8B .

FIG. 8A is a graph depicting a relationship between the input power Pin and the voltage Vbias in the power amplifier circuit 100 D according to the fourth embodiment of the present disclosure, and FIG. 8B is a graph depicting a change in the voltage Vbias with time at an input power Pb in the power amplifier circuit 100 D according to the fourth embodiment of the present disclosure. The input power Pb is an input power at which the input signal RFin has a comparatively high power level and at which, for example, the transistor Q 1 operates in saturation mode.

As illustrated in FIG. 8B , in the power amplifier circuit 100 D, the on and off states of the transistor Q 6 , in addition to the on and off states of the transistor Q 2 a , are switched. That is, when the collector voltage of the transistor Q 6 increases in accordance with the signal amplitude of the input signal RFin, the transistor Q 6 is brought into an on state. During a period in which the transistor Q 6 remains in the on state (time t 3 ), the waveform of the voltage Vbias is kept at a predetermined value. Specifically, the voltage Vbias is kept at a value obtained by adding together the base-emitter voltage (Vbe 5 ) of the transistor Q 5 a and the base-emitter voltage (Vbe 6 ) of the transistor Q 6 (i.e., at a value given by Vbe 5 +Vbe 6 ).

In the power amplifier circuit 100 D, as described above, the transistor Q 2 a is turned on in response to a decrease in the voltage Vbias, and the transistor Q 6 is turned on in response to an increase in the voltage Vbias. Accordingly, when the transistor Q 1 operates in saturation mode, the average value, Vbias_ave, of the voltage Vbias is smaller than that in a configuration that does not include the transistor Q 6 (see FIGS. 8B and 3C ). In the power amplifier circuit 100 A, as illustrated in FIG. 3A , the voltage Vbias may be increased in saturation mode and the linearity of the power gain may be improved, whereas the power-added efficiency may be lowered. In the power amplifier circuit 100 D, in contrast, as illustrated in FIG. 8A , the increase in the voltage Vbias in saturation mode is suppressed, and the power-added efficiency can be improved.

With the configuration described above, like the power amplifier circuit 100 B, the power amplifier circuit 100 D can also match impedances of an amplifier and the preceding circuit, with improved linearity of power gain. In addition, the power amplifier circuit 100 D, which includes the transistor Q 6 , can improve the power-added efficiency within a region where the power level of the input signal RFin is comparatively high, compared to the power amplifier circuits 100 A to 100 C.

The transistor Q 6 may be replaced with a diode element.

The power amplifier circuit 100 D may further include the resistance element R 4 , as in the power amplifier circuit 100 C.

FIG. 9 is a diagram illustrating an example configuration of a power amplifier circuit 100 E according to a fifth embodiment of the present disclosure. The same or substantially the same elements as those of the power amplifier circuit 100 A are denoted by the same numerals and will not be described.

As illustrated in FIG. 9 , in the power amplifier circuit 100 E, amplifiers are connected in multiple stages. Specifically, the power amplifier circuit 100 E includes three stages of amplifiers 10 , 20 , and 30 .

The amplifier 10 in the first stage includes a single amplifier path. The amplifier path is constituted by a transistor Q 10 , a capacitor C 10 , and a resistance element R 10 . The amplifier 20 in the second stage includes two amplifier paths. One of the amplifier paths is constituted by a transistor Q 20 x , a capacitor C 20 x , and a resistance element R 20 x . The other amplifier path is constituted by a transistor Q 20 y , a capacitor C 20 y , and a resistance element R 20 y . The amplifier 30 in the third stage includes three amplifier paths. One of the amplifier paths is constituted by a transistor Q 30 x , a capacitor C 30 x , and a resistance element R 30 x . Another amplifier path is constituted by a transistor Q 30 y , a capacitor C 30 y , and a resistance element R 30 y . The other amplifier path is constituted by a transistor Q 30 z , a capacitor C 30 z , and a resistance element R 30 z . The connection relationships and the operations of these elements are similar to those of the transistor Q 1 , the capacitor C 1 , and the resistance element R 1 in the power amplifier circuit 100 A, and thus will not be described in detail.

Bias currents or bias voltages are supplied to the bases of the transistors Q 10 , Q 20 x , and Q 20 y from bias circuits 121 to 123 , respectively. Further, bias currents or bias voltages are supplied to the transistors Q 30 x , Q 30 y , and Q 30 z from a bias circuit 130 . The configurations of the bias circuits 121 to 123 may be similar to that of the bias circuit 120 A illustrated in FIG. 1 , and thus will not be described in detail.

The bias circuit 130 includes three voltage generation circuits 201 to 203 , nine transistors Q 40 x , Q 40 y , Q 40 z , Q 41 x , Q 41 y , Q 41 z , Q 42 x , Q 42 y , and Q 42 z , the capacitor C 2 a , and resistance elements R 2 a and R 4 . The configurations of the three voltage generation circuits 201 to 203 may be similar to that of the voltage generation circuit 200 a illustrated in FIG. 1 , and thus will not be described in detail.

The transistors Q 40 x , Q 40 y , and Q 40 z and the transistors Q 42 x , Q 42 y , and Q 42 z are elements, each corresponding to the transistor Q 2 a in the bias circuit 110 A, and are configured to supply bias currents to the transistors Q 30 x , Q 30 y , Q 30 z , respectively. The transistors Q 41 x , Q 41 y , and Q 41 z are elements, each corresponding to the transistor Q 3 a in the bias circuit 110 A, and are supplied with the input signal RFin, which is detected by the capacitor C 2 a . The transistor Q 40 x is controlled by an on or off signal supplied to a terminal T 1 , the transistors Q 42 x , Q 42 y , and Q 42 z are controlled by an on or off signal supplied to a terminal T 2 , and the transistors Q 40 y , Q 40 z , Q 41 x , Q 41 y , and Q 41 z are controlled by an on or off signal supplied to a terminal T 3 .

The power amplifier circuit 100 E operates in three power modes that differ depending on the level of the output power, and the bias current is switched in accordance with the power mode in which the power amplifier circuit 100 E operates. Specifically, when the power amplifier circuit 100 E operates in the low power mode, an on signal is supplied to the terminal T 1 and an off signal is supplied to the terminals T 2 and T 3 . Accordingly, the bias circuit 121 , the bias circuit 122 , and the voltage generation circuit 201 are brought into an on state. In the low power mode, therefore, the transistors Q 10 , Q 20 x , and Q 30 x perform an amplification operation. When the power amplifier circuit 100 E operates in a middle power mode in which the output power is greater than that in the low power mode and is less than that in the high power mode, an on signal is supplied to the terminals T 1 and T 2 and an off signal is supplied to the terminal T 3 . Accordingly, the bias circuit 121 , the bias circuit 122 , the voltage generation circuit 201 , and the voltage generation circuit 203 are brought into an on state. In the middle power mode, therefore, the transistors Q 10 , Q 20 x , Q 30 x , Q 30 y , and Q 30 z perform an amplification operation. When the power amplifier circuit 100 E operates in the high power mode, an on signal is supplied to all the terminals T 1 to T 3 . Accordingly, all of the bias circuits 121 to 123 and the voltage generation circuits 201 to 203 are brought into an on state. In the high power mode, therefore, all of the transistors Q 10 , Q 20 x , Q 20 y , Q 30 x , Q 30 y , and Q 30 z perform an amplification operation. In this case, the transistors Q 41 x , Q 41 y , and Q 41 z are turned on, and accordingly the bias circuit 130 operates as a circuit having a detection function, like the bias circuit 110 A.

With the configuration described above, like the power amplifier circuit 100 A, the power amplifier circuit 100 E can also match the output impedance of the amplifier in the preceding stage and the input impedance of the amplifier in the subsequent stage, with improved linearity of power gain. In the power amplifier circuit 100 E, furthermore, the transistor size and the enabling and disabling of the detection function of the bias circuits can be switched in accordance with the three power modes. Thus, the linearity can be further improved, compared to a configuration in which the transistor size and the enabling and disabling of the detection function of the bias circuits are not switched.

As illustrated in FIG. 9 , in a configuration in which amplifiers are connected in multiple stages, the configurations of the bias circuits 121 to 123 are not limited, and the bias circuits 121 to 123 may have any of the various bias circuit configurations described above.

Additionally, the number of stages of amplifiers to be connected is not limited to three, and two or four or more stages of amplifiers may be connected.

Exemplary embodiments of the present disclosure have been described. In the power amplifier circuits 100 A to 100 E, the bias circuits 110 A to 110 C and 130 include the transistors Q 2 a , Q 40 x , Q 40 y , and Q 40 z that supply a bias current or bias voltage to the bases of the transistors Q 1 , Q 30 x , Q 30 y , and Q 30 z ; the transistors Q 3 a , Q 41 x , Q 41 y , and Q 41 z that amplify the input signal RFin supplied from a signal supply circuit (e.g., the capacitor C 2 a ) and that output the amplified signal to the emitters of the transistors Q 2 a , Q 40 x , Q 40 y , and Q 40 z ; and an impedance circuit (e.g., the resistance element R 2 a ) connected between the bases of the transistors Q 2 a and Q 3 a or between the bases of the transistors Q 40 y and Q 40 z , and Q 41 x , Q 41 y , and Q 41 z . With this configuration, a reduction in the voltage Vbias can be suppressed and, and the linearity of the power gain can be improved. In addition, the impedance on the capacitor C 2 a side seen from the input terminal is high, which can prevent or reduce the effect of the capacitor C 2 a on impedance matching between an amplifier and a circuit preceding the amplifier. Accordingly, the power amplifier circuits 100 A to 100 E can match impedances of an amplifier and the preceding circuit, with improved linearity of power gain, compared to the configuration disclosed in Japanese Unexamined Patent Application Publication No. 2003-324325. Additionally, the on and off states of the transistors Q 3 a , Q 41 x , Q 41 y , and Q 41 z are switched in accordance with the power mode of the power amplifier circuits 100 A to 100 E, which can improve the linearity of the power gain in the low power mode or the middle power mode.

The embodiments described above are intended to help easily understand the present disclosure, and are not to be used to construe the present disclosure in a limiting fashion. Various modifications or improvements can be made to the present disclosure without necessarily departing from the gist of the present disclosure, and equivalents thereof are also included in the present disclosure. That is, the embodiments may be appropriately modified in design by those skilled in the art, and such modifications also fall within the scope of the present disclosure so long as the modifications include the features of the present disclosure. For example, the elements included in the embodiments and the arrangement, materials, conditions, shapes, sizes, and the like thereof are not limited to those described in the illustrated examples, but can be modified as appropriate. Furthermore, the elements included in the embodiments can be combined as much as technically possible, and such combinations of elements also fall within the scope of the present disclosure so long as the combinations of elements include the features of the present disclosure.

While embodiments of the disclosure have been described above, it is to be understood that variations and modifications will be apparent to those skilled in the art without necessarily departing from the scope and spirit of the disclosure. The scope of the disclosure, therefore, is to be determined solely by the following claims.