Performance calculation system, performance calculation method, and electronic device

This application claims priority to Taiwan Application Serial Number 109136175, filed Oct. 19, 2020, which is herein incorporated by reference.

The present disclosure relates to a performance calculation system and a performance calculation method. More particularly, the present disclosure relates to a performance calculation system and a performance calculation method suitable for integrated circuits.

Integrated circuits are widely used in various electronic devices, and the performance (e.g., the delay time) of the integrated circuit significantly affects the user experience of the electronic device. In some methods of timing analysis, performance of an integrated circuit is usually evaluated according to characteristics of signals transmitted on a critical path, since the critical path dominates the highest frequency that the integrated circuit can be operated.

The present disclosure provides a performance calculation method suitable for a chip including a plurality of oscillator circuit systems. The plurality of oscillator circuit systems are configured to generate a plurality of oscillation signals and to sense operation states of the chip to adjust periods of the plurality of oscillation signals. The performance calculation method includes the following operations: when the chip is in a first operation state, constructing a first function according to the periods of the plurality of oscillation signals, and according to a first performance value of the chip or an approximate value of the first performance value; when the chip is in a second operation state, constructing a second function according to the periods of the plurality of oscillation signals, and according to a second performance value of the chip or an approximate value of the second performance value; adjusting coefficients of the first function or coefficients of the second function according to trajectories of a graph of the first function and a graph of the second function, so that the graph of the first function and the graph of the second function intersect at a coordinate point; and constructing a performance function of the chip according to the first function and the second function.

The present disclosure provides a performance calculation system including an electronic device and a chip. The chip is coupled with the electronic device, and includes a plurality of oscillator circuit systems and a control circuit. The plurality of oscillator circuit systems is configured to generate a plurality of oscillation signals, and configured to sense operation states of the chip to adjust periods of the plurality of oscillation signals. The control circuit is coupled with the plurality of oscillator circuit systems, and configured to transmit the plurality of oscillation signals to the electronic device. The electronic device is configured to conduct the following operations: when the chip is in a first operation state, construct a first function according to the periods of the plurality of oscillation signals, and according to a first performance value of the chip or an approximate value of the first performance value; when the chip is in a second operation state, construct a second function according to the periods of the plurality of oscillation signals, and according to a second performance value of the chip or an approximate value of the second performance value; adjust coefficients of the first function or coefficients of the second function according to trajectories of a graph of the first function and a graph of the second function, so that the graph of the first function and the graph of the second function intersect at a coordinate point; and construct a performance function of the chip according to the first function and the second function.

The present disclosure provides an electronic device for being coupled with a chip, in which the chip includes a plurality of oscillator circuit systems and a control circuit. The plurality of oscillator circuit systems are configured to generate a plurality of oscillation signals, and configured to sense operation states of the chip to adjust periods of the plurality of oscillation signals. The control circuit is coupled with the plurality of oscillator circuit systems, and configured to transmit the plurality of oscillation signals to the electronic device. The electronic device is configured to conduct the following operations: when the chip is in a first operation state, construct a first function according to the periods of the plurality of oscillation signals, and according to a first performance value of the chip or an approximate value of the first performance value; when the chip is in a second operation state, construct a second function according to the periods of the plurality of oscillation signals, and according to a second performance value of the chip or an approximate value of the second performance value; adjusting coefficients of the first function or coefficients of the second function according to trajectories of the graph of the first function and the graph of the second function, so that the graph of the first function and the graph of the second function intersects at a coordinate point; and construct a performance function of the chip according to the first function and the second function.

It is to be understood that both the foregoing general description and the following detailed description are by examples, and are intended to provide further explanation of the disclosure as claimed.

FIG. 1 is a simplified functional block diagram of a performance calculation system according to one embodiment of the present disclosure.

FIG. 2 is a simplified functional block diagram of an oscillator circuit system according to one embodiment of the present disclosure.

FIG. 3A shows a part of a flowchart of a performance calculation method according to one embodiment of the present disclosure.

FIG. 3B shows another part of the flowchart of the performance calculation method according to one embodiment of the present disclosure.

FIG. 4 is a schematic diagram of graphs of a first function and a second function according to one embodiment of the present disclosure.

FIG. 5 is a schematic diagram illustrating process of adjusting first weight values according to one embodiment of the present disclosure.

FIG. 6 is a schematic diagram illustrating process of adjusting second weight values according to one embodiment of the present disclosure.

FIG. 7 is a schematic diagram of a graph of a performance function according to one embodiment of the present disclosure.

FIG. 8A shows a part of a flowchart of the performance calculation method according to one embodiment of the present disclosure.

FIG. 8B shows another part of the flowchart of the performance calculation method according to one embodiment of the present disclosure.

FIG. 9 is a schematic diagram of the graphs of the first function and the second function according to one embodiment of the present disclosure.

FIG. 10 is a schematic diagram of the graph of the performance function according to one embodiment of the present disclosure.

Reference will now be made in detail to the present embodiments of the disclosure, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.

FIG. 1 is a simplified functional block diagram of a performance calculation system 100 according to one embodiment of the present disclosure. The performance calculation system 100 comprises a chip 110 and an electronic device 120 . The chip 110 comprises a plurality of oscillator circuit systems 112 _ 1 - 112 _ n and a control circuit 114 . The oscillator circuit systems 112 _ 1 - 112 _ n are disposed at difference locations of the chip 110 . The oscillator circuit systems 112 _ 1 - 112 _ n generate a plurality of oscillation signals OS_ 1 -OS_n having periods corresponding to variations of process, variations of voltage, variations of parasitic elements, or variations of temperature with respect to respective locations of the oscillator circuit systems 112 _ 1 - 112 _ n . The control circuit 114 is coupled with the oscillator circuit system 112 _ 1 - 112 _ n , and configured to receive the oscillation signals OS_ 1 -OS_n. The control circuit 114 is further coupled with the electronic device 120 , and configured to transmit the oscillation signals OS_ 1 -OS_n to the electronic device 120 .

The chip 110 further comprises an input/output (I/O) terminal 116 configured to receive an operating voltage VDD. The operating voltage VDD is for driving the chip 110 , that is, the operating voltage VDD may be used to drive the oscillator circuit systems 112 _ 1 - 112 _ n . For the sake of brevity, other functional blocks of the chip 110 are not shown in FIG. 1 .

In some embodiments, the control circuit 114 may be implemented by suitable signal transmission interface circuits, such as peripheral component interconnect express (PCIe) interface circuits or universal serial bus (USB) interface circuits.

The electronic device 120 is configured to calculate, according to the oscillation signals OS_ 1 -OS_n, performances of the chip 110 operated at different operating voltages VDD. In some embodiments, the electronic device 120 may be implemented by a chip tester, a computer, or other apparatus capable of performing logical operations.

FIG. 2 is a simplified functional block diagram of an oscillator circuit system 200 according to one embodiment of the present disclosure. Each of the oscillator circuit systems 112 _ 1 - 112 _ n of FIG. 1 may be implemented by the oscillator circuit system 200 of FIG. 2 , that is, each of the oscillation signals OS_ 1 -OS_n may be a combination of sensing signals Sa, Sb and Sc of FIG. 2 .

The oscillator circuit system 200 comprises oscillator circuits 210 , 220 and 230 . The oscillator circuits 210 , 220 and 230 are configured to respectively sense variations of process, variations of parasitic elements, and variations of voltage of the chip 110 .

In specific, the oscillator circuit 210 comprises a plurality of ring oscillators 10 a - 10 c , 20 a - 20 c and 30 a - 30 c . Each of the ring oscillators 10 a - 10 c , 20 a - 20 c and 30 a - 30 c may be implemented by inverters INV coupled in series. An inverter INV comprises a P-type transistor MP and an N-type transistor MN connected in series, in which the P-type transistor MP is configured to receive the operating voltage VDD.

In this embodiment, the P-type transistors MP of the respective ring oscillators 10 a - 10 c have different threshold voltages. For example, the P-type transistors MP of the ring oscillators 10 a - 10 c have a low threshold voltage, a standard threshold voltage, and a high threshold voltage, respectively.

In addition, the N-type transistors MN of the respective ring oscillators 20 a - 20 c have different threshold voltages. For example, the N-type transistors MN of the ring oscillators 20 a - 20 c have a low threshold voltage, a standard threshold voltage, and a high threshold voltage, respectively.

In addition, the N-type transistor MN and the P-type transistor MP of one of the ring oscillators 30 a - 30 c have threshold voltages different from that of the N-type transistor MN and the P-type transistor MP of other one of the ring oscillators 30 a - 30 c . For example, the N-type transistor MN and the P-type transistor MP of the ring oscillator 30 a have low threshold voltages; the N-type transistor MN and the P-type transistor MP of the ring oscillator 30 b have standard threshold voltages; the N-type transistor MN and the P-type transistor MP of the ring oscillator 30 c have high threshold voltages.

As a result, the oscillator circuit 210 is sensitive to variations of process, and thus periods of the sensing signals Sa may be used to reflect variations of process of the chip 110 .

The oscillator circuit 220 comprises ring oscillators 40 a - 40 f , in which each of the ring oscillators 40 a - 40 f may be implemented by inverters INV coupled in series. Inner wires WR (i.e., connection lines between adjacent inverters INV) of the ring oscillators 40 a - 40 f are implemented by different metal layers. For example, the inner wire WR of the ring oscillator 40 a is implemented by a first metal layer M 1 . As another example, the inner wire WR of the ring oscillator 40 b is realized by a second metal layer M 2 , and so on.

As a result, the ring oscillators 40 a - 40 f are sensitive to variations of parasitic elements (e.g., variations of parasitic resistors and parasitic capacitors caused by metal wirings), and thus periods of the sensing signals Sb can be used to reflect variations of parasitic elements of the chip 110 .

The oscillator circuit 230 comprises a ring oscillator 50 , in which the ring oscillator 50 can be implemented by inverters INV coupled in series, and a voltage control element 32 is coupled between each two adjacent inverters INV. That is, the voltage control element 32 can be deemed as a load of the inverter INV. The operating voltage VDD is used for driving the inverters INV, and also for setting impedance of the voltage control elements 32 . For example, the voltage control elements 32 may be implemented by voltage-controlled capacitors having capacitance value varies with the operating voltage VDD.

As a result, the ring oscillator 50 is sensitive to variations of the operating voltage VDD, and thus a period of the sensing signal Sc can be used to reflect variations of the operating voltage VDD.

Accordingly, since each of the oscillation signals OS_ 1 -OS_n of FIG. 1 is a combination of the sensing signals Sa, Sb and Sc of FIG. 2 , a period of each of the oscillation signals OS_ 1 -OS_n can be used to reflect variations of process, parasitic elements, and the operating voltage VDD of a corresponding location thereof. In addition, a number of ring oscillators included by each of the oscillator circuits 210 , 220 and 230 of FIG. 2 is merely an exemplary embodiment, the number of the ring oscillators may be adjusted according to practical design requirements in some embodiments.

FIG. 3A and FIG. 3B together show a flowchart of a performance calculation method 300 according to one embodiment of the present disclosure. The performance calculation system 100 of FIG. 1 may be configured to perform the performance calculation method 300 to evaluate performance of the chip 110 , which will be explained by referring to FIGS. 1, 3A and 3B .

In operation S 302 , the electronic device 120 set the operating voltage VDD to have a first voltage value V 1 to drive the oscillator circuit systems 112 _ 1 - 112 _ n . Therefore, the electronic device 120 receives the oscillation signals OS_ 1 -OS_n, and obtains the periods of the oscillation signals OS_ 1 -OS_n corresponding to the first voltage value V 1 .

In operation S 304 , the electronic device 120 measuring a path (not shown) of the chip 110 to obtain a first performance value T 1 of the chip 110 operated at the first voltage value V 1 . The said path may be a critical path of the chip 110 .

In operation S 306 , the electronic device 120 constructs a first function, as shown by the following Formula 1, according to the first performance value T 1 and the periods of the oscillation signal OS_ 1 -OS_n. The first function will be used in the following operations to evaluate a performance function of the chip 110 .

In Formula 1, the symbol “funs” represents the first function; the symbol “To” represents periods of the oscillation signals OS_ 1 -OS_n; the symbol “Ka” represents a plurality of first weight values corresponding to periods of the oscillation signals OS_ 1 -OS_n. As described above, periods of the oscillation signals OS_ 1 -OS_n vary with the operating voltage VDD, and thus can be expressed as functions each takes the first voltage value V 1 as an input.

For constructing the first function “funs,” the electronic device 120 assigns the first weight values to the periods of the oscillation signals OS_ 1 -OS_n, respectively, that is, the first weight values are coefficients of the first function “funs.” The electronic device 120 further sets the known first voltage value V 1 and first performance value T 1 (or an approximate value of the first performance value T 1 ) to be an input and an output of the first function “funs,” respectively, so as to evaluate the first weight values. That is, when the first function “funs” takes the first voltage value V 1 as the input, the first weight values render the first performance value T 1 (or the approximate value of the first performance value T 1 ) become the output of the first function “funs.” In some embodiments, a graph of the first function “funs” is depicted as a curve 410 in FIG. 4 (indicated by a solid line).

In operation S 308 , the electronic device 120 set the operating voltage VDD to be a second voltage value V 2 to drive oscillator circuit systems 112 _ 1 - 112 _ n . Therefore, the electronic device 120 receives the oscillation signals OS_ 1 -OS_n, and obtains periods of the oscillation signals OS_ 1 -OS_n corresponding to the second voltage value V 2 .

In operation S 310 , the electronic device 120 measures a path (not shown, such as the critical path) of the chip 110 , so as to obtain a second performance value T 2 of the chip 110 operated at the second voltage value V 2 .

In operation S 312 , the electronic device 120 constructs a second function, shown by the following Formula 2, according to the second performance value T 2 and periods of the oscillation signal OS_ 1 -OS_n. The second function will be used to evaluate the performance function of the chip 110 in the following operations.

In Formula 2, the symbol “funb” represents the second function; the symbol “To” represents periods of the oscillation signals OS_ 1 -OS_n; the symbol “Kb” represents a plurality of second weight values corresponding to periods of the oscillation signals OS_ 1 -OS_n. Periods of the oscillation signals OS_ 1 -OS_n can be expressed as functions each takes the second voltage value V 2 as an input, which are similar to those described above, and are omitted here.

For constructing the second function “funb,” the electronic device 120 assigns the second weight values to the periods of the oscillation signals OS_ 1 -OS_n, that is, the second weight values are coefficients of the second function “funb.” The electronic device 120 further sets the known second voltage value V 2 and second performance value T 2 (or an approximate value of the second performance value T 2 ) to be an input and an output of the second function “funb,” respectively, so as to evaluate the second weight values. That is, when the second function “funb” takes the second voltage value V 2 as the input, the second weight values render the second performance value T 2 (or the approximate value of the second performance value T 2 ) become the output of the second function “funb.” In some embodiments, a graph of the second function “funb” is depicted as a curve 420 in FIG. 4 (indicated by a dashed line).

In some embodiments, a difference between the aforesaid first performance value T 1 and the approximate value of the first performance value T 1 is 0.1-1% of the first performance value T 1 . A difference between the second performance value T 2 and the approximate value of the second performance value T 2 is 0.1-1% of the second performance value T 2 .

In some embodiments, the electronic device 120 configures the chip 110 to operate at a first temperature in operations S 302 -S 304 , so as to obtain the first performance value T 1 of the chip 110 corresponding to the first temperature. In operation S 306 , the electronic device 120 further sets the known first temperature and first performance value T 1 (or the approximate value of the first performance value T 1 ) to be the input and the output of the first function “funs,” respectively, so as to evaluate the first weight values. Then, the electronic device 120 configures the chip 110 to operate at a second temperature in operations S 308 -S 310 , so as to obtain the second performance value T 2 of the chip 110 corresponding to the second temperature. In operation S 312 , the electronic device 120 further sets the known second temperature and second performance value T 2 (or approximate value of the second performance value T 2 ) as the input and the output of the second function “funb,” respectively, so as to evaluate the second weight values. Accordingly, the first performance value T 1 and the second performance value T 2 of this disclosure are measured in different operation states of the chip 110 , the said different operation states may include different operating voltages VDD and/or different temperatures of the chip 110 .

Then, in operations S 314 and S 316 , the electronic device 120 determines whether trajectories of the graph of the first function “funs” (e.g., the curve 410 ) and the graph of the second function “funb” (e.g., the curve 420 ) match a predetermined rule. The said predetermined rule is that the graph of the first function “funs” and the graph of the second function “funb” intersects at a first coordinate point N 1 , in which the first coordinate point N 1 corresponds to a third performance value T 3 . The electronic device 120 adjusts the first weight values of the first function “funs” and/or the second weight values of the second function “funb” according to a determination result.

In operation S 314 , the electronic device 120 determines that if the output of the first function “funs” is greater than or equal to the second performance value T 2 when the first function “funs” takes the second voltage value V 2 as the input. If so, the electronic device 120 conducts operation S 316 to adjust the first weight values, so that the output of the first function “funs” becomes smaller than the second performance value T 2 when the first function “funs” takes the second voltage value V 2 as the input. If not, the electronic device 120 conducts operation S 318 .

For instance, referring to FIG. 5 , the curve 510 (indicated by a dashed-dotted line) is the graph of the first function “funs” obtained by the electronic device 120 after operations S 302 -S 306 are finished in one operation cycle. In this situation, when the first function “funs” takes the second voltage value V 2 as the input, the output thereof is a fourth performance value T 4 . Since the fourth performance value T 4 is greater than the second performance value T 2 , the electronic device 120 adjusts the first weight values of the first function “funb” becomes smaller than the first performance value T 1 when the second function “funb” takes the first voltage value V 1 as the input. If not, the electronic device 120 conducts operation S 322 .

For example, referring to FIG. 6 , a curve 610 (indicated by a dashed-dotted line) is the graph of the second function “funb” obtained by the electronic device 120 after operations S 308 -S 312 are finished in one operation cycle. In this case, when the second function “funb” takes the first voltage value V 1 as the input, the output thereof is a sixth performance value T 6 . Since the sixth performance value T 6 is greater than the first performance value T 1 , the electronic device 120 adjusts the second weight values of the second function “funb”, until the graph of the second function “funb” becomes the curve 420 , that is, until the output of the second function “funb” is a seventh performance value T 7 smaller than the first performance value T 1 when the second function “funb” takes the first voltage value V 1 as the input.

Accordingly, the electronic device 120 may execute polynomial regression or interpolation for multiple times according to performance of the chip 110 to evaluate the aforesaid first weight values “Ka” and the second weight values “Kb.” Then, the electronic device 120 conducts operations S 322 -S 326 of FIG. 3B to calculate the performance function of the chip 110 according to the first function “funs” and the second function “funb.” The performance function is for evaluating corresponding performances of the chip 110 when receiving different operating voltages VDD, which will be explained by referring to FIGS. 3B, 4 and 7 .

As shown in FIG. 4 , the curve 410 comprises a first curve segment La and a second curve segment Lb at a left side and a right side of the coordinate point N 1 , respectively. The curve 420 comprises a third curve segment Lc and a fourth curve segment Ld at a left side and a right side of the coordinate point N 1 , respectively.

In operation S 322 , the electronic device 120 selects one of the first curve segment La and the third curve segment Lc, in which the selected curve segment corresponds to a greater one among two performance values of the chip 110 obtained by respectively mapping the operating voltage VDD through the first curve segment La and the third curve segment Lc, and the selected curve segment will be a first part Ga of a graph of the performance function. In this embodiment, as shown in FIG. 7 , the electronic device 120 selects the first curve segment La as the first part Ga of the graph of the performance function.

In operation S 324 , the electronic device 120 selects one of the second curve segment Lb and the fourth curve segment Ld, in which the selected curve segment corresponds to a greater one among two performance values of the chip obtained by respectively mapping the operating voltage VDD through the second curve segment Lb and the fourth curve segment Ld, and the selected curve segment will be the second part Gb of the graph of the performance function. In this embodiment, as shown in FIG. 7 , the electronic device 120 selects the fourth curve segment Ld as the second part Gb of the performance function. As a result, the electronic device 120 generate the graph of the performance function in operation S 320 , which is the curve 700 of FIG. 7 including the first part Ga, the second part Gb, and the coordinate point N 1 .

In operation S 326 , the electronic device 120 constructs the performance function according to the curve 700 . In some embodiments, the performance of the chip 110 can be expressed by the following Formula 3, in which the symbol “funt” represents the performance function of the chip 110 .

funt(funa(V),funb(V))  Formula 3

As can be known from FIG. 7 , in some embodiments, outputs (i.e., the range) of the performance function comprises the first performance value T 1 or the approximate value of the first performance value T 1 , second performance value T 2 or the approximate value of the second performance value T 2 , and a third performance value T 3 corresponding to the coordinate point N 1 .

FIG. 8A and FIG. 8B together show a flowchart of a performance calculation method 800 according to one embodiment of the present disclosure. The performance calculation system 100 of FIG. 1 can be configured to execute the performance calculation method 800 to evaluate the performance of the chip 110 . Operations S 802 -S 812 of the performance calculation method 800 are similar to operations S 302 -S 312 of the performance calculation method 300 , respectively.

For example, referring to FIG. 9 , to construct the first function “funs” in this embodiment, the electronic device 120 assigns the first weight values to the periods of the oscillation signals OS_ 1 -OS_n, respectively, as the coefficients of the first function “funs.” The electronic device 120 further sets the known first voltage value V 1 ′ and first performance value T 1 ′ (or a approximate value of the first performance value T 1 ′) as the input and output of the first function “funs,” respectively, to evaluate the first weight values. In some embodiments, the curve 910 (indicated by a solid line) of FIG. 9 is the graph of the first function “funs.”

As another example, to construct the second function “funb” in this embodiment, the electronic device 120 assigns the second weight values to the periods of the oscillation signal OS_ 1 -OS_n, respectively, as the coefficients of the second function “funb.” The electronic device 120 further sets the known second voltage value V 2 ′ and second performance value T 2 ′ (or an approximate value of the second performance value T 2 ′) to be the input and the output of the second function “funb,” respectively, to evaluate the second weight values. In some embodiments, the curve 920 (indicated by a dashed line) of FIG. 9 is the graph of the second function “funb.” Since operations S 802 -S 812 are similar to operations S 302 -S 312 , those descriptions are omitted here. The following paragraphs will explain the performance calculation method 800 from operation S 814 .

In operation S 814 , the electronic device 120 determines if the output of the first unction “funs” is smaller than or equal to the second performance value T 2 ′ when the input of the first function “funs” is the second voltage value V 2 ′. If so, the electronic device 120 conducts operation S 816 to adjust the first weight values, so that the output of the first function “funs” becomes greater than the second performance value T 2 ′ when the input of the first function “funs” is the second voltage value V 2 ′. If not, the electronic device 120 conducts operation S 818 .

In operation S 818 , the electronic device 120 determines if the output of the second function “funb” is smaller than or equal to the first performance value T 1 ′ when the input of the second function “funb” is the first voltage value V 1 ′. If so, the electronic device 120 executes operation S 820 to adjust the second weight values, so that the output of the second function “funb” becomes larger than the first performance value T 1 ′ when the input of the second function “funb” is the first voltage value V 1 ′. If not, the electronic device 120 conducts operation S 822 .

In other words, the performance calculation methods 300 and 800 have different rules for trajectories of the graphs of the first function “funs” and the second function “funb.” Therefore, the trajectories of the graphs of the first function “funs” and the second function “funb” are different in FIGS. 4 and 9 .

As shown in FIG. 9 , the curve 910 comprises a first curve segment La′ and a second curve segment Lb′ at a left side and a right side of a coordinate point N 1 ′, respectively. The curve 920 comprises a third curve segment Lc′ and a fourth curve segment Ld′ at a left side and a right side of a coordinate point N 1 ′, respectively.

In operation S 822 , the electronic device 120 selects one of the first curve segment La′ and the third curve segment Lc′, in which the selected curve segment corresponds to a smaller one among two performance values of the chip 110 obtained by respectively mapping the operating voltage VDD through the first curve segment La′ and the third curve segment Lc′. The selected curve segment will be the first part Ga′ of the graph of the performance function. In this embodiment, as shown in FIG. 10 , the electronic device 120 selects the first curve segment La′ as the first part Ga′ of the graph of the performance function.

In operation S 824 , the electronic device 120 selects one of the second curve segment Lb′ and the fourth curve segment Ld′, in which the selected curve segment corresponds to a smaller one among two performance values of the chip 110 obtained by respectively mapping the operating voltage VDD through the second curve segment Lb′ and the fourth curve segment Ld′. The selected curve segment will be the second part Gb′ of the graph of the performance function. In this embodiment, as shown in FIG. 10 . The electronic device 120 selects the fourth curve segment Ld′ as the second part Gb′ of the graph of the performance function. As a result, the electronic device 120 generates the graph of the performance function in operation S 820 , which is a curve 1000 of FIG. 10 including the aforesaid first part Ga′, the second part Gb′, and the coordinate point N 1 ′.

In operation S 826 , the electronic device 120 constructing the performance function according to the curve 1000 . The performance function can be expressed by a formula similar to the Formula 3, and thus those descriptions will not be repeated here. As shown in FIG. 10 , in some embodiments, the outputs (i.e., the range) of the performance function comprises the first performance value T 1 ′ or the approximate value of the first performance value T 1 ′, the second performance value T 2 ′ or the approximate value of the second performance value T 2 ′, and a third performance value T 3 ′ corresponding to the coordinate point N 1 ′.

As can be appreciated from the foregoing descriptions, the performance calculation system 100 and the performance calculation methods 300 and 800 of the present disclosure take into account various variations of the chip 110 to precisely evaluate the performance of the chip 110 (e.g., the delay time of the critical path).

In addition, the calculation process of the performance calculation methods 300 and 800 are simple, helping to reduce periods of time analysis and requirements of relative hardware.

Certain terms are used throughout the description and the claims to refer to particular components. One skilled in the art appreciates that a component may be referred to as different names. This disclosure does not intend to distinguish between components that differ in name but not in function. In the description and in the claims, the term “comprise” is used in an open-ended fashion, and thus should be interpreted to mean “include, but not limited to.” The term “couple” is intended to compass any indirect or direct connection. Accordingly, if this disclosure mentioned that a first device is coupled with a second device, it means that the first device may be directly or indirectly connected to the second device through electrical connections, wireless communications, optical communications, or other signal connections with/without other intermediate devices or connection means.

The term “and/or” may comprise any and all combinations of one or more of the associated listed items. In addition, the singular forms “a,” “an,” and “the” herein are intended to comprise the plural forms as well, unless the context clearly indicates otherwise.

Other embodiments of the present disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the present disclosure disclosed herein. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the present disclosure being indicated by the following claims.