Pixel circuit and display panel

This application claims priority under 35 USC § 119 to Korean Patent Application No. 10-2020-0040473, filed on Apr. 2, 2020, in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein in its entirety.

The present disclosure generally relates to displays, and more particularly relates to a pixel circuit and a display panel with time-division pixel sensing and compensation.

When emission wavelengths of light-emitting diodes (LEDs), and in particular, micro-LEDs that may use inorganic materials as light-emitting materials and have a micrometer-order magnitude, may change according to the amount of current, it may be difficult to apply a driving method that expresses grayscale based on the amount of current as with organic LEDs.

According to an exemplary embodiment of the present disclosure, inorganic or micrometer-order light-emitting diodes may be applied as light-emitting elements in a display panel where the pixel circuits are operable using a time-division sensing and driving method.

An embodiment provides a pixel circuit for driving a light-emitting diode. An embodiment provides a display panel including a light-emitting diode.

Additional embodiments may be set forth in part in the description which follows and, in part, may be apparent from the description, or may be learned by practice of the presented embodiments.

A display panel according to an exemplary embodiment includes a plurality of sub-pixels, a timing control unit, and a data sensing driving unit. Each of the plurality of sub-pixels includes a light-emitting element and a pixel circuit configured to output a driving current to the light-emitting element. The pixel circuit includes a first transistor and a second transistor. The timing control unit is configured to generate bias data based on first characteristic information of the first transistor, and generate correction data based on second characteristic information of the second transistor. The data sensing driving unit is configured to receive the bias data and the correction data, and output, to the pixel circuit, a bias voltage corresponding to the bias data and a grayscale voltage corresponding to the correction data.

The pixel circuit may include the first transistor configured to output the driving current to the light-emitting element, wherein the first transistor is connected to the light-emitting element, the first driving circuit configured to control a magnitude of the driving current based on the bias voltage, and a second driving circuit configured to control a pulse width of the driving current based on the grayscale voltage, wherein the second driving circuit includes the second transistor.

A pixel according to an exemplary embodiment includes a pixel circuit connected to a light-emitting element. The pixel circuit includes: a first transistor connected between a first power line and the light-emitting element, the first power line to which a first driving voltage is applied; a fourth transistor including a gate, a first connection end, and a second connection end, the gate being connected to a scan line transmitting a scan signal, the first connection end being connected to a first data line to which a bias voltage is applied, and the second connection end being connected to a gate of the first transistor; a fifth transistor including a gate, a first connection end, and a second connection end, the gate being connected to the scan line, the first connection end being connected to a first sensing line to which a first control voltage is applied, the second connection end being connected to a source of the first transistor; a first capacitor connected between the gate and the source of the first transistor; a second transistor including a gate, a drain, and a source, the drain being connected to the gate of the first transistor, and the source being connected to a second sensing line to which a second control voltage is applied; and a third transistor including a gate, a first connection end, and a second connection end, the gate being connected to the scan line, the first connection end being connected to a second data line to which a grayscale voltage is applied, and the second connection end being connected to the gate of the second transistor.

A display panel according to an exemplary embodiment includes: a light-emitting element; a first transistor connected between a first power line and the light-emitting element, the first power line to which a first driving voltage is applied; a fourth transistor including a gate, a first connection end, and a second connection end, the gate being connected to a scan line transmitting a scan signal, the first connection end being connected to a first data line to which a bias voltage is applied, and the second connection end being connected to a gate of the first transistor; a fifth transistor including a gate, a first connection end, and a second connection end, the gate being connected to the scan line, the first connection end being connected to a first sensing line to which a first control voltage is applied, the second connection end being connected to a source of the first transistor; a first capacitor connected between the gate and the source of the first transistor; a second transistor including a gate, a drain, and a source, the drain being connected to the gate of the first transistor, and the source being connected to a second sensing line to which a second control voltage is applied; a third transistor including a gate, a first connection end, and a second connection end, the gate being connected to the scan line, the first connection end being connected to a second data line to which a grayscale voltage is applied, and the second connection end being connected to the gate of the second transistor; and a second capacitor including a first electrode and a second electrode, the first electrode being connected to a voltage line to which a sweep voltage that changes monotonically during a preset period is applied, and the second electrode being connected to the gate of the second transistor.

A display device according to an exemplary embodiment includes: a plurality of pixels each including a first transistor, a second transistor connected to a gate terminal of the first transistor, and an inorganic or micrometer-order light-emitting element connected to an output terminal of the first transistor; a time-division controller generating bias data based on first characteristic information of the first transistor, and generating correction data based on second characteristic information of the second transistor; and a sensing driver receiving the bias data and the correction data, and providing, to at least one of the plurality of pixels, a bias voltage corresponding to the bias data and a correction voltage corresponding to the correction data.

The display device may include: a first driving circuit connected to the output terminal of the first transistor and controlling a magnitude of a driving current supplied to the light-emitting element based on the bias voltage; and a second driving circuit comprising the second transistor and controlling a pulse width of the driving current based on the correction voltage.

The second driving circuit may include a third transistor and a correction capacitor each connected to a gate terminal of the second transistor, wherein the correction voltage is responsive to the correction capacitor; and the first driving circuit may include a fourth transistor connected to the gate terminal of the first transistor, a fifth transistor connected to the output terminal of the first transistor, and a bias capacitor connected between the gate terminal and the output terminal of the first transistor, wherein the bias voltage is responsive to the bias capacitor.

Other embodiments than those described above may become apparent from the drawings, claims, and/or detailed description of this disclosure.

The above and other embodiments of the present disclosure will be more apparent from the following description taken in conjunction with the accompanying drawings, in which:

FIG. 1 is a schematic block diagram of a display panel according to an embodiment;

FIG. 2 is a block diagram of a data sensing driving unit according to an embodiment;

FIG. 3 is a circuit diagram of a pixel according to an embodiment;

FIG. 4 is a timing diagram during a frame time period for driving the pixel of FIG. 3 in a display mode;

FIG. 5 is a circuit diagram of a pixel and a data sensing circuit connected to the pixel, according to an embodiment; and

FIG. 6 is a timing diagram for driving the pixel and the data sensing circuit of FIG. 4 in a sensing mode.

Reference will now be made in detail to embodiments, examples of which are illustrated in the accompanying drawings, wherein like reference numerals may refer to like elements throughout. In this regard, the present embodiments may have different forms and should not be construed as being limited to the descriptions set forth herein. Accordingly, embodiments are described below, with reference to the figures, to explain aspects of the present description by means of example, without limitation thereto. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. Throughout the disclosure, the expression “at least one of a, b or c” may indicate only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof.

As the present disclosure allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the written description. Features, effects, and methods achieving the features and effects will become apparent from the exemplary embodiments described below with reference to the drawings. However, the present disclosure is not limited to the exemplary embodiments described below, and may be implemented in various forms.

Hereinafter, embodiments of the present disclosure will be described in greater detail with reference to the accompanying drawings. To clearly describe the present disclosure, parts irrelevant to the description have been omitted, and in the description with reference to the drawings, the same or like components may be given the same or like reference numerals, where redundant descriptions thereof may be omitted.

While such terms as “first,” “second,” etc., may be used to describe various elements, such elements must not be limited to the above terms. The above terms are used only to distinguish one element from another. In the following embodiments, an expression used in the singular encompasses the expression of the plural, unless it has a clearly different meaning in the context. When a portion is referred to as being “connected” to another portion, the portion may be directly connected to the other portion, indirectly connected to the other portion, and the portion may also be “electrically connected” to the other portion with an element therebetween. When a portion is referred to as including an element, another element other than the element may be further included, rather than excluding the existence of the other element, unless otherwise described.

FIG. 1 illustrates a display panel 100 according to an embodiment. FIG. 2 illustrates part of a timing control unit 140 of FIG. 1 according to an embodiment.

Referring to FIG. 1 , the display panel 100 may include a display unit 110 , a gate sweep driving unit 120 , a data sensing driving unit 130 , a timing control unit 140 , and a voltage generating unit 150 .

The display unit 110 includes pixels PX. Although only one pixel PX is shown in FIG. 1 for ease of understanding, a plurality of pixels PX may be arranged on the display unit 110 . The pixels PX may be arranged in a matrix form including, for example, a plurality of pixel rows extending in a first direction (i.e., a row direction) and a plurality of pixel columns extending in a second direction (i.e., a column direction).

Two or more pixels PX may constitute a unit pixel. The pixel PX shown in FIG. 1 may correspond to a sub-pixel constituting a part of a unit pixel.

The pixels PX of the display unit 110 may be configured to receive an updated bias voltage DATA_bias and an updated grayscale voltage DATA_grey every frame time period, and emit light by a driving current having a magnitude corresponding to the bias voltage DATA_bias and a pulse width corresponding to the grayscale voltage DATA_grey, to thereby display an image corresponding to image data DATA1 of a frame.

Each pixel PX may be connected to a scan line SL[N] and a voltage line VL extending in, for example, the row direction, and may be connected to first and second data lines DL 1 and DL 2 , and first and second sensing lines SSL 1 and SSL 2 extending in, for example, the column direction. Each pixel PX may be connected to first and second power lines PL 1 and PL 2 .

When the display unit 110 includes the pixels PX arranged in the matrix form, the display unit 110 may include a plurality of scan lines including the scan line SL[N], a plurality of voltage lines including the voltage line VL, a plurality of first data lines including the first data line DL 1 , a plurality of second data lines including the second data line DL 2 , a plurality of first sensing lines including the first sensing line SSL 1 , a plurality of second sensing lines including a second sensing line SSL 2 , and a plurality of first power lines including the first power line PL 1 . The display unit 110 may also include a plurality of second power lines PL 2 including the second power line PL 2 .

The scan lines SL[N] and the voltage lines VL may extend in, for example, the row direction and may be connected to the gate sweep driving unit 120 . The first data lines DL 1 , the second data lines DL 2 , the first sensing lines SSL 1 , and the second sensing lines SSL 2 may extend in, for example, the column direction and may be connected to the data sensing driving unit 130 . The first power lines PL 1 and the second power lines PL 2 may be connected to the voltage generating unit 150 .

Hereinafter, the scan line SL[N], the voltage line VL, the first and second data lines DL 1 and DL 2 , the first and second sensing lines SSL 1 and SSL 2 , and the first and second power lines PL 1 and PL 2 , all of which are connected to the pixel PX, may be described in greater detail.

Each pixel PX includes a light-emitting element and a pixel circuit that outputs a driving current to the light-emitting element. The light-emitting element may be an inorganic light emitting diode (LED) manufactured using an inorganic material. The light-emitting element may be a micro-LED having a dimensional magnitude on the order of, for example, 100 micrometer (μm) or less. The light-emitting element may be an LED that emits light of a specific color, such as a red LED, a green LED, and a blue LED.

The pixel circuit includes a plurality of transistors including first and second transistors and first and second capacitors. The pixel circuit may store a bias voltage DATA_bias and a grayscale voltage DATA_grey in response to a scan signal, and may output, to the light-emitting element, a driving current having a magnitude determined based on the bias voltage DATA_bias and a pulse width determined based on the grayscale voltage DATA_grey. The light-emitting element emits light having an intended wavelength and brightness by a driving current having a controlled magnitude and a controlled pulse width during an intended emission duration, such that the grayscale may be accurately expressed.

The pixel circuit includes the first transistor, a first driving circuit, and a second driving circuit including the second transistor. The first transistor is connected to the light-emitting element and outputs a driving current to the light-emitting element. A magnitude of the driving current is determined according to a magnitude of a voltage applied between a gate and a source of the first transistor.

The first driving circuit is configured to control the magnitude of the driving current based on the bias voltage DATA_bias. The first driving circuit may apply a voltage for maintaining substantially constant the magnitude of the driving current based on the bias voltage DATA_bias between the gate and the source of the first transistor.

The second driving circuit includes a second transistor configured to control a pulse width of the driving current based on the grayscale voltage DATA_grey. The second driving circuit may receive the grayscale voltage DATA_grey and a sweep voltage Sweep that changes monotonically, such as but not limited to substantially linearly, during a preset period, and may control an emission duration of the light-emitting element based on the grayscale voltage DATA_grey and the sweep voltage Sweep. The pixel circuit may be described in greater detail below with reference to FIG. 3 .

The gate sweep driving unit 120 may generate a plurality of scan signals SCAN and the sweep voltage Sweep based on a first control signal CONT 1 provided from the timing control unit 140 . The gate sweep driving unit 120 may sequentially generate the scan signals SCAN. The scan signals SCAN generated sequentially may be supplied to the pixels PX via the scan lines SL[N]. The pixel PX may receive the scan signal SCAN via the scan line SL[N].

The gate sweep driving unit 120 may generate a sweep voltage Sweep that changes substantially linearly during a preset period and provide the sweep voltage Sweep to the pixels PX via voltage lines VL. The sweep voltage Sweep may be a voltage having a magnitude that substantially linearly increases or decreases during a preset period, such as an emission period, and a constant magnitude during a period, such as a data writing period, other than the preset period. The pixel PX may receive the sweep voltage Sweep via the voltage line VL.

The data sensing driving unit 130 may generate a bias voltage DATA_bias, a grayscale voltage DATA_grey, and first and second control voltages CV 1 and CV 2 based on bias data DATA2, correction data DATA3, and a control signal CONT 2 , which are provided from the timing control unit 140 in a display mode in which the display panel 100 displays an image.

The data sensing driving unit 130 generates a bias voltage DATA_bias by digital-to-analog conversion of the bias data DATA2 based on the second control signal CONT 2 , amplifies the bias voltage DATA_bias, and outputs the amplified bias data DATA2 to the first data line DL 1 . The data sensing driving unit 130 generates a grayscale voltage DATA_grey by digital-to-analog conversion of the correction data DATA3 based on the second control signal CONT 2 , amplifies the grayscale voltage DATA_grey, and outputs the amplified grayscale voltage DATA_grey to the second data line DL 2 . The data sensing driving unit 130 may generate a second control voltage CV 2 based on the second control signal CONT 2 in a display mode and output the second control voltage CV 2 to the second sensing line SSL 2 , and may generate a first control voltage CV 1 and output the first control voltage CV 1 to the first sensing line SSL 1 . The pixel PX may receive the bias voltage DATA_bias via the first data line DL 1 , receive the grayscale voltage DATA_grey via the second data line DL 2 , and receive the first and second control voltages CV 1 and CV 2 via the first and second sensing lines SSL 1 and SSL 2 , respectively.

The data sensing driving unit 130 may generate a reference bias voltage, a reference grayscale voltage, and a reference source voltage in a sensing mode for sensing characteristics of the first and second transistors in the pixel PX, and generate first and second sensing data SD 1 and SD 2 by sensing magnitudes of currents output by the first and second transistors via the first and second sensing lines SSL 1 and SSL 2 , respectively. The data sensing driving unit 130 may provide the first and second sensing data SD 1 and SD 2 to the timing control unit 140 .

The data sensing driving unit 130 may include a sensing circuit for generating the first and second sensing data SD 1 and SD 2 . The sensing circuit may include a plurality of switches, and the switches may be controlled based on the second control signal CONT 2 . The sensing circuit may be described in greater detail below with reference to FIG. 5 .

The voltage generating unit 150 generates first and second driving voltages PVDD and PVSS for driving the display panel 100 . The first driving voltage PVDD is applied to the first power line PL 1 , and the second driving voltage PVSS is applied to the second power line PL 2 . In an emission interval in which the light-emitting element emits light, a voltage level of the first driving voltage PVDD may be higher than a voltage level of the second driving voltage PVSS.

The timing control unit 140 may control the display unit 110 by controlling the gate sweep driving unit 120 , the data sensing driving unit 130 , and the voltage generating unit 150 . The timing control unit 140 may receive a control signal CONT and the image data DATA1 from an external device. The timing control unit 140 may generate first and second control signals CONT 1 and CONT 2 by using the control signal CONT. The timing control unit 140 may generate bias data DATA2 based on first characteristic information of the first transistor. The timing control unit 140 may generate correction data DATA3 by correcting the image data DATA1 based on second characteristic information of the second transistor.

Referring to FIG. 2 , the timing control unit 140 according to an embodiment may include a compensation coefficient calculating unit 142 , a compensation unit 144 , and a memory 146 .

The compensation coefficient calculating unit 142 may receive first and second sensing data SD 1 and SD 2 . The compensation coefficient calculating unit 142 may calculate a first compensation coefficient for compensating for a variation in characteristics of first transistors of the pixel circuits based on the first sensing data SD 1 . The compensation coefficient calculating unit 142 may calculate a second compensation coefficient for compensating a variation in characteristics of second transistors of the pixel circuits based on the second sensing data SD 2 . Characteristics of a transistor may include a threshold voltage and/or mobility of the transistor. The first compensation coefficient may be referred to as the first characteristic information of the first transistor, and the second compensation coefficient may be referred to as the second characteristic information of the second transistor. The first characteristic information and the second characteristic information calculated by the compensation coefficient calculating unit 142 may be stored in the memory 146 .

The compensation unit 144 may generate bias data DATA2 for compensating for the variation in characteristics of the first transistors based on the first compensation coefficient. The compensation unit 144 may provide the bias data DATA2 to the data sensing driving unit 130 .

The compensation unit 144 may receive the image data DATA1. The compensation unit 144 may generate correction data DATA3 by correcting the image data DATA1 based on the second compensation coefficient. The correction data DATA3 is data obtained by correcting the image data DATA1 to compensate for the variation in characteristics of the second transistors. The compensation unit 144 may provide the correction data DATA3 to the data sensing driving unit 130 .

Referring back to FIG. 1 , the display panel 100 may have a display interval in which an image is displayed and a non-display interval in which an image is not displayed. The display interval may include a plurality of frame time periods. Each frame time period includes a data writing period during which the pixel circuit stores a bias voltage and a grayscale voltage in response to a scan signal, and an emission period during which the light-emitting element may emit light.

The non-display interval includes a first sensing interval for sensing a current output from the first transistor to compensate for the variation in characteristics of the first transistors of the pixel circuits, and a second sensing interval for sensing a current output from the second transistor to compensate for the variation in characteristics of the second transistors of the pixel circuits.

A reference bias voltage and a reference source voltage are applied to the first transistor during the first sensing interval, and the data sensing driving unit 130 may sense a current output from the first transistor while changing a level of the reference bias voltage. A reference grayscale voltage and a reference source voltage are applied to the second transistor during the second sensing interval, and the data sensing driving unit 130 may sense a current output from the second transistor while changing a level of the reference grayscale voltage.

The second sensing interval may be temporally arranged immediately after the first sensing interval. The first sensing interval and the second sensing interval may be temporally arranged immediately after or immediately before the display interval. The first sensing interval and the second sensing interval may exist for each preset period.

First transistors included in the pixels PX preferably have the same characteristics, but may have different characteristics due to process errors, deterioration, etc. When a variation in characteristics of the first transistors is generated, a variation in magnitudes of driving currents output from pixel circuits of the pixels PX to light-emitting elements may be generated. Accordingly, when the variation in magnitudes of the driving currents is generated, the light-emitting elements of the pixels PX may emit light having different levels of brightness, and wavelengths of the emitted light may also be different. According to the present embodiment, the variation in magnitudes of the driving currents caused by the variation in characteristics of the first transistors may be compensated by a bias voltage DATA_bias applied to the pixel PX.

Second transistors included in the pixels PX preferably have the same characteristics, but may have different characteristics due to process errors, deterioration, etc. When a variation in characteristics of the second transistors is generated, pulse widths of the driving currents output from the respective pixel circuits of the pixels PX to the light-emitting elements might not be accurately controlled. When the pulse widths are not accurately controlled, grayscales expressed by the respective pixels PX become inaccurate. According to the present embodiment, the variation in pulse widths of the driving currents caused by the variation in characteristics of the second transistors may be compensated by a grayscale voltage DATA_grey applied to the pixel PX.

FIG. 3 illustrates an exemplary electronic circuit for a pixel PX according to an embodiment.

Referring to FIG. 3 , the pixel PX includes a light-emitting element mLED and a pixel circuit that outputs a driving current Id to the light-emitting element mLED. The pixel circuit includes a first transistor T 1 , a first driving circuit 10 , and a second driving circuit 20 .

The light-emitting element mLED may be a micro-LED that uses an inorganic material as a light-emitting material and has a micrometer-order dimensional magnitude. As shown in FIG. 3 , an anode of the light-emitting element mLED may be connected to a source of the first transistor T 1 , and a cathode of the light-emitting element mLED may be connected to a second power line PL 2 to which a second driving voltage PVSS is applied. As another alternate example, the light-emitting element mLED may be connected between a first power line PL 1 to which a first driving voltage PVDD is applied and a drain of the first transistor T 1 .

The first transistor T 1 may be an n-type metal oxide semiconductor field-effect transistor (MOSFET) as shown in FIG. 3 . Second, third, fourth, and fifth transistors T 2 , T 3 , T 4 , and T 5 may also be n-type MOSFETs. The first to fifth transistors T 1 to T 5 may be thin-film transistors. Each of the first to fifth transistors T 1 to T 5 may include a semiconductor material of a metal oxide. For example, each of the first to fifth transistors T 1 to T 5 may include an active layer formed of a metal oxide.

Hereinafter, an embodiment in which the first to fifth transistors T 1 to T 5 of the pixel PX are n-type MOSFETs will be described as shown in FIG. 3 . However, the first to fifth transistors T 1 to T 5 of the pixel PX may alternately be p-type MOSFETs, and accordingly, a connection relationship of the pixel circuit may be changed. That is, the spirit of the present disclosure may be similarly applied to a pixel PX including a p-type MOSFET and a display panel including the same.

The first transistor T 1 includes a gate connected to a first node A, a drain connected to the first power line PL 1 to which the first driving voltage PVDD is applied, and a source connected to the anode of the light-emitting element mLED. The first transistor T 1 outputs a driving current Id of which a magnitude is controlled according to a magnitude of a voltage applied to the gate of the first transistor T 1 .

The first driving circuit 10 includes the fourth transistor T 4 , the fifth transistor T 5 , and a first or bias capacitor Cst. The first driving circuit 10 is connected to a scan line SL[N] that transmits a scan signal SCAN[N], a first data line DL 1 to which a bias voltage DATA_bias is applied, and a first sensing line SSL 1 to which a first control voltage CV 1 is applied.

The fourth transistor T 4 includes a gate connected to the scan line SL[N], a first connection end connected to the first data line DL 1 , and a second connection end connected to the first node A and the gate of the first transistor T 1 . The fourth transistor T 4 applies a bias voltage DATA_bias to the gate of the first transistor T 1 in response to the scan signal SCAN[N].

The fifth transistor T 5 includes a gate connected to the scan line SL[N], a first connection end connected to the first sensing line SSL 1 , and a second connection end connected to the source of the first transistor T 1 . The fifth transistor T 5 applies a first control voltage CV 1 to the source of the first transistor T 1 in response to the scan signal SCAN[N].

The first capacitor Cst includes a first electrode connected to the node A and the first gate of the first transistor T 1 and a second electrode connected to the source of the first transistor T 1 . The first capacitor Cst stores a difference between the bias voltage DATA_bias and the first control voltage CV 1 transmitted by the fourth transistor T 4 and the fifth transistor T 5 , respectively, in response to the scan signal SCAN[N]. Because the first capacitor Cst is connected between the gate and the source of the first transistor T 1 , the first transistor T 1 outputs, to the light-emitting element mLED, a driving current Id having a magnitude determined based on a voltage stored in the first capacitor Cst.

The bias voltage DATA_bias is a voltage corresponding to bias data DATA2 generated based on characteristics such as a threshold voltage and/or mobility of the first transistor T 1 , sensed by the data sensing driving unit 130 of FIG. 1 . That is, because the bias voltage DATA_bias is a voltage that causes the driving current Id to have a preset magnitude, the driving current Id may have a constant magnitude even if characteristics of the first transistor T 1 are irregular due to process errors, deterioration, changes over time, or the like.

The second driving circuit 20 includes the second transistor T 2 , the third transistor T 3 , and a second sweep or grayscale correction capacitor Cswp. The second driving circuit 20 is connected to the scan line SL[N] that transmits the scan signal SCAN[N], a second data line DL 2 to which a grayscale voltage DATA_grey is applied, a second sensing line SSL 2 to which a second control voltage CV 2 is applied, and a voltage line VL to which a sweep voltage Sweep is applied, the sweep voltage Sweep changing substantially linearly during a preset period.

The second transistor T 2 includes a gate connected to a second node B, a drain connected to the gate of the first transistor T 1 , and a source connected to the second sensing line SSL 2 . The second transistor T 2 may turn off the first transistor T 1 by applying a second control voltage CV 2 to the gate of the first transistor T 1 according to a voltage applied to the gate of the second transistor T 2 .

The third transistor T 3 includes a gate connected to the scan line SL[N], a first connection end connected to the second data line DL 2 , and a second connection end connected to the gate of the second transistor T 2 . The third transistor T 3 applies a grayscale voltage DATA_grey to the gate of the second transistor T 2 in response to the scan signal SCAN[N].

The second capacitor Cswp includes a first electrode connected to the voltage line VL and a second electrode connected to the gate of the second transistor T 2 . The second capacitor Cswp may store the grayscale voltage DATA_grey transmitted by the third transistor T 3 in response to the scan signal SCAN[N] during a data writing period, and a voltage of the second node B may increase monotonically, such as but not limited to substantially linearly, by the sweep voltage Sweep that changes substantially linearly in an emission period. When the voltage of the second node B rising substantially linearly is higher than a threshold voltage of the second transistor T 2 , the second transistor T 2 may be turned on, and as the second control voltage CV 2 is applied to the gate of the first transistor T 1 , the first transistor T 1 may be turned off.

When the grayscale voltage DATA_grey is low, a time point at which the voltage of the second node B is higher than the threshold voltage of the second transistor T 2 is delayed, and the first transistor T 1 is turned off late, and thus, an emission duration for which the light-emitting element mLED emits light is extended. Conversely, when the grayscale voltage DATA_grey is high, the voltage of the second node B is quickly higher than the threshold voltage of the second transistor T 2 , and the first transistor T 1 is quickly turned off, and thus, the emission duration for which the light-emitting element mLED emits light is shortened. The emission duration for which the light-emitting element mLED emits light is controlled using this method, such that the grayscale may be accurately expressed.

It is preferable that all of threshold voltages of the second transistors T 2 of the pixels PX are uniform, but there may be a variation in the threshold voltages of the second transistors T 2 due to process errors, deterioration or the like. According to the present embodiment, the grayscale voltage DATA_grey is a voltage corresponding to correction data DATA3 generated by correcting image data DATA1 based on characteristics such as a threshold voltage and/or mobility of the second transistor T 2 sensed by the data sensing driving unit 130 of FIG. 1 . That is, because the grayscale voltage DATA_grey is a voltage that compensates for a variation in characteristics of each second transistor T 2 , even if the characteristics of each second transistor T 2 are irregular or change over time, the second transistor may be accurately turned off at an intended time by using the sweep voltage Sweep. Therefore, the grayscale may be accurately expressed.

An operation of the pixel PX will now be described with reference to FIG. 4 .

FIG. 4 illustrates signal timing during a frame time period for driving the pixel PX of FIG. 3 in a display mode.

Referring to FIG. 4 , the pixel PX may receive new data every frame time period in a display mode in which an image is displayed and may express grayscale corresponding to the received data. One frame time period 1 FRAME may include a data addressing and writing period TP 1 and a sweep and emission period TP 2 .

The data addressing and writing period TP 1 is a period during which the pixel PX stores a bias voltage DATA_bias in a first capacitor Cst in response to a scan signal SCAN[N] and stores a grayscale voltage DATA_grey in a second capacitor Cswp. The sweep and emission period TP 2 is a period during which the light-emitting element mLED emits light by the driving current Id.

The data addressing and writing period TP 1 may be divided into first to fifth periods DP 1 , DP 2 , DP 3 , DP 4 , and DP 5 , and the sweep and emission period TP 2 may be divided into sixth and seventh periods DP 6 and DP 7 . It may be understood that the first period DP 1 is a standby period, the second period DP 2 is a pre-charge period, the third period DP 3 is a data input period, the fourth period DP 4 is a data retention period, and the fifth period DP 5 is an emission preparation period. In addition, it may be understood that the sixth period DP 6 is a sweep or emission on period, and the seventh period DP 7 is a sweep or emission off period.

In the first period DP 1 , the first driving voltage PVDD may transition to a low level. The first driving voltage PVDD may drop to the same level as the second driving voltage PVSS. In this case, the first driving voltage PVDD may be, for example, −3 V. A voltage level of the source of the first transistor T 1 is also substantially lowered to a low level. The first driving voltage PVDD may continue to be at a low level (e.g., −3 V) during the data addressing and writing period TP 1 .

The second driving voltage PVSS may be at a low level (e.g., −3 V) during one frame time period 1 FRAME. The first control voltage CV 1 may also be at a low level (e.g., −3 V) during the one frame time period 1 FRAME.

The second control voltage CV 2 may be at a high level (e.g., 2 V) in the first period DP 1 , and the sweep voltage Sweep may be at a high level (e.g., 6 V) in the first period DP 1 . The scan signal SCAN[N] may be at a low level, and the third to fifth transistors T 3 to T 5 may be turned off.

In the second period DP 2 , the first driving voltage PVDD, the second driving voltage PVSS, and the first control voltage CV 1 may be at a low level (e.g., −3 V), the second control voltage CV 2 may be at a high level (e.g., 2 V), and the sweep voltage Sweep may be at a high level (e.g., 6 V).

The scan signal SCAN[N] may transition to a high level in the second period DP 2 , and thus, the third to fifth transistors T 3 to T 5 may be turned on. In this case, a bias voltage DATA_bias and a grayscale voltage DATA_grey to be written to a pixel PX in a previous row are applied to the first data line DL 1 and the second data line DL 2 . The bias voltage DATA_bias and the grayscale voltage DATA_grey to be written to the pixel PX in the previous row are applied to the first node A and the second node B via the fourth transistor T 4 and the third transistor T 3 , respectively. In this case, as shown in FIG. 4 , a voltage of the first node A may increase to a high level and a voltage of the second node B may decrease to an intermediate level.

The bias voltage DATA_bias is about (4+a) V, where a may be a value determined according to the characteristics of the first transistor T 1 . The grayscale voltage DATA_grey may be a value set according to grayscale data between about −7 V and about 0 V. As a grayscale value of the grayscale data is lower, the grayscale voltage DATA_grey may be at a higher voltage level, and as the grayscale value of the grayscale data is higher, the grayscale voltage DATA_grey may be at a lower voltage level.

In the second period DP 2 , the first capacitor Cst and the second capacitor Cswp are pre-charged with the bias voltage DATA_bias and the grayscale voltage DATA_grey to be written to the pixel PX in the previous row, such that a length of time in the third period DP 3 may be reduced.

A bias voltage DATA_bias (e.g., (4+a) V) to be written to the pixel PX in the previous row is applied to the gate of the first transistor T 1 , and the first control voltage CV 1 having a low level (e.g., −3 V) is applied to the source of the first transistor T 1 , and thus, the first transistor T 1 is turned on. However, because both the first driving voltage PVDD and the second driving voltage PVSS are at a low level, the light-emitting element mLED does not emit light.

The second control voltage CV 2 having a high level (e.g., 2 V) is applied to the source of the second transistor T 2 and a bias voltage DATA_bias (e.g., (4+a) V) to be written to the pixel PX in the previous row is applied to the drain of the second transistor T 2 , but a grayscale voltage DATA_grey (e.g., about −7 V to about 0 V) to be written to the pixel PX in the previous row is applied to the gate of the second transistor T 2 . Accordingly, the second transistor T 2 is not turned on.

In the third period DP 3 , the first driving voltage PVDD, the second driving voltage PVSS, and the first control voltage CV 1 may be at a low level (e.g., −3 V), the second control voltage CV 2 may be at a high level (e.g., 2 V), and the sweep voltage Sweep may be at a high level (e.g., 6 V). The scan signal SCAN[N] is at a high level, and the third to fifth transistors T 3 to T 5 are turned on.

A bias voltage DATA_bias and a grayscale voltage DATA_grey to be written to a current pixel PX are received via the first data line DL 1 and the second data line DL 2 . The bias voltage DATA_bias and the grayscale voltage DATA_grey are applied to the first node A and the second node B, that is, the first capacitor Cst and the second capacitor Cswp, respectively.

A bias voltage DATA_bias (e.g., (4+a) V) is applied to the gate of the first transistor T 1 , and the first control voltage CV 1 having a low level (e.g., −3 V) is applied to the source of the first transistor T 1 , and thus, the first transistor T 1 is turned on. However, because both the first driving voltage PVDD and the second driving voltage PVSS are at a low level, the light-emitting element mLED does not emit light.

The second control voltage CV 2 having a high level (e.g., 2 V) is applied to the source of the second transistor T 2 , a bias voltage DATA_bias (e.g., (4+a) V) is applied to the drain of the second transistor T 2 , but a grayscale voltage DATA_grey (e.g., about −7 V to about 0 V) is applied to the gate of the second transistor T 2 . Accordingly, the second transistor T 2 is not turned on.

In the fourth period DP 4 , the first driving voltage PVDD, the second driving voltage PVSS, and the first control voltage CV 1 may be at a low level (e.g., −3 V), the second control voltage CV 2 may be at a high level (e.g., 2 V), and the sweep voltage Sweep may be at a high level (e.g., 6 V). The scan signal SCAN[N] is at a high level, and the third to fifth transistors T 3 to T 5 are turned on.

The scan signal SCAN[N] may transition to a low level, and the third to fifth transistors T 3 to T 5 are turned off.

A difference between the bias voltage DATA_bias and the first control voltage CV 1 having a low level is stored in the first capacitor Cst, and a difference between the grayscale voltage DATA_grey and the sweep voltage Sweep having a high level is stored in the second capacitor Cswp.

In the fifth period DP 5 , the first driving voltage PVDD, the second driving voltage PVSS, and the first control voltage CV 1 are at a low level (e.g., −3 V).

The second control voltage CV 2 and the sweep voltage Sweep may transition to a low level. As shown in FIG. 4 , after the sweep voltage Sweep first transitions to a low level, the second control voltage CV 2 may transition to a low level.

As the sweep voltage Sweep transitions from a high level (e.g., 6 V) to a low level (e.g., 0 V), a voltage of the second node B is also lowered by 6 V. For example, the voltage of the second node B may be between about −13 V to about −6 V. Even if the second control voltage CV 2 transitions to a low level (e.g., −6 V), a voltage of the gate of the second transistor T 2 , that is, the second node B is not higher than the second control voltage CV 2 , and thus, the second transistor T 2 is turned off.

According to the present embodiment, when a grayscale value of grayscale data input to the pixel PX is 0, a grayscale voltage DATA_grey of 0V+Vth 2 , where Vth 2 is a threshold voltage, may be input to the second data line DL 2 in the third period DP 3 . Here, Vth 2 is a threshold voltage of the second transistor T 2 , and the timing control unit 140 of FIG. 1 may store threshold voltage information of the second transistor T 2 . A difference between the sweep voltage Sweep having a high level (e.g., 6 V) and the grayscale voltage DATA_grey of 0V+Vth 2 is stored across the ends of the second capacitor Cswp. In the fifth period DP 5 , when the sweep voltage Sweep transitions from a high level (e.g., 6 V) to a low level (e.g., 0 V), the voltage of the second node B becomes −6V+Vth 2 , and when the second control voltage CV 2 transitions to a low level (e.g., 6 V), a voltage of the source of the second transistor T 2 becomes −6 V. Because a voltage corresponding to the threshold voltage (Vth 2 ) of the second transistor T 2 is applied between the gate and the source of the second transistor T 2 , the second transistor T 2 is turned on and applies the second control voltage CV 2 having a low level (e.g., −6 V) to the gate of the first transistor T 1 . The first transistor T 1 is turned off by the second control voltage CV 2 having a low level (e.g., −6 V), and thereafter, the light-emitting element mLED does not emit light in the sixth period DP 6 . Because the grayscale value of the grayscale data input to the pixel PX is 0, the light-emitting element mLED should not emit light.

In the sixth period DP 6 , the first driving voltage PVDD transitions to a high level (e.g., 5 V). As a voltage difference (e.g., 8 V) is generated between the first power line PL 1 and the second power line PL 2 , a current path is formed, the first transistor T 1 outputs a driving current Id corresponding to a voltage stored in the first capacitor Cst, and the light-emitting element mLED emits light at a brightness corresponding to the driving current Id. Because the bias voltage DATA_bias stored in the first capacitor Cst is a voltage that compensates for the characteristics of the first transistor T 1 , the driving current Id may have a preset magnitude.

The sweep voltage Sweep increases substantially linearly at a low level (e.g., 0 V). Accordingly, the voltage of the second node B, that is, the gate of the second transistor T 2 , also increases substantially linearly. A difference between the voltage of the second node B and the second control voltage CV 2 having a low level (e.g., −6 V), that is, a voltage between the gate and the source of the second transistor T 2 , gradually increases. When the voltage between the gate and the source of the second transistor T 2 becomes higher than the threshold voltage of the second transistor T 2 , the sixth period DP 6 ends, and the seventh period DP 7 begins.

In the seventh period DP 7 , as the voltage between the gate and the source of the second transistor T 2 is higher than the threshold voltage of the second transistor T 2 , the second transistor T 2 is turned on. The second transistor T 2 being turned on applies the second control voltage CV 2 having a low level (e.g., −6 V) to the gate of the first transistor T 1 , and the first transistor T 1 is turned off.

A timing at which the second transistor T 2 is turned on is determined according to the grayscale voltage DATA_grey and the threshold voltage of the second transistor T 2 . Because the grayscale voltage DATA_grey is a voltage that compensates for the characteristics (e.g., the threshold voltage) of the second transistor T 2 , the timing at which the second transistor T 2 is turned on may be accurately controlled, and the grayscale value of the grayscale data input to the pixel PX may be accurately expressed.

Referring back to FIG. 1 , the voltage generating unit 150 may apply a first driving voltage PVDD having a low level (e.g., −3 V) to the first power line PL 1 in the data addressing and writing period TP 1 and may apply a first driving voltage PVDD having a high level (e.g., 5V) to the first power line PL 1 in the sweep and emission period TP 2 .

The gate sweep driving unit 120 may sequentially output scan signals SCAN[N] in the data addressing and writing period TP 1 . The gate sweep driving unit 120 may output the scan signal SCAN[N] to the scan line SL[N] connected to the pixel PX in the second and third periods DP 2 and DP 3 . The gate sweep driving unit 120 may output a sweep voltage Sweep that increases substantially linearly to the voltage line VL in the sweep and emission period TP 2 .

The data sensing driving unit 130 may output a second control voltage CV 2 having a high level (e.g., 2 V) to the second sensing line SSL 2 in the data addressing and writing period TP 1 and may output a second control voltage CV 2 having a low level (e.g., −6 V) to the second sensing line SSL 2 in the sweep and emission period TP 2 .

FIG. 5 illustrates a circuit for a pixel PX′ and a data sensing circuit 230 connected to the pixel PX′, according to an embodiment.

Referring to FIG. 5 , the pixel PX′ is similar to the pixel PX shown in FIG. 3 , so duplicate description may be omitted.

The data sensing circuit 230 may be included in the data sensing driving unit 130 and is connected to the pixel PX′. The data sensing circuit 230 is connected to the pixel PX′ via the first sensing line SSL 1 and the second sensing line SSL 2 . The data sensing circuit 230 is connected to the pixel PX′ via the first data line DL 1 and the second data line DL 2 .

The data sensing circuit 230 includes a sensing circuit 233 , first and second control voltage output units 234 and 235 , and a switch circuit including at least some of a plurality of switches S 1 , S 2 , S 3 , S 4 , S 5 , and S 6 .

The sensing circuit 233 generates first sensing data SD 1 (see FIG. 1 ) by sensing a magnitude of a first current I 1 output by the first transistor T 1 when a reference bias voltage DATA_bias and a reference source voltage Vpre are applied to the first driving circuit 10 , and generates second sensing data SD 2 (see FIG. 1 ) by sensing a magnitude of a second current I 2 output by the second transistor T 2 when the grayscale voltage DATA_grey and a reference source voltage Vpre are applied to the second driving circuit 20 .

The reference bias voltage DATA_bias refers to a voltage input to the first data line DL 1 during a first sensing period for sensing the characteristics of the first transistor T 1 , and the reference grayscale voltage DATA_grey refers to a voltage input to the second data line DL 2 during a second sensing period for sensing the characteristics of the second transistor T 2 . The reference source voltage Vpre refers to a voltage applied to the first or second sensing line SSL 1 or SSL 2 by the sensing circuit 233 . The reference source voltage Vpre may be generated by the data sensing driving unit 130 .

The sensing circuit 233 includes an integration circuit and an analog-to-digital conversion circuit 232 . The integration circuit includes an operational amplifier 231 and a third capacitor Cfb. The sensing circuit 233 is connected to the first sensing line SSL 1 via the third switch S 3 and is connected to the second sensing line SSL 2 via the fourth switch S 4 . In the first sensing period, the third switch S 3 is closed and the fourth switch S 4 is opened. In the second sensing period, the third switch S 3 is opened and the fourth switch S 4 is closed.

The operational amplifier 231 includes a first input end connected to the third switch S 3 and the fourth switch S 4 , a second input end to which a reference source voltage Vpre is applied, and an output end connected to the analog-to-digital conversion circuit 232 . The third capacitor Cfb is connected between the first input end and the output end of the operational amplifier 231 . The first switch S 1 may be connected to the third capacitor Cfb in parallel.

When the first switch S 1 is closed, all of charges stored in the third capacitor Cfb are discharged. When the first switch S 1 is opened, a current flowing toward the first input end of the operational amplifier 231 is accumulated in the third capacitor Cfb, and a voltage between both electrodes of the third capacitor Cfb increases in proportion to the accumulated current. A voltage at the output end of the operational amplifier 231 is lowered by the voltage between both electrodes of the third capacitor Cfb. The analog-to-digital conversion circuit 232 may generate sensing data by sensing a voltage Vout of an output node OUT connected to the output end of the operational amplifier 231 .

The second switch S 2 may be arranged between the output end of the operational amplifier 231 and the output node OUT. The voltage at the output end of the operational amplifier 231 may be sampled in the output node OUT when the second switch S 2 is opened, and the analog-to-digital conversion circuit 232 may sense the voltage Vout sampled in the output node OUT.

The first control voltage output unit 234 is connected to the first sensing line SSL 1 via the fifth switch S 5 . The second control voltage output unit 235 is connected to the second sensing line SSL 2 via the sixth switch S 6 . The fifth switch S 5 and the sixth switch S 6 may each be closed in a display mode and opened in a sensing mode according to the second control signal CONT 2 (see FIG. 1 ).

The data sensing circuit 230 may further include a bias voltage output unit that outputs a bias voltage DATA_bias to the first data line DL 1 , and a grayscale voltage output unit that outputs a grayscale voltage DATA_grey to the second data line DL 2 .

FIG. 6 illustrates timing for driving the pixel PX′ and the data sensing circuit 230 of FIG. 4 in a sensing mode.

Referring to FIG. 6 , the data sensing circuit 230 may sense the characteristics of the first transistor T 1 of the pixel PX′ in a first sensing period STP 1 , and the characteristics of the second transistor T 2 of the pixel PX′ in a second sensing period STP 2 . The characteristics of the first transistor T 1 may be threshold voltage characteristics and/or mobility characteristics, and the characteristics of the second transistor T 2 may be threshold voltage characteristics.

The first sensing period STP 1 may be divided into first to fourth periods SP 1 , SP 2 , SP 3 , and SP 4 , and the second sensing period STP 2 may be divided into fifth to eighth periods SP 5 , SP 6 , SP 7 , and SP 8 . The first period SP 1 is a standby period, the second period SP 2 is a T 1 biasing period, the third period SP 3 is a first current accumulation period, and the fourth period SP 4 is a first sensing period. The fifth period SP 5 is a standby period, the sixth period SP 6 is a T 2 biasing period, the seventh period SP 7 is a second current measurement period, and the eighth period SP 8 is a second sensing period.

The first driving voltage PVDD may be at a high level in the first sensing period STP 1 and may be at a low level in the second sensing period STP 2 . The second driving voltage PVSS may be at a low level in the first sensing period STP 1 and the second sensing period STP 2 .

A scan signal SCAN[N] is applied to the pixel PX′ in the second and third periods SP 2 and SP 3 of the first sensing period STP 1 , such that the third to fifth transistors T 3 to T 5 may be turned on. A scan signal SCAN[N] is applied to the pixel PX′ in the sixth and seventh periods SP 6 and SP 7 of the second sensing period STP 2 , such that the third to fifth transistors T 3 to T 5 may be turned on.

In the first period SP 1 , the first to third switches S 1 to S 3 are closed, and the fourth switch S 4 is opened. A reference source voltage Vpre input to the second input end of the operational amplifier 231 is transmitted to the output end of the operational amplifier 231 using the first switch S 1 , and an output voltage Vout of the output node OUT becomes equal to the reference source voltage Vpre using the second switch S 2 .

The third to fifth transistors T 3 to T 5 are turned on by the scan signal SCAN[N] in the second period SP 2 and the third period SP 3 . A reference bias voltage DATA_bias having a high level is applied to the first data line DL 1 in synchronization with the scan signal SCAN[N]. The reference bias voltage DATA_bias is applied to the gate of the first transistor T 1 via the fourth transistor T 4 .

The reference source voltage Vpre is applied to the source of the first transistor T 1 via the fifth transistor T 5 . The first capacitor Cst stores a difference between the reference bias voltage DATA_bias and the reference source voltage Vpre. A difference between the reference source voltage Vpre and the second driving voltage PVSS having a low level may be set smaller than a threshold voltage of the light-emitting element mLED. Because the light-emitting element mLED is not conductible, the first current I 1 output from the first transistor T 1 does not flow to the light-emitting element mLED.

A grayscale voltage DATA_grey having a low level is applied in synchronization with the scan signal SCAN[N], such that the second transistor T 2 may be turned off during the second to fourth periods SP 2 to SP 4 . As another example, because the sweep voltage Sweep is maintained at a low level, the second transistor T 2 may be turned off.

The first transistor T 1 outputs the first current I 1 having a magnitude determined based on the difference between the reference bias voltage DATA_bias and the reference source voltage Vpre. The first current I 1 flows through the fifth transistor T 5 and the third switch S 3 toward the first input end of the operational amplifier 231 .

The first switch S 1 is closed in the second period SP 2 , and is opened in the third period SP 3 . In the second period SP 2 , the first current I 1 flows through the first switch S 1 to the output end of the operational amplifier 231 . When the first switch S 1 is opened in the third period SP 3 , the first current I 1 is accumulated in the third capacitor Cfb. As the first current I 1 is accumulated in the third capacitor Cfb, a voltage between both electrodes of the third capacitor Cfb gradually increases.

When the reference source voltage Vpre is biased to a first electrode of a third capacitor Cfb connected to the first input end of the operational amplifier 231 , a voltage at the output end of the operational amplifier 231 , to which a second electrode of the third capacitor Cfb is connected, is lowered from the reference source voltage Vpre by the voltage between both electrodes of the third capacitor Cfb. As shown in FIG. 3 , the voltage Vout of the output node OUT is lowered over time in the third period SP 3 .

When the third period SP 3 ends, the second switch S 2 is opened, and the voltage Vout of the output node OUT is no longer lowered. In the fourth period SP 4 , an analog-to-digital conversion circuit ADC may generate first sensing data SD 1 by sensing the voltage Vout of the output node OUT.

The first sensing data SD 1 is related to a threshold voltage and/or mobility of the first transistor T 1 . The data sensing driving unit 130 (see FIG. 1 ) may generate the first sensing data SD 1 while changing the reference bias voltage DATA_bias under the control of the timing control unit 140 (see FIG. 1 ). The timing control unit 140 may calculate the characteristics of the first transistor T 1 based on a magnitude of the reference bias voltage DATA_bias and a value of the first sensing data SD 1 and store the characteristics in the memory 146 (see FIG. 2 ).

In the fifth period SP 5 , the first to third switches S 1 to S 3 are closed, and the fourth switch S 4 is opened. A reference source voltage Vpre input to the second input end of the operational amplifier 231 is transmitted to the output end of the operational amplifier 231 using the first switch S 1 , and an output voltage Vout of the output node OUT becomes equal to the reference source voltage Vpre using the second switch S 2 .

The third to fifth transistors T 3 to T 5 are turned on by the scan signal SCAN[N] in the sixth period SP 6 and the seventh period SP 7 . In synchronization with the scan signal SCAN[N], a reference grayscale voltage DATA_grey having a high level is applied to the second data line DL 2 , and a bias voltage DATA_bias having a high level is applied to the first data line DL 1 .

The bias voltage DATA_bias having a high level is applied to the drain of the second transistor T 2 via the fourth transistor T 4 , and the reference grayscale voltage DATA_grey having a high level is applied to the gate of the second transistor T 2 via the third transistor T 3 . The reference source voltage Vpre is applied to the source of the second transistor T 2 via the fourth switch S 4 .

The second transistor T 2 outputs the second current I 2 having a magnitude determined based on a difference between the reference grayscale voltage DATA_grey applied to the gate of the second transistor T 2 and the reference source voltage Vpre applied to the source of the second transistor T 2 . The second current I 2 flows through the fourth switch S 4 toward the first input end of the operational amplifier 231 .

The first switch S 1 is closed in the sixth period SP 6 , and is opened in the seventh period SP 7 . In the sixth period SP 6 , the second current I 2 flows through the first switch S 1 to the output end of the operational amplifier 231 . When the first switch S 1 is opened in the seventh period SP 7 , the second current I 2 is accumulated in the third capacitor Cfb. As the second current I 2 is accumulated in the third capacitor Cfb, the voltage between both electrodes of the third capacitor Cfb gradually increases.

When the reference source voltage Vpre is biased to the first electrode of the third capacitor Cfb connected to the first input end of the operational amplifier 231 , a voltage at the output end of the operational amplifier 231 , to which the second electrode of the third capacitor Cfb is connected, is lowered from the reference source voltage Vpre by the voltage between both electrodes of the third capacitor Cfb. As shown in FIG. 3 , the voltage Vout of the output node OUT is lowered over time in the seventh period SP 7 .

When the seventh period SP 7 ends, the second switch S 2 is opened, and the voltage Vout of the output node OUT is no longer lowered. In the eighth period SP 8 , an analog-to-digital conversion circuit ADC may generate second sensing data SD 2 by sensing the voltage Vout of the output node OUT.

The second sensing data SD 2 is related to a threshold voltage and/or mobility of the second transistor T 2 . The data sensing driving unit 130 (see FIG. 1 ) may generate the second sensing data SD 2 while changing the reference grayscale voltage DATA_grey under the control of the timing control unit 140 (see FIG. 1 ). The timing control unit 140 may calculate the characteristics of the second transistor T 2 based on a magnitude of the reference grayscale voltage DATA_grey and a value of the second sensing data SD 2 and store the characteristics in the memory 146 (see FIG. 2 ).

According to one or more embodiments, a pixel circuit operating in a time division driving method to drive a light-emitting element such as a micro-LED may be provided. Characteristics of transistors in the pixel circuit may be sensed by a sensing circuit. When a driving circuit outputs a bias voltage and a grayscale voltage that compensate for variations in characteristics of the transistors, a magnitude and a pulse width of a driving current output to the light-emitting element by the pixel circuit are accurately controlled, and thus, the light-emitting element may emit light with accurate brightness and color. Therefore, the display quality of a display panel may be improved.

In addition, when the pixel circuit has a relatively simple structure, high-density pixels may be manufactured, and high yield may be obtained even when manufacturing large-area panels.

It shall be understood that embodiments described herein should be considered in a descriptive sense only and not for purposes of limitation. Descriptions of features or aspects within each embodiment should typically be considered as available for other similar features or aspects in other embodiments. While one or more embodiments have been described with reference to the figures, it will be understood by those of ordinary skill in the pertinent art that various changes in form and details may be made therein without departing from the spirit and scope of the present disclosure as defined by the following claims.