Power controller and control method for LLC resonant converter

This application claims priority to and the benefit of Taiwan Application Series Number 109110852 filed on Mar. 30, 2020, which is incorporated by reference in its entirety.

The present disclosure relates generally to LLC resonant converters, and more particularly to burst-mode operation controls in LLC resonant converters that increase power conversion efficiency for light or no loads.

LLC resonant converters are very superior in conversion efficiency among switching mode power converters. As known in the art, conduction losses of power switches, the power losses when power switches conduct current, are some major causes of the power losses in a switching mode power converter. Theoretically, an LLC resonant converter can operate its two main power switches, high-side and low-side switches, to perform zero voltage switching (ZVS), a technology that a power switch is turned ON around the moment when the voltage drop across the conduction channel of the power switch is about zero. The conduction losses caused by the conductions of high-side and low-side switches could be therefore minimized. LLC resonant converters are mostly used for high power applications, for example, converting power more than 100 W.

An LLC resonant converter suffers, however, in significant switching losses when it provides power to a light load or no load. As known in the art, the switching frequency of an LLC resonant converter increases when its load decreases. Even though the conduction losses of an LLC resonant converter could be suppressed or minimized by ZVS, switching losses, the power losses needed to charge or discharge control nodes of power switches, inevitably increase along with the increment of switching frequency. The significant increment in the switching frequency of an LLC resonant converter could cause significant switching losses that seriously degrade the power conversion rate of the LLC resonant converter. Accordingly, it is often needed to provide specially operations when the load of an LLC resonant converter is light or non-existent.

Non-limiting and non-exhaustive embodiments of the present invention are described with reference to the following drawings. In the drawings, like reference numerals refer to like parts throughout the various figures unless otherwise specified. These drawings are not necessarily drawn to scale. Likewise, the relative sizes of elements illustrated by the drawings may differ from the relative sizes depicted.

The invention can be more fully understood by the subsequent detailed description and examples with references made to the accompanying drawings, wherein:

FIG. 1 demonstrates LLC resonant converter 100 according to embodiments of the invention;

FIG. 2 illustrates power controller 102 in FIG. 1 ;

FIG. 3 demonstrates the waveforms of triangular-wave signal V TRI , feedback voltage V FB minus 0.2V, stop signal GATE-STOP, signal S H controlling high-side switch HS, and signal S L controlling low-side switch LS, when feedback voltage V FB is below burst voltage V BST ;

FIG. 4A demonstrates the relationship between feedback voltage V FB and high-side ON time T H-ON and/or low-side ON time T L-ON ; and

FIG. 4B the relationship between feedback voltage V FB and work duty DWK.

According to embodiments of the invention, an LLC resonant converter operates in a burst mode when its load is light or non-existent. When operating in a burst mode, break time BRK, when high-side and low-side switches constantly turn OFF, alternates with work time WK, when high-side and low-side switches switch periodically and complementarily. The combination of a period of bread time BRK and a period of work time WK forms a predetermined burst cycle time TBST, which according to one embodiment of the invention is a constant independent from the load of an LLC resonant converter.

FIG. 1 demonstrates LLC resonant converter 100 according to embodiments of the invention, converting input voltage V IN in a primary side into output voltage V OUT in a secondary side. Shown in FIG. 1 , LLC resonant converter 100 includes power controller 102 , high-side switch HS, low-side switch LS, transformer TF, capacitors CIN, CVCC, CL, and COUT, diodes D 1 , D 2 H, and D 2 L, error amplifier ER, and photo coupler OPT. Inside transformer TF, there are primary winding LP, auxiliary winding LA, secondary windings LSH and LSL, inductively coupled to each other. FIG. 1 also shows that transformer TF includes parasitic inductor LPP, representing the leakage inductance and connected in series with primary winding LP and capacitor CL between connection node N 1 and input ground. Parasitic inductor LPP, primary winding LP and capacitor CL form an LLC resonant tank that is driven to resonate and transfer power from the primary side to the secondary side.

Power controller 102 according to embodiments of the invention is a packaged integrated circuit having, but not limited to have, power source pin VCC, feedback pin FB, setting pin BSTS, high-side drive pin HGATE, high-side ground pin HGND, low-side drive pin LGATE, and ground pin GND. Via high-side drive pin HGATE and low-side drive pin LGATE, power controller 102 controls high-side ON time T H-ON of high-side switch HS and low-side ON time T L-ON of low-side switch LS respectively, so as to energize or deenergize the LLC resonant tank. When current and voltage resonate within the LLC resonant tank, diodes D 2 H and D 2 L rectify the induced current through secondary windings LSH and LSL to build up output voltage V OUT powering load 104 . In the meantime, diode D 1 rectifies induced current through auxiliary winding LA to build up operating power voltage V CC , which substantially supplies power that power controller 102 needs.

Regulation of output voltage V OUT is controlled by the combination of error amplifier ER and photo coupler OPT, sending feedback through feedback pin FB to power controller 102 . Feedback voltage V FB at feedback pin FB is generated in response to the comparison between output voltage V OUT and predetermined target voltage V TRGT . The purpose of regulation is to stabilize output voltage V OUT at about target voltage V TRGT . For instance, when output voltage V OUT exceeds target voltage V TRGT , photo coupler OPT pulls down feedback voltage V FB at feedback pin FB, high-side ON time T H-ON and low-side ON time T L-ON in the next switching cycle shortens, the power feeding into the LLC resonant tank in the next switching cycle reduces, and the power transferred to the secondary side decreases as a result, so output voltage V OUT tends to go down to approach target voltage V TRGT . From another point of view, if output voltage V OUT is about the same as target voltage V TRGT , the lighter load 104 the lower feedback voltage V FB .

Setting pin BSTS of power controller 102 is electrically connected to an external resistor RST, whose resistance for example is detected by power controller 102 to determine burst voltage V BST . Burst voltage V BST , according to embodiments of the invention, could determine high-side ON time T H-ON and low-side ON time T L-ON when load 104 is light or non-existent.

FIG. 2 illustrates power controller 102 , including ON-time generator 110 , burst-mode controller 112 , burst-voltage setting circuit 113 , comparator 114 , logic 116 , and gate drivers 118 and 120 .

Burst-voltage setting circuit 113 electrically connects to setting pin BSTS, and detects the resistance of external resistor RST to generate burst voltage V BST . For example, burst-voltage setting circuit 113 has constant current source IS supplying a constant current flowing through external resistor RST, and burst voltage V BST is, but is not limited to be, the voltage at setting pin BSTS plus 0.2V, which is the minimum value of feedback voltage V FB . In one embodiment of the invention, photo coupler OPT can pull down feedback voltage V FB as low as 0.2V at most.

Comparator 114 compares feedback voltage V FB with burst voltage V BST . According to embodiments of the invention, when feedback voltage V FB is below burst voltage V BST , comparator 114 outputs low-load signal S LOW with logic “1”; in the opposite, when feedback voltage V FB exceeds burst voltage V BST , comparator 114 outputs low-load signal S LOW with logic “0”. The configuration of comparator 114 and multiplexer 122 is to make multiplexer 122 output the bigger one between feedback voltage V FB and burst voltage V BST . Simply speaking, when feedback voltage V FB is below burst voltage V BST , multiplexer 122 outputs burst voltage V BST , and power controller 102 operates LLC resonant converter 100 in a burst mode, where break time BRK and alternates with work time WK. When feedback voltage V FB exceeds burst voltage V BST , multiplexer 122 outputs feedback voltage V FB , and power controller 102 operates LLC resonant converter 100 in a non-burst mode, where only work time WK exists and break time BRK disappears.

When operating in a non-burst mode, ON-time generator 110 determines high-side ON time T H-ON of high-side switch HS and low-side ON time T L-ON of low-side switch LS in light of feedback voltage V FB . ON-time generator 110 includes multiplexer 122 , comparators 124 and 126 , and ramp generator 128 . Multiplexer 122 , in response to the output of comparator 114 , forwards feedback voltage V FB to comparators 124 and 126 when operating in a non-burst mode. In the other hand, when operating in a burst mode, multiplexer 122 forwards burst voltage V BST to comparators 124 and 126 . For example, ramp generator 128 starts increasing ramp signal V RAMP-H at the same time when high-side switch HS is just turned ON. At the moment when ramp signal V RAMP-H exceeds the signal at the inverted input of comparator 124 , which is either feedback voltage V FB or burst voltage V BST , depending on the comparison between them, output NH of comparator 124 provides a rising edge, which resets SR flipflop 130 to turn OFF, via gate driver 118 , high-side switch HS, so high-side ON time T H-ON is ended. Accordingly, ON-time generator 110 controls the length of high-side ON time T H-ON based on feedback voltage V FB or burst voltage V BST . Analogously, ON-time generator 110 controls the length of low-side ON time T L-ON based on feedback voltage V FB or burst voltage V BST .

Logic 116 is configured to prevent short through from happening, where short through refers to a short circuit connected between input voltage V IN and input ground when high-side switch HS and low-side switch LS are turned ON at the same time. When signal S H turns from “1” into “0” for example and gate driver 118 in response starts turning OFF high-side switch HS, the falling edge of signal S H makes pulse generator 136 generate a pulse to set SR flipflop 132 , turning signal S L from “0” into “1”, so gate driver 120 starts turning ON low-side switch LS. Accordingly, low-side switch LS is allowed to turn ON only when high-side switch HS turns OFF. Similarly, high-side switch HS is allowed to be turned ON only when low-side switch LS turns OFF. In other words, logic 116 is capable of making high-side and low-side switches HS and LS switch periodically and complementarily.

Burst-mode controller 112 has counter 140 , digital-to-analog converter 142 , comparator 144 , pulse generators 146 and 150 , AND gate 148 , and SR flipflop 152 . Based on clock CLK counter 140 provides count SD having the most significant bit MSB. The most significant bit MSB is the bit positioned in a binary number having the greatest value.

Clock CLK according to embodiments of the invention could be signal S L or signal S H , or any signal generated from an independent clock generator. For example, clock CLK could be provided by ramp generator 128 , which also generates ramp signals V RAMP-L and V RAMP-H periodically. In one embodiment of the invention, count SD changes and cycles from 0 to 31 every predetermined burst cycle time TBST, which is, but is not limited to be, 1/400 sec. Digital-to-analog converter 142 provides triangular-wave signal V TRI in response to count SD and burst voltage V BST , where triangular-wave signal V TRI could be a saw waveform periodically varying from 0V to burst voltage V BST minus 0.2V. The amplitude of triangular-wave signal V TRI is therefore in association with burst voltage V BST . For example, the value of triangular-wave signal V TRI could be, according to embodiments of the invention, expressed as SD*(V BST −0.2)/32. Comparator 144 compares triangular-wave signal V TRI with feedback voltage V FB minus 0.2V. Supposed that triangular-wave signal V TRI-M is equal to triangular-wave signal V TRI plus 0.2V, comparator 144 equivalently compares triangular-wave signal V TRI-M with feedback voltage V FB . At the time when feedback voltage V FB is below triangular-wave signal V TRI-M , comparator 144 sets, via AND gate 148 , SR flipflop 152 , making stop signal GATE-STOP “1” in logic and causing both high-side switch HS and low-side switch LS OFF. Shown in FIG. 2 , when feedback voltage V FB minus 0.2V is less than triangular-wave signal V TRI , both high-side switch HS and low-side switch LS are constantly OFF; when feedback voltage V FB minus 0.2V is more than triangular-wave signal V TRI , high-side and low-side switches HS and LS switch periodically and complementarily.

Pulse generator 146 , configured to be triggered by the falling edge of signal S L , provides a short pulse to AND gate 148 , to open a window during which stop signal GATE-STOP is allowed to turn from “0” to “1”. From an aspect of view, the comparison between triangular-wave signal V TRI and feedback voltage V FB minus 0.2V can be recorded by SR flipflop 152 only during the window after low-side switch LS is turned OFF. Further from another aspect of view, burst-mode controller 112 checks, only during that window after low-side switch LS is turned OFF, whether or not triangular-wave signal V TRI exceeds feedback voltage V FB minus 0.2V. Therefore, during the time when high-side switch HS or low-side switch LS is still ON, high-side switch HS or low-side switch LS will not be suddenly turned OFF by comparator 144 even if triangular-wave signal V TRI exceeds feedback voltage V FB minus 0.2V.

Pulse generator 150 , triggered by the falling edge of the most significant bit MSB, provides a short pulse to reset SR flipflop 152 , forcing stop signal GATE-STOP to be “0” in logic, so as to let high-side and low-side switches HS and LS switch periodically and complementarily. Therefore, no matter how much feedback voltage V FB is, the falling edge of the most significant bit MSB will cause high-side switch HS and low-side switch LS to turn ON at least once. It can be understood from the configuration of burst-mode controller 112 , since the falling edge of the most significant bit MSB appears at least once every predetermined burst cycle time TBST, high-side switch HS and low-side switch LS turn ON at least once every predetermined burst cycle time TBST. According to another embodiment of the invention, it is the rising edge of the most significant bit MSB that triggers pulse generator 150 to provide a short pulse resetting SR flipflop 152 .

FIG. 3 demonstrates the waveforms of triangular-wave signal V TRI , feedback voltage V FB minus 0.2V, stop signal GATE-STOP, signal S H controlling high-side switch HS, and signal S L controlling low-side switch LS, when feedback voltage V FB is below burst voltage V BST .

As shown in FIG. 3 , triangular-wave signal V TRI cycles once every predetermined burst cycle time TBST. Every time when the waveform of triangular-wave signal V TRI goes across that of feedback voltage V FB minus 0.2V, stop signal GATE-STOP changes its logic value into “0” or “1”. At moment t 0 , the most significant bi MSB has a falling edge, so high-side and low-side switches HS and LS start switching periodically and complementarily. Moment t 0 is also the beginning of a predetermined burst cycle time TBST, as shown in FIG. 3 .

Feedback voltage V FB minus 0.2V is higher than triangular-wave signal V TRI during the period from moment t 0 to moment t 1 , so stop signal GATE-STOP is “0”, and high-side and low-side switches HS and LS switch periodically and complementarily. Therefore, the period from moment t 0 to moment t 1 is referred to as work time WK, during which high-side and low-side switches HS and LS are controlled to energize the LLC resonant tank. Both high-side ON time T H-ON and low-side ON time T L-ON during work time WK in FIG. 3 are constant, independent from feedback voltage V FB , because multiplexer 122 in ON-time generator 110 is currently providing burst voltage V BST to comparators 124 and 126 .

During break time BRK, referring to the period of time from moment t 1 to moment t 2 , feedback voltage V FB minus 0.2V is below triangular-wave signal V TRI , so stop signal GATE-STOP is “1” in logic, and high-side and low-side switches HS and LS are constantly OFF. At moment t 2 , a predetermined burst cycle time TBST ends and a next predetermined burst cycle time TBST starts.

Work duty DWK refers to the ratio of work time WK to predetermined burst cycle time TBST. It is comprehensible from FIG. 3 that, if feedback voltage V FB increases, then both work time WK and work duty DWK increase but the predetermined burst cycle time TBST remains unchanged.

FIG. 4A demonstrates the relationship between feedback voltage V FB and high-side ON time T H-ON and/or low-side ON time T L-ON , and FIG. 4B the relationship between feedback voltage V FB and work duty DWK.

FIG. 4A shows that when feedback voltage V FB exceeds burst voltage V BST each of high-side ON time T H-ON and low-side ON time T L-ON is in positive linear correlation with feedback voltage V FB . Nevertheless, when feedback voltage V FB drops to be less than burst voltage V BST , each of high-side ON time T H-ON and low-side ON time T L-ON depends on feedback voltage V FB no more, and becomes a constant determined by burst voltage V BST .

FIG. 4B shows that if feedback voltage V FB exceeds burst voltage V BST work duty DWK is always 100%, meaning that high-side and low-side switches HS and LS switch periodically and complementarily all the time. Nevertheless, if feedback voltage V FB drops to be less than burst voltage V BST , work duty DWK becomes less than 100% because of the occurrence of break time BRK, and the less feedback voltage V FB the less work duty DWK.

According to embodiments of the invention, when the load is light or nonexistent, LLC resonant converter 100 is capable of being operated in a burst mode, in which break time BRK alternates with work time WK. The introduction of break time can reduce switching losses of high-side and low-side switches HS and LS, improving power conversion efficiency.

The predetermined burst cycle time TBST could be properly set to avoid uncomfortable audible noise that probably occurs when LLC resonant converter 100 is operated in a burst mode when the load is light.

A system engineer could select external resistor RST to determine the load threshold which determines the quantity of load 104 for LLC resonant converter 100 to operate in a burst mode. External resistor RST also can determine high-side ON time T H-ON and low-side ON time T L-ON , which are two constants when LLC resonant converter 100 operates in a burst mode.

According to embodiments of the invention, each of high-side switch HS and low-side switch LS is turned ON at least once every predetermined burst cycle time TBST, which is internally set by burst-mode controller 112 and consists of one break time BRK and one work time WK. Without making each of high-side switch HS and low-side switch LS turned ON at least once every predetermined burst cycle time TBST, break time BRK might last so long that the real predetermined burst cycle time TBST could be an integer multiple of the predetermined burst cycle time TBST internally set by burst-mode controller 112 . It might induce uncomfortable audible noise if the real predetermined burst cycle time TBST is too long.

While the invention has been described by way of example and in terms of preferred embodiment, it is to be understood that the invention is not limited thereto. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.