Differential sensing device with wide sensing margin

This non-provisional application claims priority of U.S. provisional application No. 62/988,403, filed on Mar. 12, 2020, included herein by reference in its entirety.

1. Field of the Invention

The present invention is related to a differential sensing device, and more particular, to a differential sensing device with wide sensing margin.

2. Description of the Prior Art

Resistive random-access memory (ReRAM) has been widely used due to the low power and high speed characteristics. Generally, the ReRAM cell may include a storage element, and the resistance of the storage element will be changed when a proper high voltage is applied. For example, the storage element may include a transition metal oxide (TMO), and the resistance of the transition metal oxide will decrease when a proper high voltage is applied. Therefore, the storage element can be programmed by applying high voltages, and the data stored in the ReRAM cell can be read according to the resistance of the storage element.

In prior art, an accurate reference current is usually required to read the data stored in the ReRAM cell. However, since the physical characteristics of different memory cells are different, it is quite difficult to define one accurate reference current for all different memory cells. Furthermore, the read margin would be rather small if an inappropriate reference current is used, and the small read margin can also slow down the read process, affecting the efficiency of the ReRAM.

One embodiment of the present invention discloses a differential sensing device. The differential sensing device includes a first reference cell, a second reference cell, a first path selector, a second path selector, a third path selector, and a fourth path selector.

The first reference cell provides a first reference current, and the second reference cell provides a second reference current. The first path selector is coupled to a first sensing node, the second reference cell, and a first memory cell. The second path selector is coupled to a second sensing node, the first reference cell, and the first memory cell. The third path selector is coupled to a third sensing node, the first reference cell, and a second memory cell. The fourth path selector is coupled to a fourth sensing node, the second reference cell, and the second memory cell.

The first sample circuit is coupled the first sensing node, and samples a first cell current generated by the first memory cell during a sample operation. The second sample circuit is coupled to the second sensing node, and samples the first reference current during the sample operation. The third sample circuit is coupled to the third sensing node, and samples a second cell current generated by the second memory cell during the sample operation. The fourth sample circuit is coupled to the fourth sensing node, and samples the second reference current during the sample operation. The first reference current is smaller than the second reference current.

During a race operation, a voltage of the first sensing node is settled according to a race between the first cell current and the second reference current, a voltage of the second sensing node is settled according to a race between the first reference current and the first cell current, a voltage of the third sensing node is settled according to a race between the second cell current and the first reference current, and a voltage of the fourth sensing node is settled according to a race between the second reference current and the second cell current.

These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.

FIG. 1 shows a differential sensing device according to one embodiment of the present invention.

FIG. 2 shows a differential sensing device according to another embodiment of the present invention.

FIG. 1 shows a differential sensing device 100 according to one embodiment of the present invention. The differential sensing device 100 includes reference cells 110 A and 110 B, path selectors 120 A, 120 B, 120 C, and 120 D, and sample circuits 130 A, 130 B, 130 C, and 130 D. In some embodiments, the differential sensing device 100 can be used to read the data stored in memory cells MC 1 and MC 2 .

The reference cell 110 A can provide a reference current IR 1 , and the reference cell 110 B can provide a reference current IR 2 . In some embodiments, the memory cells MC 1 and MC 2 can be resistive random-access memory (ReRAM) cells. For example, the memory cell MC 1 can include a resistive element RE 1 and a selection transistor ST 1 . The resistive element RE 1 has a first terminal coupled to a bit line BL 1 , and a second terminal. The selection transistor ST 1 has a first terminal coupled to the second terminal of the resistive element RE 1 , a second terminal coupled to a source line SL 1 , and a control terminal coupled to a word line WL 1 .

Similarly, the memory cell MC 2 can include a resistive element RE 2 and a selection transistor ST 2 . The resistive element RE 2 has a first terminal coupled to a bit line BL 2 , and a second terminal. The selection transistor ST 2 has a first terminal coupled to the second terminal of the resistive element RE 2 , a second terminal coupled to a source line SL 2 , and a control terminal coupled to a word line WL 2 .

In this case, the reference current IR 1 can be used to simulate a cell current generated by a resistive random-access memory cell having a high resistance while the reference current IR 2 can be used to simulate a cell current generated by a resistive random-access memory cell having a low resistance. For example, the reference cell 110 A may include at least one resistive element having a high resistance, and the reference cell 110 B may include at least one resistive element having a low resistance.

In FIG. 1 , the reference cell 110 A includes four resistive elements A 1 , A 2 , A 3 , and A 4 having high resistance. Also, the resistive elements A 1 and A 2 coupled in parallel can be coupled in series with the resistive elements A 3 and A 4 coupled in parallel. Therefore, the variation of resistance of the four resistive elements A 1 to A 4 can be averaged, and the overall resistance of the reference cell 110 A can be used as a more general reference for a high resistance memory cell. Similarly, the reference cell 110 B can include four resistive elements B 1 , B 2 , B 3 , and B 4 having low resistance for generating a more general simulation result for a low resistance memory cell. In this case, the reference current IR 1 provided by the reference cell 110 A would be smaller than the reference current IR 2 provided by the reference cell 110 B. In some embodiments, the reference cells 110 A and 110 B may include more resistive elements for providing even more general references according to the system requirement. However, in some other embodiments, the reference cell 110 A and 110 B can each include one resistive element for reducing the circuit area.

Also, in FIG. 1 , the path selector 120 A can be coupled to a sensing node LQ, the reference cell 110 B, and the memory cell MC 1 . The path selector 120 B can be coupled to a sensing node LQB, the reference cell 110 A, and the memory cell MC 1 . The path selector 120 C can be coupled to a sensing node RQB, the reference cell 110 A, and the memory cell MC 2 . The path selector 120 D can be coupled to a sensing node RQ, the reference cell 110 B, and the memory cell MC 2 .

Furthermore, in FIG. 1 , the sample circuit 130 A can be coupled the sensing node LQ, the sample circuit 130 B can be coupled to the sensing node LQB, the sample circuit 130 C can be coupled to the sensing node RQB, and the sample circuit 130 D can be coupled to the sensing node RQ.

In some embodiments, when the differential sensing device 100 is used to read the data stored in the memory cells MC 1 and MC 2 , the differential sensing device 100 can perform a sample operation first. During the sample operation, the path selector 120 A can form an electrical connection between the sensing node LQ and the memory cell MC 1 , and the path selector 120 B can form an electrical connection between the sensing node LQB and the reference cell 110 A. Also, the path selector 120 C can form an electrical connection between the sensing node RQB and the memory cell MC 2 , and the path selector 120 D can form an electrical connection between the sensing node RQ and the reference cell 110 B.

In this case, during the sample operation, the sample circuit 130 A can sample a cell current IC 1 generated by the memory cell MC 1 , the sample circuit 130 B can sample the reference current IR 1 , the sample circuit 130 C can sample a cell current IC 2 generated by the memory cell MC 2 , and the sample circuit 130 D can sample the reference current IR 2 .

Consequently, after the sample operation, the voltage of the sensing node LQ would be adjusted to a stable value according to the cell current IC 1 , and the voltage of the sensing node LQB would be adjusted to a stable value according to the reference current IR 1 . Similarly, the voltages of the sensing nodes RQB and RQ would be adjusted to stable values according to the cell current IC 2 and the reference current IR 2 respectively. In some embodiments, to determine the data stored in the memory cells MC 1 and MC 2 , the cell currents IC 1 and IC 2 will be compared with the reference currents IR 1 and IR 2 by performing a race operation after the sample operation.

During the race operation, the voltage of the sensing node LQ would be settled according to the race between the cell current IC 1 and the reference current IR 2 , the voltage of the sensing node LQB would be settled according to the race between the reference current IR 1 and the cell current IC 1 , the voltage of the sensing node RQB would be settled according to the race between the cell current IC 2 and the reference current IR 1 , and the voltage of the sensing node RQ would be settled according to the race between the reference current IR 2 and the cell current IC 2 . Consequently, the differential sensing device 100 can sense the voltages of the sensing nodes LQ, LQB, RQB, and RQ for reading the data stored in the memory cells MC 1 and MC 2 .

For example, during the race operation, the path selector 120 A can form an electrical connection between the sensing node LQ and the reference cell 110 B, and the path selector 120 B can form an electrical connection between the sensing node LQB and the memory cell MC 1 . Furthermore, during the race operation, the sample circuit 130 A can hold the cell current IC 1 , and the sample circuit 130 B can hold the reference current IR 1 . In this case, if the reference current IR 2 is greater than the cell current IC 1 , then the voltage of the sensing node LQ would be pulled down by the reference current IR 2 . However, if the reference current IR 2 is smaller than the cell current IC 1 , then the voltage of the sensing node LQ would be raised by the cell current IC 1 . That is, the voltage of the sensing node LQ can be used to indicate the result of subtracting the reference current IR 2 by the cell current IC 1 . Similarly, the voltage of the sensing node LQB can be used to indicate the result of subtracting the cell current IC 1 by the reference current IR 1 .

In the present embodiment, the reference current IR 1 is smaller than the reference current IR 2 . Therefore, if the memory cell MC 1 has a low resistance, the cell current IC 1 would be slightly smaller than or equal to the reference current IR 2 and would be significantly greater than the reference current IR 1 . In this case, the voltage of the sensing node LQ may not change significantly while the voltage of the sensing node LQB is dropped. However, if the memory cell MC 1 has a high resistance, the cell current IC 1 would be slightly greater than or equal to the reference current IR 1 and would be significantly smaller than the reference current IR 2 . In this case, the voltage of the sensing node LQ will be dropped while the voltage of the sensing node LQB may not change significantly.

That is, when the memory cell MC 1 has a low resistance, the voltage of the sensing node LQ will be greater than the voltage of the sensing node LQB. Also, when the memory cell MC 1 has a high resistance, the voltage of the sensing node LQ will be smaller than the voltage of the sensing node LQB. Therefore, by observing the relation between the voltages of the sensing nodes LQ and LQB, the resistance of the memory cell MC 1 can be identified, and thus, the data stored in the memory cell MC 1 can be read.

In some embodiments, the differential sensing device 100 can further include a sensing amplifier 140 A. The sensing amplifier 140 A can be coupled to the sensing nodes LQ and LQB. The sensing amplifier 140 A can output a data signal SIG DTA corresponding to the memory cell MC 1 according to the voltage difference between the sensing nodes LQ and LQB.

In FIG. 1 , the sensing amplifier 140 A can be implemented with cross-coupled inverters. For example, the sensing amplifier 140 A can include switches SWA 1 and SWA 2 , and inverters INVA 1 and INVA 2 . The switch SWA 1 has a first terminal coupled to the sensing node LQ, a second terminal, and a control terminal for receiving a sensing control signal SIG S1 . The switch SWA 2 has a first terminal coupled to the sensing node LQB, a second terminal, and a control terminal for receiving a sensing control signal SIG S1 . The inverter INVA 1 has an input terminal coupled to the second terminal of the switch SWA 1 , and an output terminal coupled to the second terminal of the switch SWA 2 . The inverter INVA 2 has an input terminal coupled to the second terminal of the switch SWA 2 , and an output terminal coupled to the second terminal of the switch SWA 1 .

In some embodiments, according to the sensing control signal SIG S1 , the switches SWA 1 and SWA 2 can be turned off during the sample operation, and can be turned on when the voltages of the sensing nodes LQ and LQB have reached stable values during the race operation. When the switches SWA 1 and SWA 2 are turned on, the inverters INVA 1 and INVA 2 can enlarge the difference between the voltages of the sensing nodes LQ and LQB and soon reach to a latched state. Consequently, the sensing amplifier 140 A can output the data signal accordingly through the output terminal of the inverter INVA 1 and/or the output terminal of the inverter INVA 2 .

Similarly, during the race operation, the path selector 120 C can form an electrical connection between the sensing node RQB and the reference cell 110 A, and path selector 120 D can form an electrical connection between the sensing node RQ and the memory cell MC 2 . Furthermore, during the race operation, the sample circuit 130 C can hold the cell current IC 2 , and the sample circuit 130 D can hold the reference current IR 2 . In this case, the voltage of the sensing node RQB can be used to indicate the result of subtracting the reference current IR 1 by the cell current IC 2 . Similarly, the voltage of the sensing node RQ can be used to indicate the result of subtracting the cell current IC 2 by the reference current IR 2 .

Therefore, if the memory cell MC 2 has a low resistance, the cell current IC 2 would be slightly smaller than or equal to the reference current IR 2 and would be significantly greater than the reference current IR 1 . In this case, the voltage of the sensing node RQ may not change significantly while the voltage of the sensing node RQB is raised. However, if the memory cell MC 2 has a high resistance, the cell current IC 2 would be slightly greater than or equal to the reference current IR 1 and would be significantly smaller than the reference current IR 2 . In this case, the voltage of the sensing node RQ will be raised while the voltage of the sensing node RQB may not change significantly.

That is, when the memory cell MC 2 has a low resistance, the voltage of the sensing node RQB will be greater than the voltage of the sensing node RQ. Also, when the memory cell MC 2 has a high resistance, the voltage of the sensing node RQB will be smaller than the voltage of the sensing node RQ. Therefore, by observing the relation between the voltages of the sensing nodes RQ and RQB, the resistance of the memory cell MC 2 can be identified, and thus, the data stored in the memory cell MC 2 can be read.

In some embodiments, the differential sensing device 100 can further include a sensing amplifier 140 B. The sensing amplifier 140 B can be coupled to the sensing nodes RQ and RQB. The sensing amplifier 140 B can be controlled by the control signal SIG s2 and output a data signal SIG DTB corresponding to the memory cell MC 2 according to the voltage difference between the sensing nodes RQ and RQB.

In this case, the differential sensing device 100 can read the data stored in the two memory cells MC 1 and MC 2 in parallel with the sensing amplifiers 140 A and 140 B while the hardware for sampling and providing the reference currents IR 1 and IR 2 can be shared, thereby reducing the circuit area required by the differential sensing device 100 and improving the reading efficiency of the differential sensing device 100 . Furthermore, since the reference cells 110 A and 110 B can provide the reference currents IR 1 and IR 2 to simulate the currents generated by a high resistance memory cell and a low resistance memory cell respectively, the sensing margin can be increased, thereby improving the sensing accuracy.

However, in some embodiments, the reference currents IR 1 and IR 2 provided by the reference cells 110 A and 110 B can also be the same if the reference currents IR 1 and IR 2 are properly selected to be in the middle point between the current corresponding to a high resistance memory cell and the current corresponding to a low resistance memory cell. Furthermore, although the memory cells MC 1 and MC 2 shown in FIG. 1 are resistive random-access memory (ReRAM) cells, in some other embodiments, the memory cells MC 1 and MC 2 can be magnetoresistive random-access memory (MRAM) cells, and the reference cells 110 A and 110 B can include magnetoresistive elements for simulating the high resistance memory cell and the low resistance memory cell correspondingly.

FIG. 2 shows a differential sensing device 200 according to another embodiment of the present invention. In some embodiments, the differential sensing devices 100 and 200 can have similar structures and can be operated with similar principles. The differential sensing device 200 includes reference cells 110 A and 110 B, path selectors 220 A, 220 B, 220 C, and 220 D, and sample circuits 230 A, 230 B, 230 C, and 230 D.

In FIG. 2 , the sample circuits 230 A, 230 B, 230 C, and 230 D can have the same structure. For example, the sample circuit 230 A can include a transistor T 1 , a capacitor C 1 , and a switch SW 1 . The transistor T 1 has a first terminal coupled to a voltage terminal VDD, a second terminal coupled to the sensing node LQ, and a control terminal. The capacitor C 1 has a first terminal coupled to the voltage terminal VDD, and a second terminal coupled to the control terminal of the transistor T 1 . The switch SW 1 has a first terminal coupled to the control terminal of the transistor T 1 , a second terminal coupled to the second terminal of the transistor T 1 , and a control terminal for receiving a control signal SIG ctr11 .

Also, in FIG. 2 , the path selectors 220 A, 220 B, 220 C, and 220 D can have the same structure. For example, the path selector 220 A can include switches SW 2 and SW 3 . The switch SW 2 has a first terminal coupled to the sensing node LQ, a second terminal coupled to the memory cell MC 1 , and a control terminal for receiving a control signal SIG ctr12 . The switch SW 3 has a first terminal coupled to the sensing node LQ, a second terminal coupled to the reference cell 110 B, and a control terminal for receiving a control signal SIG ctr13 .

In this case, during the sample operation, the control signal SIG ctr11 can turn on the switch SW 1 , the control signal SIG ctr12 can turn on the switch SW 2 , and the control signal SIG ctr13 can turn off the switch SW 3 . In this case, the sample circuit 230 A can sample the cell current IC 1 through the path selector 220 A during the sample operation.

Also, during the race operation, the control signal SIG ctrn can turn off the switch SW 1 , the control signal SIG ctr12 can turn off the switch SW 2 , and the control signal SIG ctr13 can turn on the switch SW 3 . In this case, the sample circuit 230 A can hold the cell current IC 1 with the capacitor C 1 , and the voltage of the sensing node LQ will be adjusted according to the reference current IR 2 provided by the reference cell 110 B.

Similarly, the sample circuits 230 B, 230 C, and 230 D can be controlled with the same control signal SIG ctr11 as the sample circuit 230 A. Also, the path selector 220 B, 220 C, and 220 D can be controlled with the same control signals SIG ctr12 and SIG ctr13 as the path selector 220 A.

In some embodiments, the transistors T 1 used in the sample circuits 230 A, 230 B, 230 C, and 230 D can be P-type transistors, and the switches SW 2 and SW 3 used in the path selector 220 A, 220 B, 220 C, and 220 D can be N-type transistors.

Furthermore, during the sample operation and the race operation, since the selection transistors ST 1 and ST 2 in the memory cells MC 1 and MC 2 are turned on and the source lines SL 1 and SL 2 are at a low voltage, the resistive elements RE 1 and RE 2 may be programmed if the voltages of the sensing node LQ and RQB are rather high. Therefore, in FIG. 2 , the differential sensing device 200 can further include N-type transistors N 1 , N 2 , N 3 , and N 4 for limiting the voltages received by the memory cells MC 1 and MC 2 and the reference cells 110 A and 110 B.

The N-type transistor N 1 can have a first terminal coupled to the path selector 220 A, a second terminal coupled to the memory cell MC 1 , and a control terminal for receiving a bias voltage VB 1 . The N-type transistor N 2 can have a first terminal coupled to the path selector 220 B, a second terminal coupled to the reference cell 110 A, and a control terminal for receiving a bias voltage VB 1 . The N-type transistor N 3 can have a first terminal coupled to the path selector 220 C, a second terminal coupled to the memory cell MC 2 , and a control terminal for receiving a bias voltage VB 1 . The N-type transistor N 4 can have a first terminal coupled to the path selector 220 D, a second terminal coupled to the reference cell 110 B, and a control terminal for receiving a bias voltage VB 1 .

Consequently, the voltages received by the memory cells MC 1 and MC 2 and the reference cells 110 A and 110 B can be limited by the N-type transistors N 1 , N 2 , N 3 , and N 4 so that the resistance of the memory cells MC 1 and MC 2 and the reference cells 110 A and 110 B may be maintained.

In summary, the differential sensing device provided by the embodiments of the present invention can read the data stored in two memory cells in parallel so that the hardware for sampling and providing the reference currents can be shared. Therefore the circuit area required by the differential sensing device can be reduced, and the reading efficiency of the differential sensing device can be improved.

Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.