Display panel and scan driver circuit thereof suitable for narrow border application

This application claims priority to Taiwan Application Number 109102501, filed on Jan. 22, 2020, which is herein incorporated by reference in its entirety.

The present disclosure generally relates to a display panel. More particularly, the present disclosure relates to a display panel and a related scan driver circuit suitable for narrow border application.

The narrow border design is often used in personal computer screens or house using televisions to provide visual immersion for game playing or movie watching. In addition, the vigorous development of high-bandwidth communication technology has prompted the popularization of high-quality video and audio streaming. Therefore, high resolution (e.g., 4K) and narrow border have become basic requirements for consumers to purchase displays. Compared with conventional televisions, the high resolution televisions have a higher pixel density (i.e., pixel per inch, PPI), and thus need scan driver circuits with more stages. However, a scan driver circuit with a large number of stages is unfavorable for reducing the border width of a display.

The disclosure provides a scan driver circuit including multiple stages of shift register unit and multiple gate control circuits. The multiple stages of shift register unit are disposed in a peripheral area of a display panel, and are configured to receive multiple first clock signals. The multiple gate control circuits are disposed in an active area of the display panel, and configured to receive multiple second clock signals. The active area includes multiple pixel circuits, and the multiple pixel circuits are coupled with multiple gate lines of the display panel. Each stage of shift register unit is coupled with corresponding N of the multiple gate control circuits, and is configured to provide a corresponding one of the multiple first clock signals as a control signal to the corresponding N of the multiple gate control circuits. The corresponding N of the multiple gate control circuits are coupled with corresponding M of the multiple gate lines. The corresponding N of the multiple gate control circuits are configured to provide, according to the control signal, corresponding M of the multiple second clock signals respectively as M gate signals to the corresponding M of the multiple gate lines, respectively, in which M and N are positive integers.

The disclosure provides a display panel including multiple pixel circuits disposed in an active area, multiple control lines, multiple gate lines, and a scan driver circuit. The multiple control lines and the multiple gate lines are extended from a peripheral area into the active area. The scan driver circuit includes multiple stages of shift register unit and multiple gate control circuits. Each of the multiple stages of shift register unit is coupled with corresponding N of the multiple gate control circuits through corresponding M of the multiple control lines, is configured to provide a corresponding one of the multiple first clock signals as a control signal, and is configured to provide the control signal to the corresponding N of the multiple gate control circuits through the corresponding M of the multiple control lines. The corresponding N of the multiple gate control circuits are coupled with the corresponding M of the multiple gate lines. The corresponding N of the multiple gate control circuits are configured to provide, according to the control signal, corresponding M of the multiple second clock signals respectively as M gate signals to the corresponding M of the multiple gate lines, respectively, in which M and N are positive integers.

It is to be understood that both the foregoing general description and the following detailed description are by examples, and are intended to provide further explanation of the disclosure as claimed.

FIG. 1 is a simplified functional block diagram of a display panel according to one embodiment of the present disclosure.

FIG. 2 is an enlarged view of a portion of the display panel according to one embodiment of the present disclosure.

FIG. 3 is a waveform schematic of the control signal and the gate signals according to one embodiment of the present disclosure.

FIG. 4 is an enlarged view of a portion of the display panel according to another embodiment of the present disclosure.

FIG. 5 is a circuit schematic of a shift register unit according to one embodiment of the present disclosure.

FIG. 6 is a waveform schematic of the first clock signals and the second clock signals according to one embodiment of the present disclosure.

Reference will now be made in detail to the present embodiments of the disclosure, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.

FIG. 1 is a simplified functional block diagram of a display panel 100 according to one embodiment of the present disclosure. The display panel 100 comprises a scan driver circuit 110 , a plurality of pixel circuits 120 , a plurality of gate lines GL, a plurality of data lines SL, a plurality of control lines EL, a plurality of first clock lines CLa, and a plurality of second clock lines CLb. The first clock lines CLa are configured to correspondingly transmit a plurality of first clock signals CK 1 -CK 4 . The second clock lines CLb are configured to correspondingly transmit a plurality of second clock signals HC 1 -HC 8 . The pixel circuits 120 are disposed in an active area AA of the display panel 100 , and are arranged correspondingly near intersections of the gate lines GL and the data lines SL. The display panel 100 provides data signals to the data lines SL to specify a gray value (brightness) for each pixel circuit 120 , and a time point of each pixel circuit 120 to receive the data signal are determined by a signal on a corresponding gate line GL. In other words, the active area AA is an area which the pixel circuits 120 are arranged as an array to display pictures.

The scan driver circuit 110 comprises a plurality of stages of shift register unit 1121 - 112 n and a plurality of gate control circuits 114 . The shift register units 1121 - 112 n are arranged in the peripheral area PA of the display panel 100 , in which the peripheral area PA surrounds the active area AA. The gate control circuits 114 are arranged in the active area AA, in which each gate control circuit 114 is arranged near an intersection of a corresponding second clock line CLb and a corresponding control line EL. For illustration convenience, in this disclosure “shift register unit 112 ” will be used to refer to any non-specific one among the shift register units 1121 - 112 n.

Each stage of shift register unit 112 is configured to receive a corresponding one of the first clock signals CK 1 -CK 4 from the first clock line CLa. Each stage of shift register unit 112 is further coupled with corresponding four control lines EL, and is coupled with a corresponding gate control circuit 114 through each control line EL, but this disclosure is not limited thereto. Each gate control circuit 114 is configured to receive a corresponding one of the second clock signals HC 1 -HC 8 from the second clock line CLb, and is coupled with a corresponding row of pixel circuit 120 through the gate line GL. The shift register unit 112 and the gate control circuits 114 coupled together are configured to cooperatively drive multiple corresponding rows of pixel circuit 120 .

In some embodiments, based on practical requirements, each stage of shift register unit 112 may be coupled with the control lines EL of a non-specific number, and may be coupled with gate control circuits 114 of a non-specific number through each control line EL. For example, the shift register unit 112 may be coupled with eight control lines EL, and may be coupled with two or more than two gate control circuits 114 through each control line EL to increase driving ability. Any two gate control circuits 114 , coupled with the same stage of shift register unit 112 and with the same control line EL, are coupled with the same gate line GL and receive the same one of the second clock signals HC 1 -HC 8 . On the other hand, any two gate control circuits 114 , coupled with the same stage of shift register unit 112 but with different gate lines GL, receive different two of the second clock signals HC 1 -HC 8 .

Although only one column of pixel circuit 120 is arranged between two adjacent second clock lines CLb in the embodiment of FIG. 1 , multiple columns of pixel circuit 120 may be arranged between two adjacent second clock lines CLb in practice, so as to distribute the gate control circuits 114 evenly in the active area AA.

FIG. 2 is an enlarged view of a portion of the display panel 100 according to one embodiment of the present disclosure. As shown in FIG. 2 , each gate control circuit 114 comprises a first transistor T 1 and a second transistor T 2 , in which each of the first transistor T 1 and the second transistor T 2 comprises a first terminal, a second terminal, and a control terminal. The first terminal of the first transistor T 1 is configured to receive a corresponding one of the second clock signals HC 1 -HC 8 . The second terminal of the first transistor T 1 is coupled with a corresponding gate line GL, and is configured to provide a corresponding one of multiple gate signals GP 1 -GP 4 . The control terminal of the first transistor T 1 is coupled with a corresponding shift register unit 112 through a corresponding control line EL. In this embodiment, the pixel circuit 120 comprises three sub-pixel circuits configured to provide red light, green light, and blue light, but this disclosure is not limited thereto. In practice, the number and color of sub-pixels in the pixel circuit 120 may be designed based on practical requirements.

Notably, the gate control circuits 114 of FIG. 2 are coupled with the same shift register unit 112 , and are configured to receive the same control signal CT from that same shift register unit 112 through the control lines EL.

FIG. 3 is a waveform schematic of the control signal CT and the gate signals GP 1 -GP 4 according to one embodiment of the present disclosure. Reference is made to FIG. 2 and FIG. 3 . When the control signal CT has a logic high level, the first transistor T 1 is conducted to output a corresponding one of the second clock signals HC 1 -HC 8 as a corresponding one of the gate signals GP 1 -GP 4 to the gate line GL, and the second transistor T 2 is switched off. The second clock signals HC 1 -HC 8 sequentially provide pulses as will be illustrated in the following FIG. 6 . Therefore, the gate signals GP 1 -GP 4 sequentially switch to the logic high level, and then sequentially switch to a logic low level, so as to sequentially drive multiple rows of pixel circuit 120 as shown in FIG. 2 .

In this embodiment, to ensure that waveforms of the second clock signals HC 1 -HC 8 can pass through the first transistor T 1 without degradation, the highest voltage (or amplitude) of the control signal CT is set to be higher than the highest voltage (or amplitude) of each of the second clock signals HC 1 -HC 8 . In addition, a pulse width of the control signal CT is greater than a pulse width of each of the second clock signals HC 1 -HC 8 (or each of the gate signals GP 1 -GP 4 ).

When the control signal CT has the logic low level, the first transistor T 1 and the second transistor T 2 are switched off. In this situation, if the first transistor T 1 is conducted accidentally due to oscillation of the second clock signals HC 1 -HC 8 , the second transistor T 2 forms a diode-connected transistor to stabilize the gate line GL at approximate the logic low level of the control signal CT.

FIG. 4 is an enlarged view of a portion of the display panel 100 according to another embodiment of the present disclosure. The gate control circuit 114 of FIG. 4 is similar to the gate control circuit 114 of FIG. 2 , one of the differences is that the control terminal of the second transistor T 2 of the gate control circuit 114 in FIG. 4 is coupled with the first terminal of the first transistor T 1 .

FIG. 5 is a circuit schematic of a shift register unit 500 according to one embodiment of the present disclosure. Each of the shift register units 1121 - 112 n may be implemented by the shift register unit 500 . The shift register unit 500 comprises an output node NO[i], a driving node NQ, a voltage stabilization node NP, a third transistor T 3 , a fourth transistor T 4 , a voltage input circuit 510 , and a voltage stabilization circuit 520 . The output node NO[i] is configured to provide the control signal CT, and is coupled with multiple corresponding control lines EL. The output node NO[i] is further coupled, through each control line EL, with one or more corresponding gate control circuits 114 . For example, the output node NO[i] may be coupled with all of the control lines EL in FIG. 2 .

Each of the third transistor T 3 and the fourth transistor T 4 comprises a first terminal, a second terminal, and a control terminal. The first terminal of the third transistor T 3 is configured to receive a corresponding one of the first clock signals CK 1 -CK 4 (e.g., the first clock signal CK 1 ). The second terminal of the third transistor T 3 is coupled with the output node NO[i]. The control terminal of the third transistor T 3 is coupled with the driving node NQ. That is, the third transistor T 3 is configured to provide the corresponding one of the first clock signals CK 1 -CK 4 to the output node NO[i] as the control signal CT. The first terminal of the fourth transistor T 4 is coupled with the driving node NO. The second terminal of the fourth transistor T 4 is configured to receive the first reference voltage VSSQ. The control terminal of the fourth transistor T 4 is coupled with an output node NO[i+2] of a post-two stage shift register unit 112 among the shift register units 1121 - 112 n.

The voltage input circuit 510 is configured to set the driving node NQ and the voltage stabilization node NP to the first reference voltage VSSQ or to set the driving node NQ to a second reference voltage VGHD, according to a voltage of an output node NO[i−2] of a previous-two stage shift register unit 112 among the shift register units 1121 - 112 n and also according to the start signal ST. In specific, the voltage input circuit 510 comprises a fifth transistor T 5 , a sixth transistor T 6 , and a seventh transistor T 7 , in which each of the fifth transistor T 5 , the sixth transistor T 6 , and the seventh transistor T 7 comprises a first terminal, a second terminal, and a control terminal. The first terminal of the fifth transistor T 5 is configured to receive the second reference voltage VGHD. The second terminal of the fifth transistor T 5 is coupled with the driving node NQ. The control terminal of the fifth transistor T 5 is coupled with the output node NO[i−2] of the previous-two stage shift register unit 112 . The first terminal of the sixth transistor T 6 is coupled with the driving node NQ. The second terminal of the sixth transistor T 6 is configured to receive the first reference voltage VSSQ. The control terminal of the sixth transistor T 6 is configured to receive the start signal ST. The first terminal of the seventh transistor T 7 is coupled with the voltage stabilization node NP. The second terminal of the seventh transistor T 7 is configured to receive the first reference voltage VSSQ. The control terminal of the seventh transistor T 7 is configured to receive the start signal ST.

In this embodiment, the start signal ST may provide a pulse when each frame is started to conduct the sixth transistor T 6 and the seventh transistor T 7 , so as to reset voltages of the driving node NQ and the voltage stabilization node NP.

The voltage stabilization circuit 520 is configured to stabilize voltages of the driving node NQ and the output node NO[i], according to a corresponding one of the first clock signals CK 1 -CK 4 (e.g., the first clock signal CK 1 ) and a voltage of the voltage stabilization node NP. In specific, the voltage stabilization circuit 520 comprises an eighth transistor T 8 , a ninth transistor T 9 , a tenth transistor T 10 , and a capacitor Cs, in which each of the eighth transistor T 8 , the ninth transistor T 9 , and the tenth transistor T 10 comprises a first terminal, a second terminal, and a control terminal. The first terminal of the eighth transistor T 8 is coupled with the output node NO[i]. The second terminal of the eighth transistor T 8 is configured to receive the third reference voltage VSSG. The control terminal of the eighth transistor T 8 is coupled with the voltage stabilization node NP. The first terminal of the ninth transistor T 9 is coupled with the driving node NQ. The second terminal of the ninth transistor T 9 is configured to receive the first reference voltage VSSQ. The control terminal of the ninth transistor T 9 is coupled with the voltage stabilization node NP. The first terminal of the tenth transistor T 10 is coupled with the voltage stabilization node NP. The second terminal of the tenth transistor T 10 is configured to receive the first reference voltage VSSQ. The control terminal of the tenth transistor T 10 is coupled with the driving node NQ. The capacitor Cs comprises a first terminal and a second terminal. The first terminal of the capacitor Cs is configured receive a corresponding one of the first clock signals CK 1 -CK 4 (e.g., the first clock signal CK 1 ). The second terminal of the capacitor Cs is coupled with the voltage stabilization node NP. In some embodiments, the clock signal received by the first terminal of the capacitor Cs is in phase with the clock signal received by the first terminal of the third transistor T 3 , but the first terminal of the capacitor Cs and the first terminal of the third transistor T 3 need not to receive the same clock signal and may receive different clock signals.

FIG. 6 is a waveform schematic of the first clock signals CK 1 -CK 4 and the second clock signals HC 1 -HC 8 according to one embodiment of the present disclosure. Reference is made to FIG. 1 and FIG. 6 . When the corresponding one of the first clock signals CK 1 -CK 4 received by the shift register unit 112 has the logic high level, the shift register unit 112 outputs the control signal CT having the logic high level. On the other hand, when the corresponding one of the first clock signals CK 1 -CK 4 received by the shift register unit 112 has the logic low level, the shift register unit 112 outputs the control signal CT having the logic low level.

For example, the shift register unit 1121 of FIG. 1 outputs the control signal CT having the logic high level when the first clock signal CK 1 has the logic high level. In this situation, the gate control circuit 114 coupled with the shift register unit 1121 provides the second clock signals HC 3 -HC 6 as the gate signals GP 1 -GP 4 , respectively, to sequentially drive multiple corresponding rows of pixel circuit 120 .

As another example, the shift register unit 1122 of FIG. 1 outputs control signal CT having the logic high level when the first clock signal CK 2 has the logic high level. In this situation, the gate control circuit 114 coupled with the shift register unit 1122 provides the second clock signals HC 7 -HC 8 and HC 1 -HC 2 as the gate signals GP 1 -GP 4 , respectively, to sequentially drive multiple corresponding rows of pixel circuit 120 , and so forth.

As aforementioned, to ensure that the waveforms of the second clock signals HC 1 -HC 8 can be transmitted to the gate lines GL without degradation, the highest voltage (or amplitude) of each of the first clock signals CK 1 -CK 4 is higher than the highest voltage (or amplitude) of each of the second clock signals HC 1 -HC 8 .

In addition, a pulse width of each of the first clock signals CK 1 -CK 4 is greater than a pulse width of each of the second clock signals HC 1 -HC 8 .

Moreover, if each stage of the shift register unit 112 is coupled with M control lines EL, in the pulse duration of each of the first clock signals CK 1 -CK 4 , the second clock signals HC 1 -HC 8 provide pulses of a number larger than or equal to M. For example, since each stage of the shift register unit 112 in FIG. 1 is coupled with four control lines EL, in the pulse duration of each of the first clock signals CK 1 -CK 4 , the second clock signals HC 1 -HC 8 provide pulses of a number equal to eight. By designing the first clock signals CK 1 -CK 4 to have greater pulse width, an output waveform of the gate control circuit 114 can be prevented from being affected by rising edges and falling edges of the first clock signals CK 1 -CK 4 .

In the aforementioned embodiments, the transistors of the shift register unit 112 and the gate control circuit 114 may be implemented by various suitable N-type transistors. For example, the thin-film transistor (TFT), MOSFETs, or bipolar junction transistors.

In some embodiments, the transistors of the shift register unit 112 and the gate control circuit 114 may be implemented by various P-type transistors. In this situation, the first clock signals CK 1 -CK 4 and the second clock signals HC 1 -HC 8 may have waveforms opposite to that depicted in FIG. 6 .

As can be appreciated from the foregoing descriptions, each stage of the shift register unit 112 in this disclosure can simultaneously drive multiple rows of pixel circuit 120 , different from the conventional shift register unit that can drive only one row of pixel circuit. Therefore, the display panel 100 needs few shift register units 112 , helping to reduce width of the display border.

In addition, the positions at which the gate control circuits 114 are arranged on the gate lines GL may be adjusted freely to render the gate control circuits 114 be evenly distributed in the active area AA. Therefore, signals in the display panel 100 transmitted on the gate lines GL have low transmission delay.

Certain terms are used throughout the description and the claims to refer to particular components. One skilled in the art appreciates that a component may be referred to as different names. This disclosure does not intend to distinguish between components that differ in name but not in function. In the description and in the claims, the term “comprise” is used in an open-ended fashion, and thus should be interpreted to mean “include, but not limited to.” The term “couple” is intended to compass any indirect or direct connection. Accordingly, if this disclosure mentioned that a first device is coupled with a second device, it means that the first device may be directly or indirectly connected to the second device through electrical connections, wireless communications, optical communications, or other signal connections with/without other intermediate devices or connection means.

The term “and/or” may comprise any and all combinations of one or more of the associated listed items. In addition, the singular forms “a,” “an,” and “the” herein are intended to comprise the plural forms as well, unless the context clearly indicates otherwise.

Other embodiments of the present disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the present disclosure disclosed herein. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the present disclosure being indicated by the following claims.