Serial-link receiver using time-interleaved discrete time gain

Wired communication refers to the transmission of data over a wire-based communication technology. Receiving such data, particularly at high data rates, requires sensitive, linear analog amplifiers. An amplifier is linear if its output is a linear function of its input, which means in part that signal components of different frequencies receive the same level of amplification. Linearity is difficult to obtain in practice and is a main factor limiting the speed performance of analog receivers.

The detailed description is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar elements and in which:

FIG. 1 depicts a serial receiver 100 that uses a combination of time-interleaving and discrete-time gain for rapid, efficient data reception and quantization of a serial, continuous-time signal Data on a like-identified single-ended or differential input node.

FIG. 2A details an embodiment of discrete-time variable-gain amplifier 115 ( 1 ), one of sixteen such amplifiers 115 [ 16 : 1 ] introduced in FIG. 1 .

FIG. 2B is a timing diagram 225 illustrating the operation of discrete-time variable-gain amplifier 115 ( 1 ) of FIG. 2A .

FIG. 1 depicts a serial receiver 100 that uses a combination of continuous-time equalization, analog interleaving, and discrete-time gain for rapid, efficient data reception and quantization of a serial, continuous-time input signal Data on a like-identified single-ended or differential input node. Signal Data is conveyed at a relatively high symbol rate, 56 GBd (56 billion symbols per second) as of this writing. A continuous-time equalizer 105 equalizes signal Data to provide an equalized continuous-time signal Deq that operates at the same symbol rate. In this context, a “continuous-time” signal is one that is continuous in time, and a “continuous-time” equalizer is one that is also continuous in time, e.g. it does not use any clocking and operates over a range of frequencies. Suitable continuous-time equalizers are well known to those of skill in the art so a detailed discussion is omitted.

A set of sixteen time-interleaved analog samplers 110 [ 16 : 1 ] samples equalized continuous-time signal Deq using sixteen differently phased clock signals Clk 1 through Clk 16 to obtain sixteen respective series of analog samples Da 1 through Da 16 . Timing circuitry 112 derives clock signals Clk 1 through Clk 16 from a reference clock signal Clk synchronized to signal Data. Each analog sample expressed in series Da 1 through Da 16 is a voltage level corresponding to one symbol time of equalized continuous-time signal Deq. Time interleaving samplers 110 [ 16 : 1 ] reduces the sample rate by a factor of sixteen, and thus relaxes time constraints on downstream circuitry and increases overall gain bandwidth. In this embodiment in which signal Data is conveyed at 56 GBd, for example, analog sample streams Da 1 through Da 16 are each conveyed at about 3.5 GBd. The number of time-interleaved analog samplers can be generalized to N, which may be more or fewer than sixteen in other embodiments. Analog samplers, such as so-called “track-and-hold amplifiers,” are well known to those of skill in the art.

Each of the sixteen time-interleaved analog samplers 110 [ 16 : 1 ] feeds a corresponding one of sixteen discrete-time variable-gain amplifiers 115 [ 16 : 1 ]. Amplification through discrete-time variable-gain amplifiers 115 [ 16 : 1 ] is linear relative to continuous-time variable-gain amplifiers and contributes to the overall linearity of receiver 100 . Considering equalized, continuous-time signal Da 1 , for example, one of discrete-time variable-gain amplifiers 115 [ 16 : 1 ] provides linear amplification of that series of analog symbols to produce an amplified series of analog samples Da 1 ( k ). Timing circuitry 112 controls the timing of discrete-time variable-gain amplifiers 115 [ 16 : 1 ] by issuing sixteen sets of reset and evaluation signals Rst #/Eval #, examples of which are detailed below in connection with FIGS. 2A and 2B . The remaining fifteen amplifiers 115 [ 16 : 1 ] similarly amplify signals Da 2 -Da 16 to produce amplified series of analog samples Da 2 ( k ) through Da 16 ( k ). In general, a signal xn(k) represents a sample from the nth instance of n=16:0 constituent amplifier 115 [ 16 : 1 ] at a discrete time k. The voltage gain provided by discrete-time variable-gain amplifiers 115 [ 16 : 1 ] in the discrete-time domain reduces the need for continuous-time amplification at earlier stages. Reduced continuous-time amplification allows CTE 105 and analog samplers 110 [ 16 : 1 ] to operate at lower voltage levels, and thus in more linear amplification ranges. Finally, a set of sixteen conventional quantizers 120 [ 16 : 1 ] coupled to the outputs of discrete-time variable-gain amplifiers 115 [ 16 : 1 ] quantizes analog, discrete-time signals Da 1 ( k ) through Da 16 ( k ) to produce sixteen series of digital signals D 1 ( k )-D 16 ( k ) that collectively convey the digital values represented by the original received continuous-time signal Data.

FIG. 2A details an embodiment of discrete-time variable-gain amplifier 115 ( 1 ), one of sixteen such amplifiers 115 [ 16 : 1 ] introduced in FIG. 1 . Amplifier 115 ( 1 ) is a differential amplifier with a gain stage that employs a pair of NMOS transistors M 1 and M 2 with control terminals (gates) connected to complementary input nodes to receive differential analog signal Da 1 . The sources (current-handling terminals) of transistors M 1 and M 2 are coupled to a lower power-supply terminal Vss via respective current sources 200 and to one another via a variable resistance 205 . The drains (also current-handling terminals) of transistors M 1 and M 2 are selectively coupled to complementary output nodes Da 1 ( k ) via ganged switching elements 210 , both controlled by evaluation signal Eval 1 , which can be of transistors (not shown). Output nodes Da 1 ( k ) are also coupled to upper power-supply terminal Vdd via a pair of capacitors 215 and ganged switching elements 220 that selectively discharge capacitors 215 responsive to reset signal Rst 1 .

FIG. 2B is a timing diagram 225 illustrating the operation of discrete-time variable-gain amplifier 115 ( 1 ) of FIG. 2A . The trace for signal Da 1 represents the analog voltage difference between the gates of transistors M 1 and M 2 , which voltage difference can be positive or negative depending upon the value expressed by the symbol under consideration. The trace for signal Da 1 ( k ) represents the positive or negative voltage difference between differential output nodes Da 1 ( k ).

Signals Rst 1 and Eval 1 , both digital, are low from time T 0 to T 1 to open switching elements 210 and 220 . Output nodes Da 1 ( k ) thus float at voltages that are a function of a prior symbol. Reset signal Rst 1 is asserted at time T 1 to close switching elements 220 to discharge capacitors 215 . Both nodes Da 1 ( k ) are thus set to the high supply voltage Vdd and their differential value to zero. An evaluation stage begins at time T 2 when reset signal Rst 1 returns low and evaluation signal Eval 1 is asserted. Switching elements 220 open and switching elements 210 close. The relative voltages across capacitors 220 thus change as a function of the currents through transistors M 1 and M 2 , and thus the differential voltage across the gates of transistors M 1 and M 2 . The voltage across each capacitor 215 , and thus across output nodes Da 1 ( k ), changes linearly responsive to the constant currents pulled by current sources 200 . Beginning evaluation with output nodes Da 1 ( k ) at supply voltage Vdd maximizes signal headroom and amplitude to further contribute to linearity. Source degeneration established by resistor 205 also contributes by reducing the impact of the input transconductances of transistors M 1 and M 2 on the gain of amplifier 115 ( 1 ). Resistance 205 can be tuned to establish a desired level of source degeneration and to match and calibrate amplifier 115 ( 1 ) with respect to the other variable-gain amplifiers 115 [ 16 : 2 ].

The evaluation stage ends at time T 3 when evaluation signal Eval 1 is deserted, leaving a measure of symbol magnitude stored as a voltage across nodes Da 1 ( k ). Quantizer 120 ( 1 ) quantizes the analog value of signal Da 1 ( k ) between times T 3 and T 4 to produce a digital value D 1 ( k ) ( FIG. 1 ). Reset signal Rst 1 is once again asserted in anticipation of the next symbol. Each of the reset and read stages takes about 25% of one symbol time in this example, leaving 50% for evaluation.

Input signal Data is a PAM-4 signal (for pulse-amplitude modulation, 4-level) in the example of FIG. 1 . That is, signal Data is modulated using four pulse amplitudes to represent symbols, each symbol conveying two binary bits (i.e., 00, 01, 10, and 11). Quantizer 120 [ 16 : 1 ] quantizes each analog level—each symbol—of sixteen 3.5 GBd series Da[ 16 : 1 ]( k ) into two bits for a total data rate of 112 Gb/s (3.5 GBd*16*2 bits=112 Gb/s). Binary or other modulation schemes can be used in other embodiments.

In the foregoing description and in the accompanying drawings, specific terminology and drawing symbols have been set forth to provide a thorough understanding. In some instances, the terminology and symbols may imply specific details that are not required. The term “coupled,” for example, is used herein to express a direct connection as well as a connection through one or more intervening circuits or structures. Furthermore, while the subject matter has been described in connection with specific embodiments, other embodiments are also envisioned. Therefore, the spirit and scope of the appended claims should not be limited to the foregoing description. Only those claims specifically reciting “means for” or “step for” should be construed in the manner required under the sixth paragraph of 35 U.S.C. § 112.