Display panel and pixel circuit thereof

This application claims the priority benefits of Taiwan patent application serial no. 108147304, filed on Dec. 24, 2019, and Taiwan patent application serial no. 109120751, filed on Jun. 19, 2020. The entirety of each of the above-mentioned patent applications is hereby incorporated by reference and made a part of this specification.

The disclosure relates to a display panel and a pixel circuit.

With the evolution of electronic technology, it has become an important trend to equip electronic apparatuses with high-quality display devices, and a successfully miniaturized active light-emitting diode (LED) has become a mainstream design for a flat panel display (FPD).

In the conventional technical field, brightness control of the LED may be based on pulse width modulation (PWM) and amplitude modulation. Based on work efficiency requirements of the LED, given that the LED has a high external quantum efficiency (EQE), the LED is required to operate with a sufficient amount of driving current. As a result, the high EQE of the LED cannot be effectively maintained by amplitude modulation. Besides, the PWM mechanism also faces design difficulties in response to requirements for high resolution. In addition, on the premise of maintaining the high EQE, the total amount of current flowing through the display panel may be excessive, which leads to the unlikelihood of implementation.

The disclosure provides various pixel circuits and a display panel composed of the pixel circuits, which may improve a light-emitting efficiency of an LED.

An embodiment of the disclosure provides a pixel circuit that includes a driving transistor and a light-emitting time length modulator. The driving transistor has a control terminal receiving a pulse width control signal and an amplitude control signal, and the driving transistor generates a driving signal. The light-emitting time length modulator is coupled to the driving transistor, a control switch, and the light-emitting device in series. In a first time period, the light-emitting time length modulator modulates a time length of a plurality of second time periods during which the driving signal is provided to the light-emitting device according to a light-emitting time control signal.

An embodiment of the disclosure provides another pixel circuit that includes a first control switch, a driving transistor, a second control switch, a first capacitor, and a first transistor to a fifth transistor. The first control switch has a first terminal that receives a power voltage and is controlled by a light-emitting signal. The driving transistor has a first terminal coupled to a second terminal of the first control switch. The second control switch is coupled between a second terminal of the driving transistor and the light-emitting device and controlled by the light-emitting signal. The first capacitor has one terminal receiving the power voltage and the other terminal coupled to a control terminal of the driving transistor. The first transistor has a first terminal receiving display data, a second terminal coupled to the control terminal of the driving transistor, and a control terminal receiving a first reset signal. The second transistor has a first terminal coupled to the second terminal of the first transistor, a second terminal coupled to the second terminal of the driving transistor, and a control terminal receiving a first gate driving signal. The third transistor has a first terminal receiving the display data and a second terminal coupled to the control terminal of the driving transistor. The second capacitor has one terminal receiving a timing control signal and the other terminal coupled to a control terminal of the third transistor. The fourth transistor has a first terminal coupled to the control terminal of the third transistor, a second terminal coupled to the control terminal of the driving transistor, and a control terminal receiving a second reset signal or a second gate driving signal. The fifth transistor has a first terminal receiving the display data, a second terminal coupled to the first terminal of the driving transistor, and a control terminal receiving the first gate driving signal.

An embodiment of the disclosure provides a display panel that includes a plurality of first pixel arrays and a plurality of second pixel arrays. Each of the first pixel array has a plurality of first pixel circuits. The second pixel arrays are staggered with the first pixel arrays, and each of the second pixel arrays has a plurality of second pixel circuits. Here, each of the first pixel circuits and the second pixel circuits includes a driving transistor, a control switch, and a light-emitting time length modulator. The driving transistor has a control terminal receiving a pulse width control signal and an amplitude control signal, and the driving transistor generates a driving signal. The control switch is coupled to the driving transistor and the light-emitting device in series to control a first time period during which the driving transistor generates the driving signal according to a light-emitting signal. The light-emitting time length modulator is coupled to the driving transistor, the control switch, and the light-emitting device in series. In the first time period, the light-emitting time length modulator modulates a time length of a plurality of second time periods during which the driving signal is provided to the light-emitting device according to a first light-emitting time control signal or a second light-emitting time control signal.

In view of the above, in the display panel and one pixel circuit provided in one or more embodiments of the disclosure, the light-emitting time length modulator is applied to divide the first time period (the light-emitting time period) into a plurality of second time periods, whereby the brightness is modulated. As such, the light-emitting device provided herein may stay working at the high EQE, and a uniform high brightness modulation may be performed. The other pixel circuit provided in one or more embodiments of the disclosure may have the reduced number of required devices through circuit integration, and the output quality of the driving signal may be stabilized.

Several exemplary embodiments accompanied with figures are described in detail below to further describe the disclosure in details.

The accompanying drawings are included to provide a further understanding of the disclosure, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the disclosure and, together with the description, serve to explain the principles of the disclosure.

FIG. 1A is a schematic diagram of a pixel circuit according to an embodiment of the disclosure.

FIG. 1B is a schematic diagram of a pixel circuit according to another embodiment of the disclosure.

FIG. 2 schematically illustrates an operation of a pixel circuit according to an embodiment of the disclosure.

FIG. 3 is an operational waveform of a pixel circuit according to an embodiment of the disclosure.

FIG. 4A and FIG. 4B schematically illustrate different implementation manner of a pixel circuit according to an embodiment of the disclosure, respectively.

FIG. 5 is a schematic diagram of a pixel circuit according to another embodiment of the disclosure.

FIG. 6 is an operational waveform of the pixel circuit according to the embodiment depicted in FIG. 5 .

FIG. 7 is a schematic diagram of a pixel circuit according to another embodiment of the disclosure.

FIG. 8 schematically illustrates an implementation manner of a pixel circuit according to an embodiment of the disclosure.

FIG. 9 schematically illustrates another implementation manner of a pixel circuit according to an embodiment of the disclosure.

FIG. 10 is a schematic diagram of a display panel according to an embodiment of the disclosure.

FIG. 11 is an operational waveform of the light-emitting time control signal according to the embodiment depicted in FIG. 10 .

FIG. 12A is a schematic diagram of a pixel circuit according to another embodiment of the disclosure.

FIG. 12B is an operational waveform of a pixel circuit 1200 according to an embodiment of the disclosure.

FIG. 13 is a schematic diagram of a pixel circuit according to another embodiment of the disclosure.

FIG. 1A is a schematic diagram of a pixel circuit according to an embodiment of the disclosure. As shown in FIG. 1A , a pixel circuit 100 includes a driving transistor TD and a light-emitting time length modulator 130 composed of circuits 130 - 1 and 130 - 2 . The driving transistor TD has a control terminal receiving a pulse width control signal PWC and an amplitude control signal PAM-G. The pulse width control signal PWC is generated according to a PWM signal PWM-G. The driving transistor TD generates a driving signal DS. In the embodiment, a light-emitting device LED 1 may be a light-emitting diode (LED) of any form.

On the other hand, the circuits 130 - 1 and 130 - 2 in the light-emitting time length modulator 130 are coupled to the driving transistor TD and the light-emitting device LED 1 in series. The driving transistor TD is coupled between the circuits 130 - 1 and 130 - 2 . In the embodiment, the circuits 130 - 1 and 130 - 2 are composed of transistors T 1 and T 2 , respectively, and are coupled among the driving transistor TD, a power voltage VDD, and the light-emitting device LED 1 . Control terminals of the transistors T 1 and T 2 receive a light-emitting time control signal PWEM and are switched on or off according to the light-emitting time control signal PWEM. Here, according to light-emitting time control signal PWEM, the transistors T 1 and T 2 are switched on in a plurality of second time periods in a first time period (a light-emitting time period). Time lengths of the second time periods may be adjusted according to the light-emitting time control signal PWEM, whereby the brightness of the light emitted by the light-emitting device LED 1 may be adjusted.

In some embodiments of the disclosure, one of the circuits 130 - 1 and 130 - 2 in the light-emitting time length modulator 130 may be selected to be implemented. It is unnecessary to form the circuits 130 - 1 and 130 - 2 at the same time to form the light-emitting time length modulator 130 .

FIG. 1B is a schematic diagram of a pixel circuit according to another embodiment of the disclosure. As shown in FIG. 1B , a pixel circuit 102 includes the driving transistor TD, a control switch 120 , and a light-emitting time length modulator 130 . The driving transistor TD has a control terminal receiving a pulse width control signal PWC and an amplitude control signal PAM-G. The driving transistor TD generates a driving signal DS. The control switch 120 is coupled to the driving transistor TD and the light-emitting device LED 1 in series. The control switch 120 controls a first time period during which the driving transistor TD generates the driving signal DS according to a light-emitting signal G-EM. In the embodiment, the control switch 120 is composed of a transistor T 2 . The transistor T 2 is coupled between a first terminal of the driving transistor TD and the light-emitting device LED 1 . A control terminal of the transistor T 2 receives the light-emitting signal G-EM, and in the first time period during which the transistor T 2 is switched on according to the light-emitting signal G-EM, the driving signal DS is provided to the light-emitting device LED 1 to drive the light-emitting device LED 1 to emit light.

In the embodiment of the disclosure, note that a frequency of a light-emitting time control signal PWEM is higher than a frequency of the light-emitting signal G-EM.

Please refer to FIG. 1B and FIG. 2 synchronously. FIG. 2 schematically illustrates an operation of a pixel circuit according to an embodiment of the disclosure. The horizontal axis in FIG. 2 represents time, and a vertical axis in FIG. 2 represents a current of the driving signal DS. In FIG. 2 , in a compensation time period tc, the pixel circuit 100 may perform a circuit compensation operation, and in a first time period t 1 , the control switch 120 is switched on. In addition, in a plurality of second time periods t 2 in the first time period t 1 , the transistor T 1 in the pixel circuit 100 is switched on according to the light-emitting time control signal PWEM, and brightness of the light emitted by the light-emitting device LED 1 is adjusted according to the time lengths of the second time periods.

As shown in FIG. 2 , when the brightness generated by the light-emitting device LED 1 is to be adjusted to a low display brightness, in addition to reducing the time length of the first time period t 1 , the time lengths of the second time periods t 2 may also be reduced. In the embodiment of the disclosure, note that it is not necessary to reduce the brightness of the light emitted by the light-emitting device LED 1 by reducing the current value of the driving signal DS, and the light-emitting device (the LED) LED 1 may continue to operate on the high EQE working conditions.

In addition, in the embodiment, the pixel circuit 100 further includes a pulse width control signal generator 140 . The pulse width control signal generator 140 is coupled to the control terminal of the driving transistor TD and generates a pulse width control signal PWC according to a PWM signal PWM-G. In the embodiment, the pulse width control signal generator 140 is composed of a transistor T 3 . A terminal of the transistor T 3 receives a reference voltage PPO, and another terminal is coupled to the control terminal of the driving transistor TD and provides the pulse width control signal PWC. A control terminal of the transistor T 3 receives the PWM signal PWM-G, and the transistor T 3 is switched on or off according to the PWM signal PWM-G. The reference voltage PPO may be a PWM pinch off voltage.

Incidentally, the position of the light-emitting time length modulator 130 and the position of the control switch 120 in FIG. 1B may be exchanged and should not be construed as limitations in the disclosure. In the embodiment, the control switch 120 is disposed relatively adjacent to the light-emitting device LED 1 , and the light-emitting time length modulator 130 is disposed relatively far from the light-emitting device LED 1 , which may lessen the impact on the light-emitting effects of the light-emitting device LED 1 by the light-emitting time control signal PWEM with a relatively high frequency.

In the embodiment, the transistors T 1 -T 3 and the driving transistor TD may be p-type transistors. An anode of the light-emitting device LED 1 is coupled to the transistor T 2 , and a cathode of the light-emitting device LED 1 is coupled to a reference power VSS.

Please refer to FIG. 3 , which is an operational waveform of a pixel circuit according to an embodiment of the disclosure. In a structure of a plurality of pixel circuits, the pixel circuits respectively receive light-emitting time control signals PWEM 1 -PWEM 3 . As shown by the waveforms in the upper-half of FIG. 3 , in a first time period t 31 , the light-emitting time control signals PWEM 1 -PWEM 3 may be respectively enabled in a plurality of second time periods t 321 -t 323 , whereby the brightness of corresponding light-emitting devices may be adjusted. In addition, as shown by the waveforms in the lower-half of FIG. 3 , by adjusting the time length of the first time period t 31 to the time length of the first time period t 31 ′, the brightness of the light emitted by the light-emitting device may be reduced while the EQE of the light-emitting device stays unchanged.

Next, please refer to FIG. 4A and FIG. 4B , which schematically illustrate different implementation manner of a pixel circuit according to an embodiment of the disclosure, respectively. In FIG. 4A , a pixel circuit 400 includes the driving transistor TD, a control switch 420 , a light-emitting time length modulator 430 , and a pulse width control signal generator 440 . Unlike the embodiments depicted in FIG. 1A and FIG. 1B , the light-emitting device LED 1 is coupled between the power voltage VDD and the control switch 420 . In addition, in the pixel circuit 400 , the control switch 420 is composed of a transistor T 42 , the light-emitting time length modulator 430 is composed of a transistor T 41 , and the pulse width control signal generator 440 is composed of a transistor T 43 . Here, the driving transistor TD and the transistors T 41 -T 43 are p-type transistors.

In FIG. 4B , the control switch 420 , the light-emitting time length modulator 430 , and the pulse width control signal generator 440 in a pixel circuit 400 ′ are composed of transistors T 41 ′, T 42 ′, and T 43 ′, respectively; moreover, a driving transistor TD′ and the transistors T 41 ′-T 43 ′ in the pixel circuit 400 ′ may all be n-type transistors.

FIG. 5 is a schematic diagram of a pixel circuit according to another embodiment of the disclosure. As shown in FIG. 5 , a pixel circuit 500 includes the driving transistor TD, a control switch 520 , a light-emitting time length modulator 530 , and a pulse width control signal generator 540 . In the embodiment, the control switch 520 includes transistors T 521 and T 522 . First terminals of the transistors T 521 and T 522 are commonly coupled to the driving transistor TD, and second terminals of the transistors T 521 and T 522 are respectively coupled to light-emitting devices LED 1 and LED 2 , respectively. The transistors T 521 and T 522 are controlled by light-emitting signals G-EM 1 and G-EM 2 , respectively.

In response to the control switch 520 , the light-emitting time length modulator 530 has transistors T 511 and T 512 . First terminals of the transistors T 511 and T 512 commonly receive the power voltage VDD, and second terminals of the transistors T 511 and T 512 are commonly coupled to the driving transistor TD. The transistors T 511 and T 512 are respectively controlled by the light-emitting time control signal PWEM 1 and the light-emitting time control signal PWEM 2 .

In the first time period during which the transistor T 521 is switched on, the transistor T 511 may be switched on and off in an alternate manner according to the light-emitting time control signal PWEM 1 , so as to adjust the brightness of the light emitted by the light-emitting device LED 1 . On the other hand, in another first time period during which the transistor T 522 is switched on, the transistor T 512 may be switched on and off in an alternate manner according to the light-emitting time control signal PWEM 2 , so as to adjust the brightness of the light emitted by the light-emitting device LED 2 .

In the embodiment, the light-emitting devices LED 1 and LED 2 are LEDs that may transmit light beams of different wavelengths, respectively.

Incidentally, the pulse width control signal generator 540 may be composed of the transistor T 53 .

FIG. 6 is an operational waveform of the pixel circuit according to the embodiment depicted in FIG. 5 . When the light-emitting signal G-EM 1 is in an enabled state (pulled down to a relatively low voltage level), the light-emitting time control signal PWEM 1 may be alternately disabled (raised to a relatively high voltage level) and enabled (pulled down to a relatively low voltage level), so as to adjust the brightness of the light emitted by the light-emitting device LED 1 . On the other hand, when the light-emitting signal G-EM 2 is in an enabled state (pulled down to a relatively low voltage level), the light-emitting time control signal PWEM 2 may be alternately disabled (pulled up to a relatively high voltage level) and enabled (pulled down to a relatively low voltage level), so as to adjust the brightness of the light emitted by the light-emitting device LED 2 .

FIG. 7 is a schematic diagram of a pixel circuit according to another embodiment of the disclosure. As shown in FIG. 7 , a pixel circuit 700 includes the driving transistor TD, a control switch 720 , a light-emitting time length modulator 730 , and a pulse width control signal generator 740 . The difference between the pixel circuit 700 and the pixel circuit 500 provided in the previous embodiment lies in that the control switch 720 includes three transistors T 721 -T 723 respectively coupled to three light-emitting devices LED 1 -LED 3 . The light-emitting time length modulator 730 includes transistors T 711 -T 713 corresponding to the transistors T 721 -T 723 , respectively.

An operation manner of the pixel circuit 700 in this embodiment is similar to that of the pixel circuit 500 and thus will not be further described hereinafter. The light-emitting devices LED 1 -LED 3 may emit light beams of different wavelengths.

Incidentally, the pulse width control signal generator 740 may be composed of the transistor T 73 .

FIG. 8 schematically illustrates an implementation manner of a pixel circuit according to an embodiment of the disclosure. As shown in FIG. 8 , a pixel circuit 800 includes the driving transistor TD, a control switch 820 , a light-emitting time length modulator 830 , transistors T 3 -T 7 , and capacitors C 1 -C 2 , and the transistors T 3 -T 7 and the capacitors C 1 -C 2 constitute peripheral circuits. In the embodiment, the driving transistor TD, the control switch 820 , and the light-emitting time length modulator 830 are serially connected between the power voltage VDD and the light-emitting device LED 1 , and the light-emitting device LED 1 is coupled to the reference power VSS. In addition, a first terminal of the transistor T 3 receives display data DATA[m] and is controlled by a reset signal GG-RES. A first terminal of the transistor T 4 is coupled to a second terminal of the transistor T 3 , a second terminal of transistor T 4 is coupled to the first terminal of the driving transistor TD (the coupling end point to the control switch 820 ), and the transistor T 4 is controlled by a gate driving signal G 2 [n]. The capacitor C 1 is coupled between the power voltage VDD and the control terminal of the driving transistor TD. The capacitor C 2 has a first terminal receiving a timing control signal TCS, and a second terminal coupled to the transistors T 6 and T 5 . A first terminal of the transistor T 5 is coupled to the second terminal of the capacitor C 2 , and a control terminal of the transistor T 5 receives a gate driving signal G 1 [n] or the reset signal RES. A second terminal of the transistor T 5 is coupled to the control terminal of the driving transistor TD. The transistor T 6 has a first terminal receiving the display data DATA[m], a second terminal coupled to the control terminal of the driving transistor TD, and a control terminal coupled to the second terminal of the capacitor C 2 . The transistor T 7 has a first terminal receiving the display data DATA[m], a second terminal coupled to the second terminal of the driving transistor TD, and a control terminal receiving the gate driving signal G 2 [n].

In the embodiment, the control switch 820 and the light-emitting time length modulator 830 are respectively composed of the transistors T 2 and T 1 and together form an 8T2C circuit architecture. The pixel circuit 800 may be disposed in a display panel having a pixel circuit array and may drive the light-emitting device LED 1 in a preset time sequence according to the gate driving signals G 1 [n] and G 2 [n] and the timing control signal TCS.

FIG. 9 schematically illustrates another implementation manner of a pixel circuit according to an embodiment of the disclosure. As shown in FIG. 9 , a pixel circuit 900 includes the driving transistor TD, a control switch 920 , a light-emitting time length modulator 930 , transistors T 3 -T 10 , and the capacitors C 1 -C 2 , and the transistors T 3 -T 10 and the capacitors C 1 -C 2 constitute peripheral circuits. The capacitor C 1 has a first terminal receiving a scan signal TCS. The transistor T 3 has a first terminal coupled to a second terminal of the capacitor C 1 , a second terminal of the transistor T 3 receives the reference signal REF, and the transistor T 3 is controlled by the reset signal GG-RES. The transistor T 4 has a first terminal receiving the reference signal REF, a control terminal receiving the reset signal GG-RES, and a second terminal coupled to the control terminal of the driving transistor TD. The transistor T 5 has a first terminal coupled to the control terminal of the driving transistor TD, a second terminal coupled to the first terminal of the driving transistor TD, and a control terminal receiving the gate driving signal G 2 [n]. The transistor T 6 has a first terminal coupled to the second terminal of the capacitor C 1 and a control terminal receiving the gate driving signal G 1 [n]. The transistor T 7 has a first terminal coupled to a second terminal of the transistor T 6 , a second terminal coupled to the control terminal of the driving transistor TD, and a control terminal receiving the light-emitting signal GG-EM. The transistor T 8 has a control terminal coupled to the second terminal of the capacitor C 1 and a first terminal coupled to the second terminal of the transistor T 6 . The transistor T 9 has a first terminal receiving the display data DATA[m], a second terminal coupled to a second terminal of the transistor T 8 , and a control terminal receiving the gate driving signal G 1 [n]. The transistor T 10 has a first terminal receiving the reference voltage PPO, a second terminal coupled to the second terminal of the transistor T 8 , and a control terminal receiving the light-emitting signal GG-EM. The capacitor C 2 has a first terminal receiving the power voltage VDD and the second terminal coupled to the control terminal of the driving transistor TD.

In the embodiment, the control switch 920 and the light-emitting time length modulator 930 are respectively composed of the transistors T 2 and T 1 and together form an 11T2C circuit structure. Similar to the pixel circuit provided in the embodiment depicted in FIG. 8 , the pixel circuit 900 may be arranged in a display panel having a pixel circuit array and may drive the light-emitting device LED 1 in a preset time sequence according to the gate driving signals G 1 [n] and G 2 [n] and the timing control signal TCS.

FIG. 10 is a schematic diagram of a display panel according to an embodiment of the disclosure. As shown in FIG. 10 , a display panel 1000 includes a plurality of pixel circuits P 11 -P 23 . Here, the pixel circuits P 11 -P 13 form a first pixel array PC 1 , and the pixel circuits P 21 -P 23 form a second pixel array PC 2 . The first pixel array PC 1 and the second pixel array PC 2 are staggered. In addition, the pixel circuits P 11 -P 23 may be implemented in form of any of the pixel circuits provided in the foregoing embodiments, which should not be construed as a limitation in the disclosure. It is worth mentioning that in the pixel circuits P 11 -P 13 of the first pixel array PC 1 , light-emitting time length modulators 1011 - 1013 respectively constituting the pixel circuits P 11 -P 13 are commonly controlled by the light-emitting time control signal PWEM 1 . In the pixel circuits P 21 -P 23 of the second pixel array PC 2 , light-emitting time length modulators 1021 - 1023 respectively constituting the pixel circuits P 21 -P 23 are commonly controlled by another light-emitting time control signal PWEM 2 .

Please refer to FIG. 10 and FIG. 11 synchronously, wherein FIG. 11 is an operational waveform of the light-emitting time control signal according to the embodiment depicted in FIG. 10 . In the embodiment, the light-emitting time control signal PWEM 1 and the light-emitting time control signal PWEM 2 may perform the transition operation in the same first time period. Note that the time periods tEN 1 and tEN 2 during which the light-emitting time control signal PWEM 1 and the light-emitting time control signal PWEM 2 are enabled (pulled down to a relatively low voltage level) are sequential and do not overlap. In other words, in the same display panel 1000 , the time period during which the pixel circuits P 11 -P 13 provide a driving current to the corresponding light-emitting devices LED 11 -LED 13 and the time period during which the pixel circuits P 21 -P 23 provides a driving current to the corresponding light-emitting devices LED 21 -LED 23 do not overlap. Thereby, given that the display quality of the display panel 1000 stays unchanged, the total amount of current generated by the display panel 1000 at the same time point may be reduced, the burden on power supply may be effectively reduced, and potential electromagnetic interference may be mitigated.

Incidentally, the light-emitting devices of the display panel 1000 may be divided into three groups (or more) through three (or more) light-emitting time control signals that are sequentially enabled, and the light-emitting devices may be lit up in different time periods, which may more effectively reduce the total amount of current generated by the display panel 1000 at the same time point.

FIG. 12A is a schematic diagram of a pixel circuit according to another embodiment of the disclosure. As shown in FIG. 12A , a pixel circuit 1200 includes control switches 1220 and 1230 , the driving transistor TD, the transistors T 1 -T 5 , and the capacitors C 1 -C 2 , and the transistors T 1 -T 5 and the capacitors C 1 -C 2 constitute peripheral circuits. The control switches 1220 and 1230 are composed of the transistors T 7 and T 6 , respectively. The pixel circuit 1200 is configured to drive the light-emitting device LED 1 .

In the detailed circuit structure, the control switch 1230 has a first terminal receiving the power voltage VDD, and the control switch 1230 is controlled by the light-emitting signal GG-EM. The driving transistor TD has the first terminal coupled to the second terminal of the control switch 1230 . The control switch 1220 is coupled between the second terminal of the driving transistor TD and the light-emitting device LED, and the control switch 1230 is controlled by light-emitting signal GG-EM. One terminal of the capacitor C 1 receives the power voltage VDD, and the other terminal is coupled to the control terminal of the driving transistor TD. The transistor T 1 has the first terminal receiving the display data DATA[m], the second terminal coupled to the control terminal of the driving transistor TD, and the control terminal receiving the reset signal GG-RES. The transistor T 2 has the first terminal coupled to the second terminal of the transistor T 1 , the second terminal coupled to the second terminal of the driving transistor TD, and the control terminal receiving the gate driving signal G 2 [n]. The transistor T 3 has the first terminal receiving the display data DATA[m] and the second terminal coupled to the control terminal of the driving transistor TD. One terminal of the capacitor C 2 receives the timing control signal TCS, and the other terminal is coupled to the control terminal of the transistor T 3 . The transistor T 4 has the first terminal coupled to the control terminal of the transistor T 3 , the second terminal coupled to the control terminal of the driving transistor TD, and the control terminal receiving the reset signal RES or the gate driving signal G 1 [n]. The transistor T 5 has the first terminal receiving the display data DATA[m], the second terminal coupled to the first terminal of the driving transistor TD, and the control terminal receiving the gate driving signal G 2 [n].

In terms of operation, please refer to FIG. 12B , which is an operational waveform of a pixel circuit 1200 according to an embodiment of the disclosure. In a first driving stage ts 0 , the timing control signal TCS is a descending ramp wave, the transistors T 3 , T 6 , T 7 and the driving transistor TD are switched on, and the remaining transistors T 1 , T 2 , T 4 , and T 5 are all switched off. At this time, a signal Gp continues to descend along with the timing control signal TCS, and the voltage level of the display data DATA[m] is set to the PWM pinch off voltage (e.g., the reference voltage PPO), and when the voltage of the timing control signal TCS is sufficiently low, the voltage is transmitted to the control terminal of the driving transistor TD through the transistor T 3 to raise a driving signal Ga. As such, the voltage difference between the gate and the source of the driving transistor TD may be greater than zero.

Next, in a second driving stage ts 1 , the transistors T 1 and T 4 are switched on by the reset signals RES and GG-RES, and the transistors T 6 and T 7 are switched off by the light-emitting signal GG-EM. As such, the second terminal of the capacitor C 2 (the coupling end point to the transistor T 4 ) may form a loop through the transistors T 1 and T 4 . By setting the display data DATA[m] to be at the voltage level of the reference power VSS, for instance, the voltage of the signal Gp and the driving signal Ga may be pulled down. At this time, the timing control signal TCS may be a relatively low voltage TCS_L (for instance, equal to the reference power VSS).

In a third driving stage ts 2 , the transistor T 1 is changed to an off state. The display data DATA[m] provide pulse width modulation data VP 1 of the light-emitting device LED 1 written into the capacitor C 2 through the transistors T 3 and T 4 when the gate driving signal G 1 [n] is pulled down.

Next, in a fourth driving stage ts 3 , the transistor T 4 is switched off. The timing control signal TCS is pulled up to a relatively high voltage level TCS_H at a time point, so that the capacitor C 2 pumps up the voltage. Thereby, the voltage level of the signal Gp at the second terminal of the capacitor C 2 may be substantially equal to VP 1 −Vth+TCS_H. Here, VP-Vth is the voltage level actually written to the capacitor C 2 , and Vth is the on-voltage of the transistor T 4 .

In a fifth driving stage ts 4 , the voltage level of the display data DATA[m] is again set to a voltage VO, for instance, and the transistor T 1 is switched on to reset the driving signal Ga at the driving terminal of the driving transistor TD and the capacitor C 1 through the switched-on transistor T 1 .

In a sixth driving stage ts 5 , the transistor T 1 is changed to be switched off, and the transistors T 2 and T 5 are changed to be switched on. At this time, the display data DATA[m] received by the transistor T 5 are the amplitude modulation data VP 2 and written to the control terminal of the driving transistor TD and the capacitor C 1 through the switched-on transistors T 5 and T 2 when the gate driving signal G 2 [n] is pulled down.

In a seventh driving stage ts 6 , the transistors T 2 and T 5 are changed to be switched off, and the transistors T 6 and T 7 are switched on again. Thereby, the control terminal of the driving transistor TD generates the driving signal according to the voltage on the capacitors C 1 and C 2 , so as to drive the light-emitting device LED 1 to emit light.

According to the embodiment, by setting the control switch 1220 , the impact of the parasitic capacitance of the light-emitting device LED 1 on the pixel circuit 1200 may be blocked; besides, the cathode of the light-emitting device LED 1 receives the stable DC reference power VSS, so that the light-emitting device LED 1 may receive a relatively high driving current of the driving signal. In addition, the display data DATA[m] load some commands related to the scan action, which may improve the voltage setting performance of the pixel circuit 1200 . In general, the pixel circuit 1200 requires eight transistors and two capacitors, and the number of the required circuit devices may be reduced to raise the price competitiveness.

Incidentally, the transistors T 1 -T 5 and the driving transistor TD in this embodiment may be p-type transistors.

FIG. 13 is a schematic diagram of a pixel circuit according to another embodiment of the disclosure. As shown in FIG. 13 , the circuit structure and the operation manner of the pixel circuit 1300 in FIG. 13 are similar to those of the pixel circuit 1200 . The difference therebetween lies that the transistors T 1 -T 5 in the embodiment depicted in FIG. 13 are n-type transistors. Here, the pixel circuit 1300 is designed to have the p-type transistors constituting the circuit that generates the driving signal (current) and have the n-type transistors T 1 , T 2 , T 4 , and T 5 for locking the voltage at the control terminal of the driving transistor TD. In the embodiment, the structure of the complementary transistor may effectively reduce the required voltage level at the control terminal of the driving transistor TD, reduce possible current leakage of the driving transistor TD, optimize the capacitance value, and achieve high resolution.

To sum up, in the pixel circuit provided in one or more embodiments of the disclosure, the light-emitting time length modulator may be applied to adjust the brightness of the light emitted by the light-emitting device during the light-emitting time period. Thereby, low brightness display may be achieved while the EQE of the light-emitting device stays unchanged. In another embodiment of the disclosure, the pixel circuit with the simplified structure is provided, and the working performance of the pixel circuit may still remain high.

It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed embodiment without departing from the scope or spirit of the disclosure. In view of the foregoing, it is intended that the disclosure covers modifications and variations provided that they fall within the scope of the following claims and their equivalents.