Semiconductor device

This application is a Continuation application of U.S. patent application Ser. No. 16/438,026, filed on Jun. 11, 2019, which is based upon and claims the benefit of priority of the Japanese Patent Application No. 2018-119819, filed on Jun. 25, 2018, the entire contents of which are incorporated herein by reference.

1. Field of the Invention

The present disclosure relates to a semiconductor device.

2. Description of the Related Art

A semiconductor device includes various circuit regions, and a standard cell region is used as a circuit region by way of example. In such a standard cell region, various logical circuits and power switching circuits are arranged.

For example, a power switching circuit is disposed between a power supply interconnect with supplied Vdd potential and an interconnect for supplying VVdd power to transistors in logical circuits. The VVdd power to the transistors is switched on or off by the power switching circuit. With use of the power switching circuit, power supply is switched off when the logical circuit does not need to operate whereby leak current of the transistors of the logical circuit is decreased. This can reduce power consumption. See, for example, U.S. Pat. No. 7,142,019, U.S. Publication No. 2017/0331472, Japanese Laid-Open Patent Publication Nos. 2014-072488; 2011-049477, WO 2017/208888.

However, the logical circuit in proximity of the power switching circuit may have variations of electrical characteristics, and thus the logical circuit may fail to achieve desired specifications.

The embodiments of the present disclosure provide a semiconductor device including a logical circuit so as to decrease its variations of electrical characteristics.

According to one aspect of the present disclosure, a semiconductor device includes a semiconductor substrate, a first standard cell including a first active region and a second active region, and a power switching circuit including a first switching transistor electrically connected between a first interconnect and a second interconnect over the semiconductor substrate, and including a first buffer connected to a gate of the first switching transistor, the first buffer including a third active region and a fourth active region, and wherein the first buffer adjoins, in a plan view, the first standard cell in a first direction, wherein an arrangement of the first active region matches an arrangement of the third active region in a second direction different from the first direction, and wherein an arrangement of the second active region matches an arrangement of the fourth active region in the second direction.

FIG. 1 is a diagram illustrating an example of a layout of a semiconductor device according to a first embodiment;

FIG. 2 is a diagram illustrating an example of an enlargement of a part of a standard cell region;

FIG. 3 is a circuit view illustrating an example of a configuration of a power switching circuit;

FIG. 4A is a circuit view illustrating an example of a configuration of a first buffer;

FIG. 4B is a circuit view illustrating an example of a configuration of a second buffer;

FIG. 5 is a diagram illustrating, in a plan view, an example of a configuration of a well according to the first embodiment;

FIG. 6 is a diagram illustrating, in a plan view, an example of a relationship between an active region and an element isolation region according to the first embodiment;

FIG. 7 is a diagram illustrating, in a plan view, an example of a configuration of fins, gate electrodes, and local interconnects according to the first embodiment;

FIG. 8 is a diagram illustrating, in a plan view, an example of a relationship with respect to a first interconnect layer, the gate electrodes and the local interconnects according to the first embodiment;

FIG. 9 is a diagram illustrating, in a plan view, an example of a relationship between a second interconnect layer and the first interconnect layer according to the first embodiment;

FIG. 10 is a cross-sectional view (part 1) illustrating an example of a configuration of the semiconductor device according to the first embodiment;

FIG. 11 is a cross-sectional view (part 2) illustrating an example of a configuration of the semiconductor device according to the first embodiment;

FIG. 12 is a cross-sectional view (part 3) illustrating an example of a configuration of the semiconductor device according to the first embodiment;

FIG. 13 is a diagram illustrating, in a plan view, an example of a configuration of a well according to a second embodiment;

FIG. 14 is a diagram illustrating, in a plan view, an example of a relationship between active regions and an element isolation region according to the second embodiment;

FIG. 15 is a diagram illustrating, in a plan view, an example of a configuration of fins, gate electrodes and local interconnects according to the second embodiment;

FIG. 16 is a diagram illustrating, in a plan view, an example of a relationship with respect to a first interconnect layer, the gate electrodes and the local interconnects according to the second embodiment;

FIG. 17 is a diagram illustrating, in a plan view, an example of a relationship between a second interconnect layer and the first interconnect layer according to the second embodiment;

FIG. 18 is a cross-sectional view illustrating an example of a configuration of a semiconductor device according to the second embodiment;

FIG. 19 is a diagram illustrating, in a plan view, an example of a configuration of fins, gate electrodes, and local interconnects according to a third embodiment;

FIG. 20 is a diagram illustrating, in a plan view, an example of a relationship with respect to a first interconnect layer, the gate electrodes and the local interconnects according to the third embodiment;

FIG. 21 is a diagram illustrating, in a plan view, an example of a relationship between a second interconnect layer and the first interconnect layer according to the third embodiment;

FIG. 22 is a cross-sectional view illustrating an example of a configuration of a semiconductor device according to the third embodiment;

FIG. 23 is a diagram illustrating, in a plan view, an example of a configuration of fins, gate electrodes and local interconnects according to a fourth embodiment;

FIG. 24 is a diagram illustrating, in a plan view, an example of a relationship with respect to a first interconnect layer, the gate electrodes and the local interconnects according to the fourth embodiment;

FIG. 25 is a diagram illustrating, in a plan view, an example of a relationship between a second interconnect layer and the first interconnect layer according to the fourth embodiment; and

FIG. 26 is a cross-sectional view illustrating an example of a configuration of a semiconductor device according to the fourth embodiment.

With respect to conventional semiconductor devices, the inventors have recognized that their logical circuits may suffer from an irregular operation. After careful consideration, it has been found by the inventors that, in a case where there is a design difference of the arrangement of active regions between a power switching circuit and a standard cell in which logical circuits are disposed, transistors in the standard cell may have variations of electrical characteristics. For example, with respect to the power switching circuit and the standard cell, in a case where, in a direction perpendicular to a direction in which they are arranged side by side, there is a design difference of the size between their active regions or distance between their adjacent active regions, transistors in the standard cell may have variations of electrical characteristics during manufacturing. Such variations of electrical characteristics of the transistors may result in not being able to obtain expected characteristics of the logical circuit.

In view of the above recognition, it has been found by the inventors that such variations of electrical characteristics are suppressed in a case where active regions whose arrangement matches an arrangement of active regions in the standard cell are disposed in an area adjacent to the standard region. Hereafter, the embodiments will be explained with reference to the drawings.

First Embodiment

A first embodiment is described hereafter. FIG. 1 is a diagram illustrating an example of a layout of a semiconductor device according to a first embodiment. FIG. 2 is a diagram illustrating an example of an enlargement of part of a standard cell region.

As illustrated in FIG. 1 , a semiconductor device 100 according to the first embodiment includes a plurality of standard cell regions 1 , and input and output (I/O) cell regions 2 around the standard cell regions 1 . As illustrated in FIG. 2 , in the standard cell region 1 , a plurality of standard cells 11 and a plurality of power switching circuits 12 are arranged. The standard cells 11 each include various logical circuits such as a NAND circuit and an inverter circuit. In the standard cell region 1 , Vss interconnects for supplying a ground potential to the standard cells 11 , as well as VVdd interconnects for supplying a power supply potential to the standard cells 11 , are arranged. In the present embodiment, a Vss interconnect and a VVdd interconnect are each extended in an X direction, and they are alternately arranged in a Y direction perpendicular to the X direction. For example, the standard cells 11 are each disposed in a plan view, between an adjacent VVdd interconnect and Vss interconnect.

In this description, in the Y direction, a distance between the Vss interconnect and the VVdd interconnect adjacent thereto is referred to as a height. When a standard cell 11 or a power switching circuit 12 is of one height in the Y direction, it is referred to as a single height cell. When a standard cell 11 or a power switching circuit 12 is of two or more heights in the Y direction, it is referred to as a multi-height cell. In the case of two heights, it is referred to as a double height cell.

In the layout of FIG. 2 , in the standard cell region 1 , in a plan view, the Vss interconnects that extend in the X direction, and the VVdd interconnects that extend in the X direction are alternately arranged. Also, in each of the power switching circuits 12 disposed in the standard cell region 1 , Vdd interconnects are arranged. Also, with respect to the standard cell region 1 , in an interconnect layer, a plurality of Vss interconnects, a plurality of VVdd interconnects and a plurality of Vdd interconnects, which all extend in the Y direction, are arranged, the interconnect layer being different from the Vss interconnects and the VVdd interconnects that extend in the X direction as well as differing from the Vdd interconnects in the power switching circuits 12 . The Vss interconnects extending in the X direction are each connected to a corresponding Vss interconnect extending in the Y direction through a corresponding via 13 . The VVdd interconnects extending in the X direction are each connected to a corresponding VVdd interconnect extending in the Y direction through a corresponding via 13 . The Vdd interconnects in the power switching circuit 12 are each connected to a corresponding Vdd interconnect extending in the Y direction through a corresponding via 13 . Note that the Vdd interconnects in the power switching circuit 12 may be formed in an interconnect layer different from the Vss interconnect and the VVdd interconnects that extend in the X direction. Alternatively, the Vdd interconnects in the power switching circuit 12 may be formed in a same interconnect layer as the Vss interconnect and the VVdd interconnects that extend in the X direction. By way of example, the power switching circuit 12 is disposed between two adjacent VVdd interconnects, on both sides of the Vss interconnect. In this case, the power switching circuit 12 is a double height cell. The Vdd interconnects of the power switching circuit 12 are supplied with a power supply potential from the outside. The power switching circuit 12 performs switching to supply a potential through the Vdd interconnect to the VVdd interconnect or shut off a potential supplied through the Vdd interconnect (on or off).

A configuration of the power switching circuit 12 is described hereafter. FIG. 3 is a circuit view illustrating an example of the configuration of the power switching circuit.

As illustrated in FIG. 3 , the power switching circuit 12 includes a first switching transistor SW 1 and a second switching transistor SW 2 , which are each connected between the Vdd interconnect and the VVdd interconnect. For example, each of the first switching transistor SW 1 and the second switching transistor SW 2 is a P-channel MOS transistor. The power switching circuit 12 also includes a first buffer BU connected to a gate of the first switching transistor SW 1 and a second buffer BU 2 connected to a gate of the second switching transistor SW 2 .

Hereafter, a configuration of the first buffer BU 1 and the second buffer BU 2 is described. FIG. 4A is a circuit view illustrating an example of the configuration of the first buffer. FIG. 4B is a circuit view illustrating an example of the configuration of the second buffer.

As illustrated in FIG. 4A , the first buffer BU 1 includes an inverter IV 1 a and an inverter IV 1 b . An input signal IN 1 is inputted into the inverter IV 1 a , and then output of the inverter IV 1 a is inputted into a gate of the first switching transistor SW 1 and the inverter IV 1 b . The inverter IV 1 b outputs an output signal OUT 1 . The inverters IV 1 a and IV 1 b each have two P-channel MOS transistors and two N-channel MOS transistors. Note that the configuration of inverters IV 1 a and IV 1 b is merely an example, and for example, the inverters IV 1 a and IV 1 b may each have one P-channel MOS transistor and one N-channel MOS transistor.

As illustrated in FIG. 4B , the second buffer BU 2 includes an inverter IV 2 a and an inverter IV 2 b . An input signal IN 2 is inputted into the inverter IV 2 a , and then output of the inverter IV 2 a is inputted into a gate of the second switching transistor SW 2 and the inverter IV 2 b . The inverter IV 2 b outputs an output signal OUT 2 . The inverters IV 2 a and IV 2 b each have one P-channel MOS transistor and one N-channel MOS transistor. Note that the configuration of inverters IV 2 a and IV 2 b is merely an example, and for example, the inverters IV 2 a and IV 2 b may each have two P-channel MOS transistors and two N-channel MOS transistors.

As described in detail below, an N-well with respect to the P-channel MOS transistor is, as a substrate potential, supplied with a Vdd power supply potential from the Vdd interconnect (power supply interconnect) through a well tap. Also, a P-well with respect to the N-channel MOS transistor is, as the supply potential, supplied with a Vss ground potential from the Vss interconnect (ground interconnect) through a well tap.

In the present embodiment, since the first switching transistor SW 1 has lower drivability than the second switching transistor SW 2 , a current that flows through the first switching transistor SW 1 is smaller than the second switching transistor SW 2 in a case where the switching transistors SW 1 and SW 2 are switched on. For this reason, in a case where the second switching transistor SW 2 is switched on after the first switching transistor SW 1 is switched on, a potential supplied to the VVdd interconnect can be gradually increased. If a power supply potential is rapidly supplied to a standard cell SC 51 through the VVdd interconnect, a power noise occurs in the Vdd interconnect. This may cause a malfunction, etc. in the standard cell SC 52 that is supplied with a power supply potential through the Vdd interconnect. However, as described above, by gradually increasing a potential, the above malfunction, etc. can be suppressed.

Hereafter, a layout of the standard cell 11 and the power switching circuit 12 is described. FIG. 5 is a diagram illustrating, in a plan view, an example of a configuration of a well according to the first embodiment. FIG. 6 is a diagram illustrating, in a plan view, an example of a relationship between active regions and an element isolation region according to the first embodiment. FIG. 7 is a diagram illustrating, in a plan view, an example of a configuration of fins, gate electrodes and local interconnects according to the first embodiment. FIG. 8 is a diagram illustrating, in a plan view, an example of a relationship with respect to a first interconnect layer, the gate electrodes and the local interconnects according to the first embodiment. FIG. 9 is a diagram illustrating, in a plan view, an example of a relationship between a second interconnect layer and the first interconnect layer according to the first embodiment. FIGS. 10 to 12 are cross-sectional views illustrating an example of a configuration of the semiconductor device according to the first embodiment. FIG. 10 is a cross-sectional view taken along line I-I in FIGS. 5 to 9 . FIG. 11 is a cross-sectional view taken along line II-II in FIGS. 5 to 9 . FIG. 12 is a cross-sectional view taken along line III-III in FIGS. 5 to 9 . FIGS. 5 to 12 illustrate an area between two adjacent VVdd interconnects in the Y direction.

As illustrated in FIG. 5 , etc., in the X direction, the power switching circuit 12 is disposed between standard cells SC 1 and SC 2 . Also, a fill cell FC is disposed between the standard cell SC 1 and the power switching circuit 12 . The power switching circuit 12 includes a region RSW 1 for a first switching transistor SW 1 , a region RSW 2 for a second switching transistor SW 2 , a region RWT 1 for a first well tap, and a region RWT 2 for a second well tap. The power switching circuit 12 also includes a region RBU 1 for a first buffer BU 1 , a region RBU 2 for a second buffer BU 2 , and a region RD for a dummy cell. In the X direction, the region RBU 2 adjoins the standard cell SC 2 , and the region RBU 1 adjoins the region RBU 2 . In the X direction, the region RWT 2 and the region RSW 1 each adjoin the region RBU 1 , the region RSW 2 adjoins the region RWT 2 and the region RSW 1 , and the region RWT 1 and the region RD each adjoin the region RSW 2 . In the Y direction, an interconnect M 1001 used as the Vss interconnect is arranged in the middle of the two interconnects M 1002 used as the respective VVdd interconnects. In the present embodiment, the standard cell SC 2 is an example of a first standard cell, and the regions RSW 1 and RSW 2 are examples of a region for a first switching transistor. Also, the regions RBU 1 and RBU 2 are examples of a region for a first buffer, and the region RWT 2 is an example of a region for a first well tap.

As illustrated in FIGS. 5 and 10 , etc., on a surface of a semiconductor substrate 101 , an N-well 102 N, a P-well 102 P 1 and a P-well 102 P 2 are formed. The N-well 102 N is formed under the interconnect M 1001 , between the P-well 102 P 1 and the P-well 102 P 2 . The standard cell SC 1 , the fill cell FC and the region RWT 1 are wholly formed in a region that is the N-well 102 N and the P-well 102 P 1 . The region RD, the region RSW 2 and the region RSW 1 are formed in the N-well 102 N. The region RWT 2 , the region RBU 1 , the region RBU 2 and the standard cell SC 2 are wholly formed in a region that is the N-well 102 N and the P-well 102 P 2 . In such a manner, in the present embodiment, the P-well 102 P 1 is separated from the P-well 102 P 2 , interposing the N-well 102 N in a plan view.

As described in FIG. 6 , etc., on the surface of the semiconductor substrate 101 , an element isolation region 103 for defining an active region is formed. The element isolation region 103 is formed by a STI (shallow trench isolation) method, for example. In the present disclosure, the active region refers to a region defined by the element isolation region. In such an active region, a source, a drain and a channel with respect to each transistor are formed. For example, in the case of a planar transistor, in the active region, the surface of the semiconductor substrate 101 is exposed, protruding from the element isolation region. In the case of a fin transistor, a fin protruding from the element isolation region is formed in the active region. Note that the letter N or P represented in each active region of FIG. 6 indicates a conductivity type of a well in the corresponding active region.

The standard cell SC 1 includes active regions ASC 11 , ASC 12 , ASC 13 and ASC 14 . The active regions ASC 11 , ASC 12 , ASC 13 and ASC 14 are arranged in the Y direction, for example. The active regions ASC 11 and ASC 14 are disposed in the N-well 102 N, and the active regions ASC 12 and ASC 13 are disposed in the P-well 102 P 1 . Note that for example, in a case where the standard cell SC 1 is a single height cell that includes the active regions ASC 11 and ASC 12 , another standard cell may include the active regions ASC 13 and ASC 14 .

The fill cell FC includes active regions AFC 1 , AFC 2 , AFC 3 and AFC 4 . The active regions AFC 1 , AFC 2 , AFC 3 and AFC 4 are arranged in the Y direction, for example. The active regions AFC 1 and AFC 4 are disposed in the N-well 102 N, and the active regions AFC 2 and AFC 3 are disposed in the P-well 102 P 1 .

The region RWT 1 for a well tap includes active regions AWT 11 and AWT 12 . The active region AWT 11 is disposed in the N-well 102 N, and the active region AWT 12 is disposed in the P-well 102 P 1 .

The region RD for a dummy load cell includes an active region ARD. The active region ARD is disposed in the N-well 102 N. The active regions AWT 11 and AWT 12 and the active region ARD are arranged in the Y direction, for example.

The region RSW 2 for a switching transistor SW 2 includes active regions ASW 21 and ASW 22 . The active regions ASW 21 and ASW 22 are formed in the N-well 102 N.

The region RSW 1 for a switching transistor SW 1 includes an active region ASW 1 . The active region ASW 1 is formed in the N-well 102 N.

The region RWT 2 for a well tap includes active regions AWT 2 and AWT 22 . The active region AWT 21 is disposed in the N-well 102 N, and the active region AWT 22 is disposed in the P-well 102 P 2 . The active regions AWT 21 and AWT 22 and the active region ASW 1 are arranged in the Y direction, for example.

The region RBU 1 for a buffer BU 1 includes active regions ABU 11 , ABU 12 , ABU 13 and ABU 14 . The active regions ABU 11 , ABU 12 , ABU 13 and ABU 14 are arranged in the Y direction, for example. The active regions ABU 11 and ABU 14 are disposed in the N-well 102 N, and the active regions ABU 12 and ABU 13 are disposed in the P-well 102 P 2 .

The region RBU 2 for a buffer BU 2 includes active regions ABU 21 , ABU 22 , ABU 23 and ABU 24 . The active regions ABU 21 , ABU 22 , ABU 23 and ABU 24 are arranged in the Y direction, for example. The active regions ABU 21 and ABU 24 are disposed in the N-well 102 N, and the active regions ABU 22 and ABU 23 are disposed in the P-well 102 P 2 .

The standard cell SC 2 includes active regions ASC 21 , ASC 22 , ASC 23 and ASC 24 . The active regions ASC 21 , ASC 22 , ASC 23 and ASC 24 are arranged in the Y direction, for example. The active regions ASC 21 and ASC 24 are disposed in the N-well 102 N, and the active regions ASC 22 and ASC 23 are disposed in the P-well 102 P 2 . Note that for example, in a case where the standard cell SC 2 is a single height cell that includes the active regions ASC 21 and ASC 22 , another standard cell may include the active regions ASC 23 and ASC 24 .

As illustrated in FIGS. 7 and 10 , etc., in each active region, fins 110 N or fins 110 P protruding from the element isolation region 103 are formed. The fins 110 N each constitute at least part of the N-well 102 N. The fins 110 P each constitute at least part of the P-well 102 P. The fins 110 N and the fins 110 P extend in the X direction. Also, in each active region, gate electrodes 112 and dummy gate electrodes 112 d that extend in the Y direction are formed. Gate insulator films 111 are each formed between a fin 110 N and either of a gate electrode 112 or a dummy gate electrode 112 d , as well as between a fin 110 P and either of the gate electrode 112 or a dummy gate electrode 112 d . Also, with respect to each fin 110 N in which at least a transistor is formed, a source and a drain of a P-channel MOS transistor are formed in impurity regions 104 P for P type impurity. With respect to each fin 110 P in which at least a transistor is formed, a source and a drain of an N-channel MOS transistor are formed in impurity regions 104 N for N type impurity. Local interconnects are formed over the impurity regions 104 P or 104 N. In such a manner, P-channel MOS transistor(s) or N-channel MOS transistor(s) are formed in each active region. Note that as illustrated in FIG. 12 , in the active region AWT 21 , impurity regions 104 N are formed in the fins 110 N, and in the active region AWT 22 , impurity regions 104 P are formed in the fins 110 P. Also, in the active region AWT 11 , impurity regions 104 N are formed in fins 110 N, and in the active region AWT 12 , impurity regions 104 P are formed in the fins 110 P (not shown). In such a manner, with respect to the active regions relating to the regions RWT 1 and RWT 2 for a well tap, a conductive type of the impurity region where a given fin is formed is same as that of the well where a portion of the same fin is formed.

The gate electrodes 112 and local interconnects 113 are partially shared in the active regions. The region RBU 1 includes a region RIV 1 a for an inverter IV 1 a and a region RIV 1 b for an inverter IV 1 b . In the region RIV 1 a , gate electrodes 112 are shared in the active regions ABU 11 and ABU 12 . In the region RIV 1 b , gate electrodes 112 are shared in the active regions ABU 13 and ABU 14 . Also, a local interconnect 113 that is connected to each source is shared in the active regions ABU 12 and ABU 13 . The region RBU 2 includes a region RIV 2 a for an inverter IV 2 a and a region RIV 2 b for an inverter IV 2 b . In the region RIV 2 a , a gate electrode 112 is shared in the active regions ABU 21 and ABU 22 . In the region RIV 2 b , a gate electrode 112 is shared in the active regions ABU 23 and ABU 24 . Also, a local interconnect 113 that is connected to each source is shared in the active regions ABU 22 and ABU 23 .

A material of the local interconnect 113 includes tungsten, cobalt or ruthenium, for example. For the local interconnect 113 , a base film that is formed of, e.g., titanium, titanium nitride, ruthenium or cobalt may be preferably formed. In a case where the local interconnect 113 is formed of cobalt or ruthenium, the base film may not be formed.

As illustrated in FIGS. 10 to 12 , an interlayer insulation film 121 is formed to surround the fins 110 N and 110 P, as well as the gate electrodes 112 and the dummy gate electrodes 112 d . The interlayer insulation film 121 and an interlayer insulation film 122 are formed to surround the local interconnects 113 . Further, an interlayer insulation film 123 is formed on the interlayer insulation film 122 , and a first interconnect layer M 1 including various interconnects, as illustrated in FIG. 8 , etc., is formed in the interlayer insulation film 123 . Also, an interlayer insulation film 124 is formed on the interlayer insulation film 123 , and a second interconnect layer M 2 including various interconnects, as illustrated in FIG. 9 , etc., is formed in the interlayer insulation film 124 .

As illustrated in FIG. 8 , etc., the first interconnect layer M 1 includes the interconnect M 1001 serving as the Vss interconnect, as well as including the interconnects M 1002 serving as the respective VVdd interconnects. The interconnect M 1001 is connected to each local interconnect 113 that is formed in the P-well P 102 P 1 , as well as each local interconnect 113 in the active region AWT 22 that is formed in the P-well 102 P 2 . The interconnect M 1001 is also connected to each local interconnect 113 that is shared in the active regions ABU 12 and ABU 13 as well as each local interconnect 113 that is shared in the active regions ABU 22 and ABU 23 . The interconnect M 1002 is connected to an interconnect M 1021 that is connected to a drain in the region RSW 1 as well as an interconnect M 1022 that is connected to a drain in the region RSW 2 . The first interconnect layer M 1 includes an interconnect M 1025 that is connected to a source in the region RSW 1 as well as an interconnect M 1026 that is connected to a source in the region RSW 2 .

The first interconnect layer M 1 includes an interconnect M 1011 connected to a gate in the region RIV 1 a , which constitutes an input section of the inverter IVa. The first interconnect layer M 1 includes an interconnect M 1012 connected to a gate in the region RIV 2 a , which constitutes an input section of the inverter IV 2 a . Also, the first interconnect layer M 1 includes an interconnect M 1013 , which is connected to a drain in the active region ABU 11 and a drain in the active region ABU 12 . The first interconnect layer M 1 includes an interconnect M 1014 , which is connected to a drain in the active region ABU 21 and a drain in the active region ABU 22 . The interconnect M 1013 constitutes an output section of the inverter IV 1 a , and the interconnect M 1014 constitutes an output section of the inverter IV 2 a.

The first interconnect layer M 1 includes an interconnect M 1015 connected to a gate in the region RIV 1 b , which constitutes an input section of the inverter IV 1 b . The first interconnect layer M 1 includes an interconnect M 1016 connected to a gate in a region RIV 2 b , which constitutes an input section of the inverter IV 2 b . Also, the first interconnect layer M 1 includes an interconnect M 1023 , which is connected to a drain in the active region ABU 13 and a drain in the active region ABU 14 . The first interconnect layer M 1 includes an interconnect M 1024 , which is connected to a drain in the active region ABU 23 and a drain in the active region ABU 24 . The interconnect M 1023 constitutes an output section of the inverter IV 1 b , and the interconnect M 1014 constitutes an output section of the inverter IV 2 b.

The interconnect M 1013 and the interconnect M 1015 are interconnected through part of local interconnects 113 , and the interconnect M 1014 and the interconnect M 1016 are interconnected through part of local interconnects 113 . The interconnect M 1015 is also connected to a gate in the region RSW 1 , and the interconnect M 1016 is also connected to a gate in the region RSW 2 .

The first interconnect layer M 1 includes an interconnect M 1031 that is connected to a source and a drain over the N-well 102 N in the active region AWT 11 , and includes an interconnect M 1032 that is connected to a source and a drain over the N-well 102 N in the region RWT 2 . The interconnect M 1032 is also connected to a source in the activity region ABU 11 as well as a source in the activity region ABU 21 .

The first interconnect layer M 1 includes an interconnect M 1017 , which is connected to a source in the active region ABU 14 and a source in the active region ABU 24 .

The respective interconnects included in the first interconnect layer M 1 are connected to the local interconnects 113 through a corresponding via 140 . For example, the first interconnect layer M 1 includes barrier metal films 141 and interconnect films 142 . A material of the barrier metal film 141 includes, e.g., tantalum, tantalum nitride, titanium, ruthenium or cobalt, and a material of the interconnect film 142 includes, e.g., copper. For example, the first interconnect layer M 1 , including vias 140 , is formed by a dual damascene method.

As illustrated in FIG. 9 , etc., the second interconnect layer M 2 includes interconnects M 2001 and M 2002 that each serve as the Vdd interconnect. The interconnect M 2001 is connected to an interconnect M 1031 in the active region AWT 11 as well as an interconnect M 1032 in the active region AWT 21 . The interconnect M 2001 is also connected to an interconnect M 1026 in the active region ASW 21 . The interconnect M 2002 is connected to an interconnect M 1025 in the active region ASW 1 , as well as an interconnect M 1017 that is connected to a source in the active region ABU 14 and a source in the active region ABU 24 . The interconnect M 2002 is also connected to an interconnect M 1026 in the active region ASW 22 .

The respective interconnects included in the second interconnect layer M 2 are connected to interconnects included in the first interconnect layer M 1 through a corresponding via 150 . For example, the second interconnect layer M 2 includes barrier metal films 151 and interconnect films 152 . A material of the barrier metal film 151 includes, e.g., tantalum, tantalum nitride, titanium, ruthenium or cobalt, and a material of the interconnect film 152 includes, e.g., copper. For example, the second interconnect layer M 2 , including vias 150 , is formed by a dual damascene method.

According to the first embodiment in such a manner, a power supply potential with respect to Vdd is supplied from the interconnects M 2001 and M 2002 to the N-well 102 N through the active regions AWT 11 and AWT 21 . Also, a ground potential with respect to Vss is supplied from the interconnect M 1001 to the P-wells 102 P 1 and 102 P 2 through the active regions AWT 12 and AWT 22 . The power supply potential with respect to Vdd and the ground potential with respect to Vss are also supplied to standard cells to which a given well is electrically connected, other than the regions in the X and Y directions as illustrated in FIGS. 5 to 12 . In accordance with input signals IN 1 and IN 2 , the interconnect M 1002 is supplied with a power supply potential with respect to Wdd through the power switching circuit 12 .

The interconnect M 1002 is an example of a first interconnect, and the interconnects M 2001 and M 2002 are examples of a second interconnect.

In the present embodiment, in the Y direction, an arrangement of the active regions AWT 21 and AWT 22 included in the region RWT 2 for a well tap is different from that of the active regions ASC 21 to ASC 24 included in the standard cell SC 2 . Specifically, in the Y direction, with respect to the active regions ASC 21 to ASC 24 , their edge positions are each different from the edge positions of the active regions AWT 21 and AWT 22 . Also, in the Y direction, with respect to the active regions ASC 21 to ASC 24 , their sizes may be each different from the sizes of the active regions AWT 21 and AWT 22 . Now, the regions RBU 1 and RBU 2 for a buffer are disposed between the region RWT 2 and the standard cell SC 2 . In the Y direction, the arrangements of the active regions ASC 21 to ASC 24 match the respective arrangements of the active regions ABU 11 to ABU 14 , and match the respective arrangements of the active regions ABU 21 to ABU 24 . In other words, in terms of both a position and a size in the Y direction, the active regions ASC 21 to ASC 24 respectively match the active regions ABU 11 to ABU 14 , and respectively match the active regions ABU 21 to ABU 24 . For example, in the Y direction, the arrangements of the fins in the active regions ASC 21 to ASC 24 match the respective arrangements of the fins in the active regions ABU 11 to ABU 14 , and match the respective arrangements of the fins in the active regions ABU 21 to ABU 24 . Thereby, in the first embodiment, transistors in the standard cell SC 2 are not easily affected by a difference in arrangement of the active regions between the standard cell SC 2 and the region RWT 2 . For this reason, according to the first embodiment, variations of electrical characteristics of the standard cell SC 2 can be suppressed.

Also, transistors formed in the regions RBU 1 and RBU 2 for a buffer are flexibly designed, compared to the transistors formed in the standard cell SC 2 . For example, in a case where a same standard cell is designed, no matter where it is situated in the standard cell region 1 , the standard cell may be expected to have its characteristics within a desired range. However, such a standard cell is not easily designed in consideration of variations of electrical characteristics of the standard cell, affected by a distance between the power switching circuit 12 and the standard cell. In contrast, buffers included in the power switching circuit 12 can be designed in a buffer-specific manner. In this case, transistors in the regions RBU 1 and RBU 2 for a buffer can be designed in consideration of an effect affected by the region RWT 2 for a well tap, on account of the region RWT 2 differing from the standard cell in terms of an arrangement of the active regions in the region RWT 2 and the standard cell. Accordingly, transistors in the regions RBU 1 and RBU 2 for a buffer can be preliminarily designed in consideration of an effect affected by the region RWT 2 .

Note that in the present disclosure, a match between the arrangement of regions does not mean a perfect match to the extent of not allowing for manufacturing variations. For example, even when there are manufacturing variations in the arrangements, the arrangements are considered as matching. This consideration also applies to other embodiments.

Also, the number of fins with respect to each of the active regions ABU 11 to ABU 14 may not be respectively same as that with respect to each of the active regions ABU 21 to ABU 24 . For example, part of the fins in a certain active region may be removed without removing the fins in another active region in a case where the arrangements of these active regions defined by the element isolation region match. The number of fins in an active region is not limited to a specific number, and may be an even number or an odd number, for example.

The power switching circuit 12 is not limited to a double height cell, and may be a single height cell disposed between an adjacent Vss interconnect and VVdd interconnect. The power switching circuit 12 may be a multi-height cell that has three or more heights in size in the Y direction.

Similarly, the standard cell 11 may be a single height cell or a multi-height cell. In a case where the power switching circuit 12 is, for example, a single height cell, in the buffer BU 2 that contacts with the standard cell SC 2 , the inverters 2 a and 2 b may be disposed in the respective active regions ABU 21 and ABU 22 .

In a case where the region RWT 1 for a well tap covers the region RD for a dummy cell, the interconnect M 2002 may be connected to a source and a drain in the active region ARD through the first interconnect layer M 1 , and thus this active region may be used as a well tap for an N-well. In this case, the impurity regions formed in the fins 110 N in the active region ARD are of an N conductivity type.

In the present embodiment, the second buffer BU 2 is disposed to adjoin the standard cell SC 2 , but the positions of the first buffer BU 1 and the second buffer BU 2 may be reversed. Specifically, in a plan view, the first buffer BU 1 may be disposed to adjoin the second standard cell SC 2 , between the second buffer BU 2 and the standard cell SC 2 .

Second Embodiment

A second embodiment is described hereafter. The second embodiment differs from the first embodiment in terms of the arrangement of the region RBU 2 for a buffer BU 2 . FIG. 13 is a diagram illustrating, in a plan view, an example of a configuration of a well according to the second embodiment. FIG. 14 is a diagram illustrating, in a plan view, an example of a relationship between active regions and an element isolation region according to the second embodiment. FIG. 15 is a diagram illustrating, in a plan view, an example of a configuration of fins, gate electrodes and local interconnects according to the second embodiment. FIG. 16 is a diagram illustrating, in a plan view, an example of a relationship with respect to a first interconnect layer, the gate electrodes and the local interconnects according to the second embodiment. FIG. 17 is a diagram illustrating, in a plan view, an example of a relationship between a second interconnect layer and the first interconnect layer according to the second embodiment. FIG. 18 is a cross-sectional view illustrating an example of a configuration of a semiconductor device according to the second embodiment. FIG. 18 is a cross-sectional view taken along line I-I in FIGS. 13 to 17 . FIGS. 13 to 18 illustrate an area between two adjacent VVdd interconnects in the Y direction.

As illustrated in FIGS. 13 to 18 , a power switching circuit 12 is disposed in an X direction, between standard cells SC 1 and SC 2 . The power switching circuit 12 includes a region RSW 1 for a switching transistor SW 1 , a region RSW 2 for a switching transistor SW 2 , a region RWT 1 for a first well tap, a region RWT 2 for a second well tap, a region RBU 1 for a first buffer BU 1 , and a region RBU 2 for a second buffer BU 2 . In a plan view, the region RBU 1 adjoins the standard cell SC 2 , the region RWT 2 and the region RSW 1 each adjoin the region RBU 1 , and the region RSW 2 adjoins the region RWT 2 and the region RSW 1 . In a plan view, the region RWT 1 adjoins the region RSW 2 , and the region RBU 2 adjoins the region RWT 1 . The region RWT 1 covers the region RD for a dummy cell in the first embodiment. In a plan view, an interconnect M 1001 used as a Vss interconnect is disposed between two interconnects M 1002 used as the respective VVdd interconnects.

The region RWT 1 for a well tap includes active regions AWT 11 , AWT 12 and AWT 13 . The active region AWT 13 is disposed in an N-well 102 N, as in the case of the active region ARD.

In the second embodiment, an interconnect M 2002 that constitutes the Vdd interconnect is electrically connected to a source in an active region ABU 14 through an interconnect M 1017 . The interconnect M 2002 is also electrically connected to a source in an active region ABU 24 through an interconnect M 1018 . Further, an interconnect M 2001 that constitutes the Vdd interconnect is electrically connected to a source in an active region ABU 11 through an interconnect M 1032 . The interconnect M 2001 is also electrically connected to a source in an active region ABU 21 through an interconnect M 1031 . The interconnect M 1018 is also electrically connected to an N type impurity region that is formed over an N-well 102 N in the active region AWT 13 . Also, the interconnect M 1031 is electrically connected to an N type impurity region that is formed over the N-well 102 N in the active region AWT 11 . Note that instead of the active region AWT 13 , the active region ARD used as a dummy may be disposed, as in the case of the first embodiment.

The interconnect M 2002 is also connected to the interconnect M 1018 in the active region AWT 13 , in addition to the interconnects M 1025 , M 1026 and M 1017 .

In the present embodiment, the standard cell SC 1 is an example of a second standard cell, and the standard cell SC 2 is an example of a first standard cell. The region RSW 1 is an example of a region for a first switching transistor, and the region RSW 2 is an example of a region for a second switching transistor. Also, the region RBU 1 is an example of a region for a first buffer, and the region RBU 2 is an example of a region for a second buffer. The region RWT 1 is an example of a region for a second well tap, and the region RWT 2 is an example of a region for a first well tap. The interconnects M 1002 are examples of a first interconnect, and the interconnects M 2001 and M 2002 are examples of a second interconnect.

Other configurations are same as the first embodiment.

According to the second embodiment in such a manner, a potential with respect to Vdd is supplied from the interconnects M 2001 and M 2002 to the N-well 102 N through the active regions AWT 11 , AWT 13 and AWT 21 . Also, a potential with respect to Vss is supplied from the interconnect M 1001 to the P-wells 102 P 1 and 102 P 2 through the active regions AWT 12 and AWT 22 . The power supply potential with respect to Vdd and the ground potential with respect to Vss are also supplied to each standard cell to which a given well is electrically connected, other than the regions in the X and Y directions as illustrated in FIGS. 13 to 18 . In accordance with input signals IN 1 and IN 2 , the interconnect M 1002 is supplied with a power supply potential with respect to VVdd through the power switching circuit 12 .

The second embodiment can have a similar effect to the first embodiment as well. In the second embodiment, without disposing the fill cell FC, the region RBU 2 for a buffer is disposed between the region RWT 1 and the standard cell SC 1 . In the Y direction, the respective arrangements of the active regions ABU 21 to ABU 24 match the arrangements of the active regions ASC 11 to ASC 14 . In other words, in the Y direction, with regards to the active regions ABU 21 to ABU 24 , their respective positions and sizes match the positions and sizes with respect to the active regions ASC 11 to ASC 14 . For example, in the Y direction, the respective arrangements of the fins in the active regions ABU 21 to ABU 24 match the arrangements of the fins in the active regions ASC 11 to ASC 14 . Accordingly, in the second embodiment, without disposing the fill cell FC, transistors in the standard cell SC 1 are not easily affected by a difference in the arrangement between the active region RWT 1 and the standard cell SC.

Further, the region RBU 1 for a buffer is disposed between the region RWT 2 and the standard cell SC 2 . In the Y direction, the respective arrangements of the active regions ASC 21 to ASC 24 match the arrangements of the active regions ABU 11 to ABU 14 . In other words, in the Y direction, with regards to the active regions ASC 21 to ASC 24 , their respective positions and sizes match the positions and sizes with respect to the active regions ABU 11 to ABU 14 . For example, in the Y direction, the respective arrangements of the fins in the respective active regions ASC 21 to ASC 24 match the arrangements of the fins in the active regions ABU 11 to ABU 14 . Accordingly, as in the case of the first embodiment, transistors in the standard cell SC 2 are not easily affected by a difference in the arrangement between the active region RWT 1 and the standard cell SC 2 , thereby suppressing variations of electrical characteristics of the standard cell SC 2 , as in the case of the first embodiment.

In view of the above, the second embodiment can suppress variations of electrical characteristics of the standard cells SC 1 and SC 2 along with decreasing the area, compared to the first embodiment.

Third Embodiment

A third embodiment is described hereafter. The third embodiment differs from the second embodiment in terms of the arrangement of the active regions ASW 21 and ASW 22 included in the region RSW 2 . FIG. 19 is a diagram illustrating, in a plan view, an example of a configuration of fins, gate electrodes and local interconnects according to the third embodiment. FIG. 20 is a diagram illustrating, in a plan view, an example of a relationship with respect to a first interconnect layer, the gate electrodes and the local interconnects according to the third embodiment. FIG. 21 is a diagram illustrating, in a plan view, an example of a relationship between a second interconnect layer and the first interconnect layer according to the third embodiment. FIG. 22 is a cross-sectional view illustrating an example of a configuration of a semiconductor device according to the third embodiment. FIG. 22 is a cross-sectional view taken along line I-I in FIGS. 19 to 21 . FIGS. 19 to 21 illustrate an area between two adjacent Wdd interconnects in the Y direction.

As illustrated in FIGS. 19 to 22 , in the third embodiment, an interconnect M 1016 connected to a gate in a region RSW 2 is positioned in the middle between two interconnects M 1002 in a Y direction. In the Y direction, a size of an active region ASW 21 matches a size of an active region ASW 22 . In other words, in a plan view, a portion of the interconnect M 1016 that overlaps a gate in the region RSW 2 is situated between active regions ASW 21 and ASW 22 . In such a manner, a portion of an interconnect M 1001 bypasses, in a plan view, the middle between the interconnects M 1002 so as to be situated in the active region ASW 21 . Specifically, the interconnect M 1001 includes two portions, which are bent so as to be situated in the active region ASW 21 and extend in the Y direction, and includes a portion that is connected to the two portions and that extends in an X direction. In a plan view, the portion that extends in the X direction is displaced in the Y direction with respect to a position of the interconnect M 1001 in an area where a power switching circuit 12 is not situated. For example, in a plan view, a portion of the interconnect M 1016 extends in the X direction, at the same direction as the Y direction position of the interconnect M 1001 in the region where the interconnect M 1001 does not overlap the power switching circuit 12 , and is situated between the two portions of the interconnect M 1001 that extend in the Y direction. Note that in the region RSW 2 , the above bypass portion of the interconnect M 1001 may be situated, in a plan view, between the active region ASW 21 and the interconnect M 1016 . Alternatively, such a bypass portion may be situated so as to overlap the active region ASW 21 in a plan view.

Other configurations are same as the second embodiment. Note that the interconnects M 1016 and M 1001 in the present embodiment may apply to the first embodiment.

The third embodiment can have a similar effect to the second embodiment. In the third embodiment, in the X and Y directions, the size of the active region ASW 21 matches the size of the active region ASW 22 . In such a manner, the number of fins in the active region ASW 21 is same as that in the active region ASW 22 , and thus the number of transistors in the active region ASW 21 is same as that in the active region ASW 22 . Thereby, a potential Vdd is equally supplied through the interconnects 1002 . Note that, in a case where there are manufacturing variations in the sizes, the sizes are considered as matching. This consideration also applies to other embodiments.

Fourth Embodiment

A fourth embodiment is described hereafter. The fourth embodiment differs from the third embodiment, in that gates included in a region RSW 2 are connected to a common local interconnect 113 . FIG. 23 is a diagram illustrating an example of a configuration of fins, gate electrodes and local interconnects according to the fourth embodiment. FIG. 24 is a diagram illustrating, in a plan view, an example of a relationship with respect to a first interconnect layer, the gate electrodes and the local interconnects according to the fourth embodiment. FIG. 25 is a diagram illustrating, in a plan view, an example of a relationship between a second interconnect layer and the first interconnect layer according to the fourth embodiment. FIG. 26 is a cross-sectional view illustrating an example of a configuration of a semiconductor device according to the fourth embodiment. FIG. 26 is a cross-sectional view taken along line I-I in FIGS. 23 to 25 . FIGS. 23 to 26 illustrate an area between two adjacent VVdd interconnects in the Y direction.

As illustrated in FIGS. 23 to 26 , in the fourth embodiment, gates in the region RSW 2 are commonly connected to a portion of the local interconnects 113 . In a plan view, the portion of the local interconnects 113 that overlaps the gates in the active region RSW 2 is situated between the active region ASW 21 and the active region ASW 22 . Another portion of the local interconnects extends in a Y direction, and its portion end is situated between an interconnect M 1001 and an interconnect M 1002 in an active region AWT 13 . An interconnect M 1016 is connected to said another portion of the local interconnects 113 at a position between the interconnect M 1001 and the interconnect M 1002 in the active region AWT 13 . Also, the interconnect M 1001 linearly extends in the X direction in the middle of the two interconnects M 1002 .

Other configurations are same as the third embodiment. Note that the interconnects 113 and M 1001 in the present embodiment may apply to the first embodiment.

The fourth embodiment can have a similar effect to the third embodiment. In the fourth embodiment, the interconnect M 1001 linearly extends, thereby decreasing a parasitic resistance of the interconnect M 1001 .

The embodiments have been described, but are not limited to the requirements described in the embodiments. It will be appreciated by those skilled in the art that modifications, combinations or alternative to the configurations of the foregoing embodiments are made within the scope of the present invention or the equivalent thereof. The above requirements can be appropriately defined in an application manner.