Semiconductor device

This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2019-226743, filed on Dec. 16, 2019; the entire contents of which are incorporated herein by reference.

Embodiments of the invention generally relate to a semiconductor device.

For example, it is desirable to improve the characteristics of a semiconductor device such as a transistor or the like.

FIG. 1 is a schematic cross-sectional view illustrating a semiconductor device according to a first embodiment;

FIG. 2 is a schematic cross-sectional view illustrating a semiconductor device according to a second embodiment; and

FIG. 3 is a schematic cross-sectional view illustrating a semiconductor device according to a third embodiment.

According to one embodiment, a semiconductor device includes a first electrode, a second electrode, a third electrode, a first semiconductor layer, a first insulating member, a second insulating member, a second semiconductor layer, and a first member. A direction from the first electrode toward the second electrode is along a first direction. The third electrode includes a first electrode portion. A position in the first direction of the first electrode portion is between a position in the first direction of the first electrode and a position in the first direction of the second electrode. The first semiconductor layer includes Al x1 Ga 1-x1 N (0≤x1<1). The first semiconductor layer includes a first partial region, a second partial region, a third partial region, a fourth partial region, and a fifth partial region. A second direction from the first partial region toward the first electrode crosses the first direction. A direction from the second partial region toward the second electrode is along the second direction. A direction from the third partial region toward the first electrode portion is along the second direction. The fourth partial region is between the first partial region and the third partial region in the first direction. The fifth partial region is between the third partial region and the second partial region in the first direction. The first insulating member includes a first insulating region and a second insulating region. The first insulating member includes Al and nitrogen. At least a portion of the first insulating member is amorphous. The second insulating member includes a first insulating portion and a second insulating portion. The first insulating portion is between the fourth partial region and the first insulating region in the second direction. The second insulating portion is between the fifth partial region and the second insulating region in the second direction. The second insulating portion includes silicon and nitrogen. The second semiconductor layer includes Al x2 Ga 1-x2 N (0<x2≤1 and x1<x2). The second semiconductor layer includes a first semiconductor portion, a second semiconductor portion, and a third semiconductor portion. The first semiconductor portion is between the fourth partial region and the first insulating portion in the second direction. The second semiconductor portion is between the fifth partial region and the second insulating portion in the second direction. The third semiconductor portion is between the third partial region and the first electrode portion in the second direction. The first member includes a crystal including Al x3 Ga 1-x3 N (0<x3≤1 and x2<x3). The first member is between the third semiconductor portion and the first electrode portion in the second direction.

Various embodiments are described below with reference to the accompanying drawings.

The drawings are schematic and conceptual; and the relationships between the thickness and width of portions, the proportions of sizes among portions, etc., are not necessarily the same as the actual values. The dimensions and proportions may be illustrated differently among drawings, even for identical portions.

In the specification and drawings, components similar to those described previously in an antecedent drawing are marked with like reference numerals, and a detailed description is omitted as appropriate.

First Embodiment

FIG. 1 is a schematic cross-sectional view illustrating a semiconductor device according to a first embodiment.

As shown in FIG. 1 , the semiconductor device 110 according to the embodiment includes a first electrode 51 , a second electrode 52 , a third electrode 53 , a first semiconductor layer 10 , a second semiconductor layer 20 , a first insulating member 61 , a second insulating member 62 , and a first member 31 .

The direction from the first electrode 51 toward the second electrode 52 is along a first direction D 1 . The first direction D 1 is, for example, an X-axis direction. One direction perpendicular to the X-axis direction is taken as a Z-axis direction. A direction perpendicular to the X-axis direction and the Z-axis direction is taken as a Y-axis direction.

The third electrode 53 includes a first electrode portion 53 p . The position in the first direction D 1 of the first electrode portion 53 p is between the position in the first direction D 1 of the first electrode 51 and the position in the first direction D 1 of the second electrode 52 . For example, the third electrode 53 is between the first electrode 51 and the second electrode 52 in the first direction D 1 .

The first semiconductor layer 10 includes Al x1 Ga 1-x1 N (0≤x1<1). The Al composition ratio in the first semiconductor layer 10 is, for example, not less than 0 and not more than 0.05. The first semiconductor layer 10 includes, for example, GaN.

The first semiconductor layer 10 includes a first partial region 10 a , a second partial region 10 b , a third partial region 10 c , a fourth partial region 10 d , and a fifth partial region 10 e . A second direction D 2 from the first partial region 10 a toward the first electrode 51 crosses the first direction D 1 . The second direction D 2 is, for example, the Z-axis direction. For example, the first semiconductor layer 10 spreads parallel to the X-Y plane.

The direction from the second partial region 10 b toward the second electrode 52 is along the second direction D 2 . The direction from the third partial region 10 c toward the first electrode portion 53 p is along the second direction D 2 . The fourth partial region 10 d is between the first partial region 10 a and the third partial region 10 c in the first direction D 1 . The fifth partial region 10 e is between the third partial region 10 c and the second partial region 10 b in the first direction D 1 .

The first insulating member 61 includes a first insulating region 61 a and a second insulating region 61 b . The first insulating member 61 includes Al and nitrogen. At least a portion of the first insulating member 61 is amorphous. The first insulating member 61 includes, for example, amorphous AlN. As described below, the first insulating member 61 may further include another element such as oxygen, etc.

The second insulating member 62 includes a first insulating portion 62 p and a second insulating portion 62 q . The first insulating portion 62 p is between the fourth partial region 10 d and the first insulating region 61 a in the second direction D 2 .

The second insulating portion 62 q is between the fifth partial region 10 e and the second insulating region 61 b in the second direction D 2 . The second insulating member 62 includes, for example, silicon and nitrogen. The second insulating member 62 includes, for example, SiN (e.g., Si 3 N 4 ). The second insulating member 62 may have a stacked structure including multiple films that include silicon and nitrogen with mutually-different compositions. The second insulating member 62 may be, for example, a stacked body including a Si-rich SiN film and a N-rich SiN film. For example, low current collapse and low current leakage are obtained by such a stacked structure (or stacked body). A highly reliable semiconductor device is obtained.

The second semiconductor layer 20 includes Al x2 Ga 1-x2 N (0<x2≤1 and x1<x2). The Al composition ratio in the second semiconductor layer 20 is not less than 0.05 and not more than 0.35. The second semiconductor layer 20 includes AlGaN.

The second semiconductor layer 20 includes a first semiconductor portion 21 , a second semiconductor portion 22 , and a third semiconductor portion 23 . The first semiconductor portion 21 is between the fourth partial region 10 d and the first insulating portion 62 p in the second direction D 2 . The second semiconductor portion 22 is between the fifth partial region 10 e and the second insulating portion 62 q in the second direction D 2 . The third semiconductor portion 23 is between the third partial region 10 c and the first electrode portion 53 p in the second direction D 2 .

The first member 31 includes a crystal including Al x3 Ga 1-x3 N (0<x3≤1 and x2<x3). The Al composition ratio in the first member 31 is, for example, 0.8 or more. The first member 31 may include, for example, AlN. The first member 31 is between the third semiconductor portion 23 and the first electrode portion 53 p in the second direction D 2 . The first member 31 includes a crystal.

Information that relates to the crystalline state of the first member 31 and information that relates to the amorphous state of the first insulating member 61 are obtained by, for example, electron microscopy, an X-ray diffraction image, etc.

For example, a substrate 10 s is provided as shown in FIG. 1 . The substrate 10 s may be, for example, a SiC substrate. The substrate 10 s may be a silicon substrate. A buffer layer 17 may be provided on the substrate 10 s as necessary. The buffer layer 17 includes, for example, a nitride semiconductor. For example, the first semiconductor layer 10 is provided on the substrate 10 s (e.g., on the buffer layer 17 ). The second semiconductor layer 20 is provided on the first semiconductor layer 10 . The first electrode 51 and the second electrode 52 are provided on portions of the second semiconductor layer 20 . The first member 31 is provided on a portion of the second semiconductor layer 20 . The third electrode 53 is provided on the first member 31 .

The first insulating portion 62 p is provided on the second semiconductor layer 20 between the first electrode 51 and the third electrode 53 . The first insulating region 61 a is provided on the first insulating portion 62 p . The second insulating portion 62 q is provided on the second semiconductor layer 20 between the third electrode 53 and the second electrode 52 . The second insulating region 61 b is provided on the second insulating portion 62 q.

In one example in which the substrate 10 s is insulative, a conductive layer 56 may be provided at the lower surface of the substrate 10 s . The conductive layer 56 is electrically connected to the first electrode 51 . For example, the electrical connection is performed by an interconnect 57 , etc.

A carrier region 10 E is formed in a portion of the first semiconductor layer 10 at the second semiconductor layer 20 side. The carrier region 10 E is, for example, a two-dimensional electron gas. A current that flows between the first electrode 51 and the second electrode 52 is controllable by changing the potential of the third electrode 53 . The first electrode 51 is, for example, a source electrode. The second electrode 52 is, for example, a drain electrode. The third electrode 53 is, for example, a gate electrode. The semiconductor device 110 is, for example, a HEMT (High Electron Mobility Transistor). The semiconductor device 110 is, for example, a normally-on semiconductor device.

The crystalline first member 31 is provided in the embodiment. The carrier density of the carrier region 10 E under the third electrode 53 is increased thereby. A large maximum output current is obtained thereby. According to the embodiment, a semiconductor device can be provided in which the characteristics can be improved.

According to experiments by the inventor, the carrier density when the first member 31 is a crystal is 1.5 times the carrier density when a member corresponding to the first member 31 is amorphous. According to the embodiment, for example, 1.5 times the maximum output current is obtained.

In the embodiment, the amorphous first insulating region 61 a is provided in a portion between the first electrode 51 and the third electrode 53 . The amorphous second insulating region 61 b is provided in a portion between the second electrode 52 and the third electrode 53 . For example, the unintended penetration of an element from the outside into at least one of the second insulating member 62 or the second semiconductor layer 20 can be suppressed by the first insulating region 61 a and the second insulating region 61 b . The unintended element is, for example, hydrogen. For example, the hydrogen is trapped at the interface between the first insulating member 61 and the second insulating member 62 . The hydrogen concentration in the second insulating member 62 can be reduced.

For example, the leakage current can be suppressed by suppressing the introduction of the unintended element (e.g., hydrogen). The fluctuation of the device characteristics can be suppressed. For example, high reliability is obtained.

For example, when the first insulating member 61 includes a crystal, a leakage current that is caused by the grain boundaries of the crystal flows easily. The leakage current can be suppressed when the first insulating member 61 is amorphous. According to the embodiment, a high carrier density is obtained while suppressing the leakage current.

In the embodiment, for example, the first member 31 contacts the first electrode portion 53 p . For example, the first electrode portion 53 p has a Schottky contact with the first member 31 . The third electrode 53 includes, for example, at least one selected from the group consisting of Ni, Au, Pt, W, Al, Ta, and Ti. A Schottky contact is easily obtained thereby.

On the other hand, for example, the first member 31 contacts the third semiconductor portion 23 . For example, the first member 31 can be formed on the third semiconductor portion 23 by ALD (Atomic Layer Deposition). For example, the film that is used to form the first member 31 and the first insulating member 61 is formed by a method such as ALD, etc. The portion that is provided on the crystalline third semiconductor portion 23 is used to form the first member 31 . The portion that is provided on the amorphous second insulating member 62 is used to form the first insulating member 61 .

It is favorable for a thickness t 1 along the second direction D 2 of the first member 31 (referring to FIG. 1 ) to be not less than 0.5 nm and not more than 10 nm. By setting the thickness t 1 to be 0.5 nm or more, the carrier concentration can be effectively increased. By setting the thickness t 1 to be 10 nm or less, the gate capacitance can be reduced, and a good high frequency gain is easily obtained. In the embodiment, the thickness t 1 may be not less than 4 nm and not more than 10 nm. The carrier concentration can be more effectively increased. A good high frequency gain is more easily obtained.

In the embodiment, a length L 1 along the first direction D 1 of the first electrode portion 53 p (referring to FIG. 1 ) is, for example, 0.1 μm or more. A semiconductor device that has low characteristic fluctuation is easily obtained thereby. The length L 1 is, for example, 1 μm or less. Good high frequency characteristics are easily obtained thereby.

As shown in FIG. 1 , the first insulating member 61 may further include a third insulating region 61 c . The third insulating region 61 c is between the first insulating portion 62 p and a portion of the first electrode portion 53 p in the first direction D 1 . The third insulating region 61 c is a side portion of the first insulating member 61 .

For example, the third insulating region 61 c includes a first side surface 61 ca . The first side surface 61 ca faces the first insulating portion 62 p in the first direction D 1 . In the example, the first side surface 61 ca is oblique to the first and second directions D 1 and D 2 . For example, the side surface of the first insulating portion 62 p is oblique, and the first side surface 61 ca is provided on the side surface. The third insulating region 61 c that includes the first side surface 61 ca also is amorphous. The leakage current at the side surface portion of the first insulating portion 62 p also can be suppressed thereby. For example, the unintended elements such as hydrogen, etc., can be trapped also at the interface between the first side surface 61 ca and the first insulating portion 62 p . The surface area of the interface can be large because the interface is oblique. The unintended elements are easily and efficiently trapped because the interface has a large surface area. Because the interface is oblique, a film that has a uniform film thickness and uniform film properties is easily obtained at the first side surface 61 ca.

As shown in FIG. 1 , the first insulating member 61 may further include a fourth insulating region 61 d . The fourth insulating region 61 d is between the second insulating portion 62 q and a portion of the first electrode portion 53 p in the first direction D 1 . For example, the fourth insulating region 61 d includes a second side surface 61 db . The second side surface 61 db faces the second insulating portion 62 q in the first direction D 1 . In the example, for example, the second side surface 61 db is oblique to the first and second directions D 1 and D 2 . The fourth insulating region 61 d that includes the second side surface 61 db also is amorphous. The leakage current can be effectively suppressed. The unintended elements are easily and efficiently trapped. Because the interface is oblique, a film that has a uniform film thickness and uniform film properties is easily obtained at the first side surface 61 ca . Because the interface is oblique, a locally-concentrated electric field due to intense electric field stress from the second electrode 52 can be relaxed at the side surface edge. For example, high reliability is obtained.

As shown in FIG. 1 , the third electrode 53 may further include a second electrode portion 53 q and a third electrode portion 53 r . A portion of the first insulating region 61 a of the first insulating member 61 is between the first insulating portion 62 p and the second electrode portion 53 q in the second direction D 2 . A portion of the second insulating region 61 b of the first insulating member 61 is between the second insulating portion 62 q and the third electrode portion 53 r in the second direction D 2 .

A portion of the first insulating portion 62 p at the third electrode 53 side is covered with the second electrode portion 53 q of the third electrode 53 . A portion of the second insulating portion 62 q at the third electrode 53 side is covered with the third electrode portion 53 r of the third electrode 53 . The penetration of the unintended elements (e.g., hydrogen, etc.) into these portions can be more effectively suppressed thereby. For example, the leakage current can be more effectively suppressed. It is desirable for at least one of a length L 2 in the first direction D 1 of the second electrode portion 53 q or a length L 3 in the first direction D 1 of the third electrode portion 53 r to be 0.2 μm or less. Thereby, for example, the gate capacitance can be suppressed, and good high frequency characteristics are easily obtained.

In the embodiment, the first insulating member 61 may further include oxygen in addition to Al and nitrogen. A higher hydrogen trapping efficiency is obtained thereby. The transmission of hydrogen by the first insulating member 61 can be further suppressed. The leakage current can be further suppressed. The oxygen concentration in the first insulating member 61 is, for example, 5% or more. The leakage current can be more effectively suppressed.

In the embodiment, the first insulating member 61 may further include silicon in addition to Al, nitrogen, and oxygen. A higher hydrogen trapping efficiency is obtained thereby. The transmission of hydrogen by the first insulating member 61 can be further suppressed. The leakage current can be further suppressed. The silicon concentration in the first insulating member 61 is, for example, 5% or more. The leakage current can be more effectively suppressed.

Second Embodiment

FIG. 2 is a schematic cross-sectional view illustrating a semiconductor device according to a second embodiment.

As shown in FIG. 2 , the semiconductor device 120 according to the embodiment further includes a third insulating member 63 in addition to the first electrode 51 , the second electrode 52 , the third electrode 53 , the first semiconductor layer 10 , the second semiconductor layer 20 , the first insulating member 61 , the second insulating member 62 , and the first member 31 . The configurations of the first electrode 51 , the second electrode 52 , the third electrode 53 , the first semiconductor layer 10 , the second semiconductor layer 20 , the first insulating member 61 , the second insulating member 62 , and the first member 31 of the semiconductor device 120 are applicable to those of the semiconductor device 110 . An example of the third insulating member 63 will now be described.

The first electrode portion 53 p is between the first member 31 and at least a portion of the third insulating member 63 in the second direction D 2 . The third insulating member 63 may cover at least a portion of the first electrode 51 , at least a portion of the second electrode 52 , and at least a portion of the third electrode 53 . For example, the third insulating member 63 functions as a passivation layer.

The third insulating member 63 includes silicon and at least one selected from the group consisting of nitrogen and oxygen. The third insulating member 63 includes, for example, SiN (e.g., Si 3 N 4 ). The third insulating member 63 includes, for example, SiO 2 . The third insulating member 63 includes, for example, SiON. High reliability is obtained by providing the third insulating member 63 .

Hydrogen easily diffuses toward the semiconductor layers when forming the third insulating member 63 . In the embodiment, the diffusion of hydrogen can be effectively suppressed by providing the first insulating member 61 .

Third Embodiment

FIG. 3 is a schematic cross-sectional view illustrating a semiconductor device according to a third embodiment.

As shown in FIG. 3 , the semiconductor device 130 according to the embodiment further includes a conductive member 51 F in addition to the first electrode 51 , the second electrode 52 , the third electrode 53 , the first semiconductor layer 10 , the second semiconductor layer 20 , the first insulating member 61 , the second insulating member 62 , the first member 31 , and the third insulating member 63 . The configurations of the first electrode 51 , the second electrode 52 , the third electrode 53 , the first semiconductor layer 10 , the second semiconductor layer 20 , the first insulating member 61 , the second insulating member 62 , the first member 31 , and the third insulating member 63 of the semiconductor device 130 are applicable to those of the semiconductor device 120 . An example of the conductive member 51 F will now be described.

The conductive member 51 F is electrically connected to the first electrode 51 . At least a portion of the third insulating member 63 is between the first electrode portion 53 p and at least a portion of the conductive member 51 F. For example, the conductive member 51 F functions as a field plate. The electric field concentration on the edge of the gate electrode 53 can be relaxed. High reliability is obtained due to the conductive member 51 F, for example. For example, good frequency characteristics are easily obtained due to the conductive member 51 F.

According to the embodiments, a semiconductor device can be provided in which the characteristics can be improved.

In the embodiments, “nitride semiconductor” includes all compositions of semiconductors of the chemical formula B x In y Al z Ga 1-x-y-z N (0≤x≤1, 0≤y≤1, 0≤z≤1, and x+y+z≤1) for which the composition ratios x, y, and z are changed within the ranges respectively. “Nitride semiconductor” further includes group V elements other than N (nitrogen) in the chemical formula recited above, various elements added to control various properties such as the conductivity type and the like, and various elements included unintentionally.

Hereinabove, exemplary embodiments of the invention are described with reference to specific examples. However, the embodiments of the invention are not limited to these specific examples. For example, one skilled in the art may similarly practice the invention by appropriately selecting specific configurations of components included in semiconductor devices such as semiconductor layers, electrodes, insulating members, etc., from known art. Such practice is included in the scope of the invention to the extent that similar effects thereto are obtained.

Further, any two or more components of the specific examples may be combined within the extent of technical feasibility and are included in the scope of the invention to the extent that the purport of the invention is included.

Moreover, all semiconductor devices practicable by an appropriate design modification by one skilled in the art based on the semiconductor devices described above as embodiments of the invention also are within the scope of the invention to the extent that the spirit of the invention is included.

Various other variations and modifications can be conceived by those skilled in the art within the spirit of the invention, and it is understood that such variations and modifications are also encompassed within the scope of the invention.

While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the invention.