LED panel controlling method and LED panel controlling system

The present disclosure relates to a controlling method and a controlling system. More particularly, the present disclosure relates to an LED panel controlling method and an LED panel controlling system.

Recently, owing to the fast development of LED technology, the applications of LED develop to large displaying systems. In LED display, the color retention and consistency are more difficult than other flat panels such as LCD displays. The LED switching time is nanocurrents. While coupling with its large display area with long-distance wires for signal transmission, the data transmission is bounded by the operating frequency and the wiring length. However, the frequency must be promoted for huge data transferring in a high resolution display. Hence, the stability of the system becomes low. In addition, the high frequency switching will consume more energy.

In order to solve this problem, a parallel structure is used to reduce the frequency; however, in the parallel structure, the number of wiring increases, and the implementation cost and system complex become high. Hence, there is a need to improve the controlling method and system to solve the problems.

According to one aspect of the present disclosure, an LED panel controlling method is applied to control an LED panel including (1,1) to (N,M) LED areas to display a previous frame and a current frame displayed subsequently to the previous frame. Each of the (1,1) to (N,M) LED areas includes (1,1) to (H,1) LED rows, and each of the (1,1) to (H,1) LED rows includes (1,1) to (1,D) LED pixels. The LED panel controlling method includes a frame splitting step, a comparing and transmitting step, a laminating step and a controlling step. In the frame splitting step, each of the previous frame and the current frame is split into (1,1) to (N,M) areas, and each of the (1,1) to (N,M) areas includes (1,1) to (G,K) blocks. Each of the (1,1) to (G,K) blocks includes (1,1) to (P,1) rows, and each of the (1,1) to (P,1) rows includes (1,1) to (1,E) pixels, where N, M, H, D, G, K, P and E are positive integers, G×P=H, and K×E=D. In the comparing and transmitting step, a plurality of previous datasets of the previous frame are stored in a transmitting module before a plurality of current datasets of the current frames are transmitted to and stored in the transmitting module, and the current datasets are compared to the previous datasets. Whether the current dataset of the (1,e) pixel of the (p,1) row of the (g,k) block of the (n,m) area is different from the previous dataset of the (1,e) pixel of the (p,1) row of the (g,k) block of the (n,m) area is judged, and, if yes, an area address of the (n,m) area, a block address of the (g,k) block, a row address of the (p,1) row, and the current datasets of the (1,1) to (1,E) pixels of the (p,1) row of the (g,k) block of the (n,m) area are coded and transmitted to a receiving module, where each of e, p, g, k, n and m represents a variable, e is a positive integer between 1 to E inclusive, p is a positive integer between 1 to P inclusive, g is a positive integer between 1 to G inclusive, k is a positive integer between 1 to K inclusive, n is a positive integer between 1 to N inclusive, and m is a positive integer between 1 to M inclusive. As long as the current datasets of the (g,k) block of the (n,m) area are identical to the previous datasets of the (g,k) block of the (n,m) area, the current datasets of the (g,k) block of the (n,m) area are not coded and transmitted. In the laminating step, the current datasets of the (p,1) row of one or more of the (g,1) to (g,K) blocks of the (n,m) area newly received by the receiving module are laminated with the previous datasets of the (p,1) row of the rest of the (g,1) to (g,K) blocks of the (n,m) area previously stored in the receiving module to form a (n,m)_((g-1)×P+p,1) controlling sequence. In the controlling step, the (n,m)_((g-1)×P+p,1) controlling sequence is received by a driving module to drive the ((g-1)×P+p,1) LED row of the (n,m) LED area.

According to another aspect of the present disclosure, an LED panel controlling system includes an LED panel configured to display a previous frame and a current frame displayed subsequently to the previous frame, a frame source module configured to providing the previous frame and the current frame, a transmitting module configured to receive the previous frame and the current frame, a receiving module and a driving module. The LED panel includes (1,1) to (N,M) LED areas, and each of the (1,1) to (N,M) LED areas includes (1,1) to (H,1) LED rows. Each of the (1,1) to (H,1) LED rows includes (1,1) to (1,D) LED pixels, where N, M, H and D are positive integers. Each of the previous frame and the current frame is split into (1,1) to (N,M) areas, and each of the (1,1) to (N,M) areas includes (1,1) to (G,K) blocks. Each of the (1,1) to (G,K) blocks includes (1,1) to (P,1) rows, and each of the (1,1) to (P,1) rows includes (1,1) to (1,E) pixels, where D, G, K, P and E are positive integers, G×P=H, and K×E=D. The transmitting module includes a first memorizing set configured to store a plurality of previous datasets of the previous frame, a second memorizing set configured to store a plurality of current datasets of the current frame, a comparing module configured to compare the current datasets and the previous datasets, and a coding and transmitting set. When the current dataset of the (1,e) pixel of the (p,1) row of the (g,k) block of the (n,m) area is different from the previous dataset of the (1,e) pixel of the (p,1) row of the (g,k) block of the (n,m) area, an area address of the (n,m) area, a block address of the (g,k) block, a row address of the (p,1) row, and the current datasets of the (1,1) to (1,E) pixels of the (p,1) row of the (g,k) block of the (n,m) area are coded and transmitted by the coding and transmitting set, where each of e, p, g, k, n and m represents a variable, e is a positive integer between 1 to E inclusive, p is a positive integer between 1 to P inclusive, g is a positive integer between 1 to G inclusive, k is a positive integer between 1 to K inclusive, n is a positive integer between 1 to N inclusive, and m is a positive integer between 1 to M inclusive. As long as the current datasets of the (g,k) block of the (n,m) area are identical to the previous datasets of the (g,k) block of the (n,m) area, the current datasets of the (g,k) block of the (n,m) area are not coded and transmitted. The receiving module is configured to laminate the current datasets of the (p,1) row of one or more of the (g,1) to (g,K) blocks of the (n,m) area newly received by the receiving module with the previous datasets of the (p,1) row of the rest of the (g,1) to (g,K) blocks of the (n,m) area previously stored in the receiving module to form a (n,m)_((g-1)×P+p,1) controlling sequence. The driving module includes (1,1) to (N,M) LED controlling sets to control the (1,1) to (N,M) LED areas, respectively, and the ((g-1)×P+p,1) LED row of the (n,m) LED area is driven by the (n,m) LED controlling set according to the (n,m)_((g-1)×P+p,1) controlling sequence.

The present disclosure can be more fully understood by reading the following detailed description of the embodiments, with reference made to the accompanying drawings as follows:

FIG. 1 shows a flow chart of the LED panel controlling method according to one embodiment of the present disclosure.

FIG. 2 shows an illustration of the LED panel applied to the LED panel controlling method of FIG. 1 .

FIG. 3 shows an illustration of a previous frame applied to the LED panel controlling method of FIG. 1 .

FIG. 4 shows an illustration of a current frame applied to the LED panel controlling method of FIG. 1 .

FIG. 5 shows a block diagram of an LED panel controlling system according to another embodiment of the present disclosure.

FIG. 6 shows a block diagram of the transmitting module of the LED panel controlling system of FIG. 5 .

FIG. 7 shows a block diagram of the receiving module and the controlling module of the LED panel controlling system of FIG. 5 .

FIG. 8 shows an illustration of a code format coded by the transmitting module of the LED panel controlling system of FIG. 5 .

FIG. 9 shows an illustration of a controlling sequence laminated by the receiving module of the LED panel controlling system of FIG. 5 .

FIG. 1 shows a flow chart of the LED panel controlling method 100 according to one embodiment of the present disclosure. FIG. 2 shows an illustration of the LED panel 200 applied to the LED panel controlling method 100 of FIG. 1 . FIG. 3 shows an illustration of a previous frame applied to the LED panel controlling method 100 of FIG. 1 . FIG. 4 shows an illustration of a current frame applied to the LED panel controlling method 100 of FIG. 1 . The LED panel controlling method 100 is applied to control the LED panel 200 including (1,1) to (N,M) LED areas to display a previous frame and a current frame displayed subsequently to the previous frame. Each of the (1,1) to (N,M) LED areas includes (1,1) to (H,1) LED rows, and each of the (1,1) to (H,1) LED rows includes (1,1) to (1,D) LED pixels. As shown in FIG. 2 , N is 2 and M is 2; hence, the LED panel 200 includes the (1,1) LED area LAR 0 , the (1,2) LED area LAR 1 , the (2,1) LED area LAR 2 and the (2,2) LED area LAR 3 . H is 6, and, taking the (1,1) LED area LAR 0 as an example, the (1,1) LED area LAR 0 includes the (1,1) LED row LRW 0 to the (6,1) LED row LRW 5 . D is 8, and, taking the (1,1) LED row LRW 0 as an example, the (1,1) LED row LRW 0 includes the (1,1) LED pixel LP 0 to the (1,8) LED pixel LP 7 .

The LED panel controlling method 100 includes a frame splitting step S 01 , a comparing and transmitting step S 03 , a laminating step S 04 and a controlling step S 05 .

In the frame splitting step S 01 , each of the previous frame and the current frame is split into (1,1) to (N,M) areas, and each of the (1,1) to (N,M) areas includes (1,1) to (G,K) blocks. Each of the (1,1) to (G,K) blocks includes (1,1) to (P,1) rows, and each of the (1,1) to (P,1) rows includes (1,1) to (1,E) pixels, where N, M, H, D, G, K, P and E are positive integers, G×P=H, and K×E=D. As shown in FIG. 3 , N is 2 and M is 2; hence, each of the previous frame and the current frame includes the (1,1) area AR 0 , the (1,2) area AR 1 , the (2,1) area AR 2 and the (2,2) area AR 3 . G is 2 and K is 2, and, taking the (1,1) area AR 0 as an example, the (1,1) area AR 0 includes the (1,1) block BK 0 , the (1,2) block BK 1 , the (2,1) block BK 2 and the (2,2) block BK 3 . P is 3, and, taking the (1,1) block BK 0 as an example, the (1,1) block BK 0 includes the (1,1) row RW 0 , the (2,1) row RW 1 and the (3,1) row RW 2 . E is 4, and, taking the (3,1) row RW 2 as an example, the (3,1) row RW 2 includes the (1,1) pixel P 0 , the (1,2) pixel P 1 , the (1,3) pixel P 2 and the (1,4) pixel P 3 .

In the comparing and transmitting step S 03 , a plurality of previous datasets of the previous frame are stored in a transmitting module 520 (shown in FIG. 5 ) before a plurality of current datasets of the current frame are transmitted to and stored in the transmitting module 520 , and the current datasets are compared to the previous datasets. Whether the current dataset of the (1,e) pixel of the (p,1) row of the (g,k) block of the (n,m) area is different from the previous dataset of the (1,e) pixel of the (p,1) row of the (g,k) block of the (n,m) area is judged, and, and if yes, an area address of the (n,m) area, a block address of the (g,k) block, a row address of the (p,1) row, and the current datasets of the (1,1) to (1,E) pixels of the (p,1) row of the (g,k) block of the (n,m) area are coded and transmitted to a receiving module 530 , where each of e, p, g, k, n and m represents a variable, e is a positive integer between 1 to E inclusive, p is a positive integer between 1 to P inclusive, g is a positive integer between 1 to G inclusive, k is a positive integer between 1 to K inclusive, n is a positive integer between 1 to N inclusive, and m is a positive integer between 1 to M inclusive. As long as the current datasets of the (g,k) block of the (n,m) area are identical to the previous datasets of the (g,k) block of the (n,m) area, the current datasets of the (g,k) block of the (n,m) area are not coded and transmitted.

In the laminating step S 04 , the current datasets of the (p,1) row of one or more of the (g,1) to (g,K) blocks of the (n,m) area newly received by the receiving module 530 are laminated with the previous datasets of the (p,1) row of the rest of the (g,1) to (g,K) blocks of the (n,m) area previously stored in the receiving module 530 to form a (n,m)_((g-1)×P+p,1) controlling sequence.

In the controlling step S 05 , the (n,m)_((g-1)×P+p,1) controlling sequence is received by a driving module 540 (shown in FIG. 5 ) to drive the ((g-1)×P+p,1) LED row of the (n,m) LED area.

FIG. 5 shows a block diagram of an LED panel controlling system 500 according to another embodiment of the present disclosure. FIG. 6 shows a block diagram of the transmitting module 520 of the LED panel controlling system 500 of FIG. 5 . FIG. 7 shows a block diagram of the receiving module 530 and the controlling module 540 of the LED panel controlling system 500 of FIG. 5 . The details of the LED panel controlling method 100 will be described with reference of the LED panel controlling system 500 shown in FIGS. 5 to 7 hereinafter.

The LED panel controlling system 500 can include a frame source module 550 configured to provide the previous frame and the current frame. The frame source module 550 can be, but not limited to, a computer or a camera. The LED panel controlling method 100 can further include a signal converting step S 02 , and a HDMI is converted to a DVI as transmitting the previous datasets of the previous frame or the current datasets of the current frame to the transmitting module 520 . The LED panel controlling system 500 can include a signal converting module 510 signally connected to the frame source module 550 for converting the HDMI to the DVI. The signal converting module 510 can further be signally connected to the transmitting module 520 , and, after signal converting, the signal converting module 510 can send a clock signal, an enable controlling signal, horizontal and vertical synchronous signals, and the data signal including the previous datasets or the current datasets to the transmitting module 520 .

The transmitting module 520 can be a FPGA (field programming gate array) and include a first memorizing set 521 configured to store the previous datasets of the previous frame, a second memorizing set 522 configured to store the current datasets of the current frame, a comparing module 523 configured to compare the current datasets and the previous datasets, and a coding and transmitting set 524 .

In the comparing and transmitting step S 03 , the current datasets are compared with the previous datasets row by row and block by block by the comparing module 523 . The comparing module 523 can read the first datasets stored in the first memorizing set 521 and read the second datasets stored in the second memorizing set 522 .

As shown in FIGS. 3 and 4 , the current dataset of the (1,1) pixel P 0 of the (1,1) row RW 0 of the (1,1) block BK 0 of the (1,1) area AR 0 is compared to the previous dataset of the (1,1) pixel P 0 of the (1,1) row RW 0 of the (1,1) block BK 0 of the (1,1) area AR 0 . Then, the current dataset of the (1,2) pixel P 1 of the (1,1) row RW 0 of the (1,1) block BK 0 of the (1,1) area AR 0 is compared to the previous dataset of the (1,2) pixel P 1 of the (1,1) row RW 0 of the (1,1) block BK 0 of the (1,1) area AR 0 . The comparison will be continuous until the comparison of the last pixel, i.e., the (1,4) pixel P 3 of the (3,1) row RW 2 of the (2,2) block BK 3 of the (2,2) area AR 3 , is done. And whether the current dataset is different from the previous dataset is recorded. After comparison between the current datasets and the previous datasets of the (1,1) pixel P 0 to the (1,4) pixel P 3 of the (1,1) row RW 0 of the (1,1) block BK 0 of the (1,1) area AR 0 are completed, it is found that the current datasets of the (1,2) pixel P 1 and the (1,3) pixel P 3 of the (1,1) row RW 0 of the (1,1) block BK 0 of the (1,1) area AR 0 are different from the previous datasets thereof. Hence, the current datasets thereof can be coded by the coding and transmitting set 524 with the area address of the (1,1) area AR 0 , the block address of the (1,1) block BK 0 and the row address of the (1,1) row RW 0 .

FIG. 8 shows an illustration of a code format 300 coded by the transmitting module 520 of the LED panel controlling system 500 of FIG. 5 . The code format 300 can include a position 310 for the area address of the (1,1) area AR 0 , a position 320 for the block address of the (1,1) block RW 0 , a position 330 for the row address of the (1,1) row RW 0 , and a position 340 for R-values of the current datasets of the (1,1) pixel P 0 to the (1,4) pixel P 3 , a position 350 for G-values of the current datasets of the (1,1) pixel P 0 to the (1,4) pixel P 3 , and a position 360 for B-values of the current datasets of the (1,1) pixel P 0 to the (1,4) pixel P 3 . The position 340 includes columns 341 to 344 for the R-values of the current dataset of the (1,1) pixel P 0 to the (1,4) pixel P 3 , respectively. The position 350 and the position 360 are similar to the position 340 . The R-values of the current dataset of the (1,1) pixel P 0 to the (1,4) pixel P 3 can be connected by at least one line buffer (not shown) of the coding and transmitting set 524 first and then be coded by a SPI controller (not shown) of the coding and transmitting set 524 .

Please go back to FIGS. 3 and 4 , similarly, the area address of the (1,1) area AR 0 , the block address of the (1,2) block BK 1 , the row address of the (1,1) row RW 0 , and the current dataset of the (1,1) pixel P 0 to the (1,4) pixel P 3 thereof are coded. The area address of the (1,1) area AR 0 , the block address of the (2,1) block BK 2 , the row address of the (1,1) row RW 0 , and the current dataset of the (1,1) pixel P 0 to the (1,4) pixel P 3 thereof are coded.

The LED controlling system 500 further includes a receiving module 530 and the receiving module 530 includes an address reading set 531 , a data reading set 532 , a gamma correction set 533 and a data laminating set 534 . In the recoding step S 04 , the R-value, the G-value and the B-value of each of the current datasets newly received by the receiving module 530 are gamma corrected, and an R-value, a G-value and a B-value of each of the previous datasets previously stored in the receiving module 530 have already been gamma corrected. To be more specific, after receiving the code format 300 , the address reading set 531 can read the area address of the (1,1) area AR 0 , the block address of the (1,1) block BK 0 , and the row address of the (1,1) row RW 0 , and the data reading set 532 can read the R-values, the B-values and the G-values of the current datasets thereof. Each of the R-values, the B-values and the G-values may originally have 8-bit length, and after being gamma corrected by the gamma correction set 533 , each of the R-values, the B-values and the G-values may extend to 12-bit length. Since the previous datasets have been already transmitted to the receiving module 530 before displaying of the previous frame on the LED panel 200 , all of the previous datasets have been stored in the receiving module 530 and have been gamma corrected by the gamma correction set 533 before the current datasets for displaying the current frame is transmitted.

FIG. 9 shows an illustration of a controlling sequence 400 laminated by the receiving module 530 of the LED panel controlling system 500 of FIG. 5 . Please refer to FIG. 9 with reference of FIGS. 3 to 7 , the area address of the one of the current datasets newly received is 0 which means the (1,1) area AR 0 . The block addresses of the current datasets newly received belonging to the (1,1) area AR 0 are 0, 1 and 2 which mean the (1,1), (1,2) and (2,1) blocks BK 0 , BK 1 and BK 3 , respectively. Because the (1,1) row RW 0 of the (1,1) and (1,2) blocks BK 0 and BK 1 of the (1,1) area AR 0 can be connected together to correspond to the (1,1) LED row LRW 0 of the (1,1) LED area LAR 0 , the gamma-corrected R-value of the current datasets of the (1,1) pixel P 0 to the (1,4) pixel P 3 of the (1,1) row RW 0 of the (1,1) block BK 0 of the (1,1) area AR 0 are laminated with the gamma-corrected R-value of the current datasets of the (1,1) pixel P 0 to the (1,4) pixel P 3 of the (1,1) row RW 0 of the (1,2) block BK 1 of the (1,1) area AR 0 as the controlling sequence 400 , e.g., a (1,1)_(1,1) controlling sequence 400 for controlling the (1,1) LED row LRW 0 of the (1,1) LED area LAR 0 by the data laminating set 534 . The controlling sequence 400 can include sub-sequences 410 to 430 . The sub-sequence 410 has positions 411 to 418 for the gamma corrected R-values arranged in sequence: R-value of the (1,1) pixel P 0 of the (1,1) row RW 0 of the (1,1) block BK 0 , R-value of the (1,2) pixel P 1 of the (1,1) row RW 0 of the (1,1) block BK 0 , . . . , and R-value of the (1,4) pixel P 3 of the (1,1) row RW 0 of the (1,2) block BK 1 . The sub-sequence 420 are for B-values and the sub-sequence 430 are for G-values. The sub-sequence 410 is stored in a Bram_R 535 . The sub-sequence 420 is stored in a Bram_G 536 . The sub-sequence 430 is stored in a Bram_B 537 .

Because the current datasets and the previous datasets of the (2,2) block BK 3 of the (1,1) area AR 0 are identical, the current datasets of the (2,2) block BK 3 of the (1,1) area AR 0 will not be coded and transmitted, and therefore will not be received by the receiving module. Consequently, the gamma-corrected R-value of the current datasets of the (1,1) pixel P 0 to the (1,4) pixel P 3 of the (1,1) row RW 0 of the (2,1) block BK 2 of the (1,1) area AR 0 are laminated with the gamma-corrected R-value of the previous datasets of the (1,1) pixels P 0 to the (1,4) pixels P 3 of the (1,1) row RW 0 of the (2,2) block BK 2 of the (1,1) area AR 0 as a controlling sequence 400 , e.g., the (1,1)_(4,1) controlling sequence 400 for controlling the (4,1) LED row LR 3 of the (1,1) LED area LAR 0 .

In addition, since the current datasets and the previous datasets of the (1,2), (2,1) and (2,2) areas AR 1 to AR 3 are identical, the (1,2), (2,1) and (2,2) LED areas AR 1 to AR 3 can display the previous datasets.

The driving module 540 is signally connected to the receiving module 530 . The driving module 540 includes (1,1) to (N,M) LED controlling sets to control the (1,1) to (N,M) LED areas, respectively, and each of the (1,1) to (N,M) LED controlling sets includes a PWM controller 542 and a decoder 543 .

As shown in FIGS. 2 , (1,1) to (2,2) LED controlling sets CN 0 to CN 3 are used to control the (1,1) to (2,2) LED areas LAR 0 to LAR 3 , respectively. Each of the (1,1) to (2,2) LED controlling sets LAR 0 to LAR 3 includes a local memory 541 to store the PWM duty ratios of the current datasets from the receiving module 530 . Once the PWM duty datasets are written to the local memory 541 , the (1,1) to (2,2) LED areas LAR 0 to LAR 3 can continuously display by local control from the stored PWM duty ratios by self-scanning independently.

Precisely, in order to increase the update rate, improve the system stability and reduce the components of the LED panel 200 , data transmission and frame scanning are conducted simultaneously with VGA signal, by laminating area address with datasets (previous datasets and current datasets), each of the (1,1) to (2,2) LED areas LAR 0 to LAR 3 can judge whether the datasets is belong thereto and store the datasets into the local memory 541 . Hence, the datasets of the frame is stored in the local memory 541 as the datasets are transmitted to each of the (1,1) to (2,2) LED areas LAR 0 to LAR 3 , and even if the transmission cable is removed, the frame stored previously can still be displayed. In other words, even though a specific row is lit up at a specific scanning time, the other rows of each of the (1,1) to (2,2) LED areas LAR 0 to LAR 3 will not stop displaying; instead, the other rows will still be lit up by the datasets in the local memory 541 which stores the previous datasets of the previous frame until the current datasets of the current frame are completely received, and then the current frame will be displayed. Hence, after completely receiving the previous datasets of the previous frame, each of the (1,1) to (2,2) LED areas LAR 0 to LAR 3 will scan and update itself, and even if the size of the LED area in other embodiments is increased, the technique can still be used. However, in a conventional technique, only a specific row is lit up at a specific scanning time while the other rows are dark, and high update rate is required. Therefore, compared to the conventional technique, lower update rate can be used in the present disclosure, and the system stability thereof is increased.

In the LED panel controlling method 100 , the current datasets of the (n,m) area are transmitted only when the current datasets thereof are different from the previous datasets thereof. Hence, whether the (1,1) to (N,M) areas of the current frame belonging to still or motion can be detected. If it is motion, the present datasets are transmitted to the LED area for refreshing display; otherwise, the process is skipped. The present datasets can be sent to the relative LED area with the area address through SPI. Since the still LED area will accumulate the errors during a period of time, all of the LED areas are forced to refresh per one second.

In the controlling step S 05 , the (1,1)_(1,1) controlling sequence is sent to control the (1,1) LED row LRW 0 . For gray level control, a time stay control for MSB to LSB with various clock periods is used. First, the MSB of the PWM duty ratios of the (1,1) LED row LRW 0 with staying 4096 clocks are sent. A 4 to 1 MUX (not shown) selects 4096 and compares a counter (not shown). The counter is counting from 0 to 4096 per cycle. When its counting value arrived at 4096 , the counting value resets to zero. At the same time, a pulse is sent to the decoder 552 , and the decoder 552 can be a 4-to-16 decoder. The decoder 542 changes the active line from the (1,1) LED row LRW 0 to the (2,1) LED row LRW 1 . All MSB of PWM duty ratios for the (1,1) to (6,1) LED rows LRW 0 to LRW 5 can be sent. After that, the 4 to 1 MUX selects 2048 for the 2nd MSB control, and then 1024 can be selected. Following this schedule, the LSB is controlled with 512 clocks for scanning the (1,1) to (6,1) LED rows LRW 0 to LRW 5 . After all PWM duty ratios are scanned completely, it is repeated to read the PWM duty ratios from the local memory 541 and scan the PWM duty ratios to the LED panel 200 again without the need of waiting the datasets from the transmitting module 520 . Therefore, high brightness for LED display with local scanning can be completed, and the clock frequency of the transmitter does not require very high speed.

Although the present disclosure has been described in considerable detail with reference to certain embodiments thereof, other embodiments are possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein.

It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present disclosure without departing from the scope or spirit of the disclosure. In view of the foregoing, it is intended that the present disclosure covers modifications and variations of this disclosure provided they fall within the scope of the following claims.