Memory unit with adaptive clamping voltage scheme and calibration scheme for multi-level neural network based computing-in-memory applications and computing method thereof

The present disclosure relates to a memory unit and a computing method thereof. More particularly, the present disclosure relates to a memory unit with an adaptive clamping voltage scheme and a calibration scheme for a plurality of multi-level neural network based computing-in-memory applications and a computing method thereof.

In these years, due to the industrial growth of mobile device, medical electrical equipment, portable storage, etc., requirement of memory with low power, high speed and high density is increased. Computation-in-Memory (CIM) is a promising solution to improve the energy efficiency of multiply-accumulate (MAC) operations for AI chips, and multiple-bit convolutional neural network (CNN) is required for high inference accuracy in many applications.

Using non-volatile memory for CIM can save time from repeatedly writing weights to memory. In addition, in order to increase the operation speed, the amount of operation information needs to be increased in one operation cycle. However, increasing the amount of information will affect each other and cause incorrect results. Therefore, how to increase the amount of computing information and eliminate the influence between information in one cycle is one of the challenges we face.

In a conventional technology, to generate multi-bit input need multiple operation cycles. In addition, the conventional technology accumulates the current of multiple memories on the bit line, and the bit line will have high-impedance and low-impedance currents. The result of currents will overlap and then send it to the sense amplifier for reading, so that the overlapping part will cause an error. Therefore, a memory unit with an adaptive clamping voltage scheme and a calibration scheme for a plurality of multi-level neural network based computing-in-memory applications and a computing method thereof having the features of reducing the power consumption and improving the accuracy of the result are commercially desirable.

According to one aspect of the present disclosure, a memory unit with an adaptive clamping voltage scheme and a calibration scheme for a plurality of multi-level neural network based computing-in-memory applications is controlled by a word line, a reference voltage and a bit-line clamping voltage. The memory unit with the adaptive clamping voltage scheme and the calibration scheme for the multi-level neural network based computing-in-memory applications includes a non-volatile memory cell, a source line, a bit line and a clamping module. The non-volatile memory cell is controlled by the word line and stores a weight. The source line is electrically connected to one end of the non-volatile memory cell. The bit line is electrically connected to another end of the non-volatile memory cell and has a bit-line current. The clamping module is electrically connected to the non-volatile memory cell via the bit line and controlled by the reference voltage and the bit-line clamping voltage. The clamping module includes a clamping transistor, a cell detector and a clamping control circuit. The clamping transistor is electrically connected to the bit line. The bit-line current is flowed through the clamping transistor, and the clamping transistor is controlled by the bit-line clamping voltage to adjust the bit-line current. The cell detector is electrically connected to the clamping transistor. The cell detector is configured to detect the bit-line current to generate a comparison output according to the reference voltage. The clamping control circuit is electrically connected between the clamping transistor and the cell detector. The clamping control circuit switches the clamping transistor according to the comparison output and the bit-line clamping voltage. When the clamping transistor is turned on by the clamping control circuit, the bit-line current is corresponding to the bit-line clamping voltage multiplied by the weight.

According to another aspect of the present disclosure, a memory unit with an adaptive clamping voltage scheme and a calibration scheme for a plurality of multi-level neural network based computing-in-memory applications is controlled by a word line, a reference voltage and a bit-line clamping voltage. The memory unit with the adaptive clamping voltage scheme and the calibration scheme for the multi-level neural network based computing-in-memory applications includes two non-volatile memory cells, a source line, two bit lines and two clamping modules. The two non-volatile memory cells are controlled by the word line and storing two weights, respectively. The source line (SL) is electrically connected to one end of each of the two non-volatile memory cells. Each of the two bit lines is electrically connected to another end of each of the two non-volatile memory cells, and each of the two bit lines has a bit-line current. The two clamping modules are electrically connected to the two non-volatile memory cells via the two bit lines, respectively. The two clamping modules are controlled by the reference voltage and the bit-line clamping voltage. Each of the two clamping modules includes a clamping transistor, a cell detector and a clamping control circuit. The clamping transistor is electrically connected to one of the two bit lines. The bit-line current is flowed through the clamping transistor, and the clamping transistor is controlled by the bit-line clamping voltage to adjust the bit-line current. The cell detector is electrically connected to the clamping transistor. The cell detector is configured to detect the bit-line current to generate a comparison output according to the reference voltage. The clamping control circuit is electrically connected between the clamping transistor and the cell detector. The clamping control circuit switches the clamping transistor according to the comparison output and the bit-line clamping voltage. When the clamping transistor is turned on by the clamping control circuit, the bit-line currents of the two bit lines are corresponding to the bit-line clamping voltage multiplied by the two weights, respectively.

According to further another aspect of the present disclosure, a computing method of the memory unit with the adaptive clamping voltage scheme and the calibration scheme for the multi-level neural network based computing-in-memory applications includes performing a voltage level applying step and a computing step. The voltage level applying step includes applying a plurality of voltage levels to the reference voltage, the bit-line clamping voltage and the word line, respectively. The computing step includes driving the clamping transistor, the cell detector and the clamping control circuit to generate the bit-line current on the bit line according to the reference voltage and the bit-line clamping voltage. When the clamping transistor is turned on by the clamping control circuit, the bit-line current is corresponding to the bit-line clamping voltage multiplied by the weight.

The present disclosure can be more fully understood by reading the following detailed description of the embodiment, with reference made to the accompanying drawings as follows:

FIG. 1 shows a block diagram of a memory unit with an adaptive clamping voltage scheme and a calibration scheme for a plurality of multi-level neural network based computing-in-memory applications according to a first embodiment of the present disclosure.

FIG. 2 shows a block diagram of a memory unit with an adaptive clamping voltage scheme and a calibration scheme for a plurality of multi-level neural network based computing-in-memory applications according to a second embodiment of the present disclosure.

FIG. 3 shows timing diagrams of the memory unit of FIG. 2 , with the adaptive clamping voltage scheme.

FIG. 4 shows timing diagrams of the memory unit of FIG. 2 , with different resistance states (HRS/LRS).

FIG. 5 shows a schematic view of the memory unit of FIG. 2 , with the calibration scheme.

FIG. 6 shows a flow chart of a computing method of a memory unit with an adaptive clamping voltage scheme and a calibration scheme for a plurality of multi-level neural network based computing-in-memory applications according to a third embodiment of the present disclosure.

FIG. 7 shows a flow chart of a computing method of a memory unit with an adaptive clamping voltage scheme and a calibration scheme for a plurality of multi-level neural network based computing-in-memory applications according to a fourth embodiment of the present disclosure.

The embodiment will be described with the drawings. For clarity, some practical details will be described below. However, it should be noted that the present disclosure should not be limited by the practical details, that is, in some embodiment, the practical details is unnecessary. In addition, for simplifying the drawings, some conventional structures and elements will be simply illustrated, and repeated elements may be represented by the same labels.

It will be understood that when an element (or device) is referred to as be “connected to” another element, it can be directly connected to the other element, or it can be indirectly connected to the other element, that is, intervening elements may be present. In contrast, when an element is referred to as be “directly connected to” another element, there are no intervening elements present. In addition, the terms first, second, third, etc. are used herein to describe various elements or components, these elements or components should not be limited by these terms. Consequently, a first element or component discussed below could be termed a second element or component.

Before describing any embodiments in detail, some terms used in the following are described. A voltage level of “1” represents that the voltage is equal to a power supply voltage VDD. The voltage level of “0” represents that the voltage is equal to a ground voltage GND. A PMOS transistor and an NMOS transistor represent a P-type MOS transistor and an N-type MOS transistor, respectively. Each transistor has a source, a drain and a gate.

Please refer to FIG. 1 . FIG. 1 shows a block diagram of a memory unit 100 with an adaptive clamping voltage scheme and a calibration scheme for a plurality of multi-level neural network based computing-in-memory applications according to a first embodiment of the present disclosure. The memory unit 100 with the adaptive clamping voltage scheme and the calibration scheme for the multi-level neural network based computing-in-memory applications is controlled by a word line WL[i], a reference voltage V REF and a bit-line clamping voltage V BLC , and includes a non-volatile memory cell 110 , a source line SL[i], a bit line BL[i] and a clamping module 120 .

The non-volatile memory cell 110 is controlled by the word line WL[i] and stores a weight W[i]. The source line SL[i] is electrically connected to one end of the non-volatile memory cell 110 . The bit line BL[i] is electrically connected to another end of the non-volatile memory cell 110 and has a bit-line current I BL[i] and a bit-line voltage V BL[i] . The bit-line current I BL[i] represents a current flowed through the bit line BL[i]. The bit-line voltage V BL[i] represents a voltage level of the bit line BL[i]. The clamping module 120 is electrically connected to the non-volatile memory cell 110 via the bit line BL[i] and controlled by the reference voltage V REF and the bit-line clamping voltage V BLC . The clamping module 120 includes a clamping transistor Ni, a cell detector 122 and a clamping control circuit 124 . The clamping transistor Ni is electrically connected to the bit line BL[i]. The bit-line current I BL[i] is flowed through the clamping transistor Ni, and the clamping transistor Ni is controlled by the bit-line clamping voltage V BLC to adjust the bit-line current I BL[i] . The cell detector 122 is electrically connected to the clamping transistor Ni. The cell detector 122 is configured to detect the bit-line current I BL[i] to generate a comparison output CO according to the reference voltage V REF . The clamping control circuit 124 is electrically connected between the clamping transistor Ni and the cell detector 122 . The clamping control circuit 124 switches the clamping transistor Ni according to the comparison output CO and the bit-line clamping voltage V BLC . When the clamping transistor Ni is turned on by the clamping control circuit 124 , the bit-line current I BL[i] is corresponding to the bit-line clamping voltage V BLC multiplied by the weight W[i]. In other words, the bit-line current I BL[i] is corresponding to the bit-line voltage V BL[i] multiplied by the weight W[i]. “i” is an integer which is greater than or equal to 0. Therefore, the memory unit 100 with the adaptive clamping voltage scheme and the calibration scheme for the multi-level neural network based computing-in-memory applications of the present disclosure utilizes different bit-line clamping voltages V BLC on the non-volatile memory cell 110 to generate different bit-line currents I BL[i] so as to increase the number of input bits in one operating cycle and improve the results which affect each other after accumulating multiple memory cells.

Please refer to FIG. 2 . FIG. 2 shows a block diagram of a memory unit 100 a with an adaptive clamping voltage scheme and a calibration scheme for a plurality of multi-level neural network based computing-in-memory applications according to a second embodiment of the present disclosure. The memory unit 100 a with the adaptive clamping voltage scheme and the calibration scheme for the multi-level neural network based computing-in-memory applications is controlled by a plurality of word lines (e.g., WL[ 0 ], WL[ 1 ], WL[ 2 ]), a reference voltage V REF and a bit-line clamping voltage V BLC , and includes a plurality of non-volatile memory cells 110 , a source line SL[ 0 ], two bit lines BL[ 0 ], BL[ 1 ], a first transmission gate G 1 , a second transmission gate G 2 , a third transmission gate G 3 and two clamping modules 120 a , 120 b.

Two of the non-volatile memory cells 110 are controlled by the word line WL[ 0 ]. The two of the non-volatile memory cells 110 store two weights W[ 0 ], W[ 1 ], respectively. In detail, each of the non-volatile memory cells 110 includes a transistor and a resistive element. The resistive element is electrically connected to one of the two bit lines BL[ 0 ], BL[ 1 ] and stores one of the two weights W[ 0 ], W[ 1 ]. The resistive element of each of the non-volatile memory cells 110 is in one of a high resistance state (HRS) and a low resistance state (LRS). The transistor is electrically connected between the resistive element and the source line SL[ 0 ]. The transistor is the NMOS transistor.

The source line SL[ 0 ] is electrically connected to one end of each of the two non-volatile memory cells 110 , and the two non-volatile memory cells 110 are connected to one of the word lines (e.g., WL[ 0 ]). The source line SL[ 0 ] is coupled to the ground voltage VSS via the second transmission gate G 2 .

Each of the two bit lines BL[ 0 ], BL[ 1 ] is electrically connected to another end of each of the two non-volatile memory cells 110 , and each of the two bit lines BL[ 0 ], BL[ 1 ] has a bit-line current (i.e., one of I BL[0] , I BL[1] ). The voltage level (i.e., one of the bit-line voltages V BL[0] , V BL[1] ) of each of the two bit lines BL[ 0 ], BL[ 1 ] is smaller than the power supply voltage VDD.

The first transmission gate G 1 is electrically connected between one end of one of the two non-volatile memory cells 110 and one of the two clamping modules 120 a , 120 b . The second transmission gate G 2 is electrically connected between another end of the one of the two non-volatile memory cells 110 and the ground voltage VSS. In other words, the second transmission gate G 2 is electrically connected between the source line SL[ 0 ] and the ground voltage VSS. The third transmission gate G 3 is electrically connected between one end of another of the two non-volatile memory cells 110 and another of the two clamping modules 120 a , 120 b . The first transmission gate G 1 , the second transmission gate G 2 and the third transmission gate G 3 are controlled by a pass enable signal YMUX. Each of the first transmission gate G 1 , the second transmission gate G 2 and the third transmission gate G 3 is the NMOS transistor.

The two clamping modules 120 a , 120 b are electrically connected to the two non-volatile memory cells 110 via the two bit lines BL[ 0 ], BL[ 1 ], respectively. The two clamping modules 120 a , 120 b are controlled by the reference voltage V REF and the bit-line clamping voltage V BLC . The clamping module 120 a includes a clamping transistor N 0 , a cell detector 122 a and a clamping control circuit 124 a.

The clamping transistor N 0 is electrically connected to the bit line BL[ 0 ] via the first transmission gate G 1 . The bit-line current I BL[0] is flowed through the clamping transistor N 0 , and the clamping transistor N 0 is controlled by the bit-line clamping voltage V BLC to adjust the bit-line current I BL[0] . In detail, the clamping transistor N 0 is the NMOS transistor. The clamping transistor N 0 has a clamping gate, a clamping drain and a clamping source. The clamping gate is coupled to the clamping control circuit 124 a . The clamping drain is coupled to a detecting node PG 0 , and the clamping source is coupled to the bit line BL[ 0 ] via the first transmission gate G 1 .

The cell detector 122 a is electrically connected to the clamping transistor N 0 . The cell detector 122 a is configured to detect the bit-line current I BL[0] to generate a comparison output CO according to the reference voltage V REF . In detail, the cell detector 122 a includes a detecting transistor PO and a comparator CP. The detecting transistor PO is electrically connected between the clamping transistor N 0 and the power supply voltage VDD. The detecting transistor PO is electrically connected to the clamping transistor N 0 via a detecting node PG 0 . In other words, the detecting node PG 0 is connected between the comparator CP and the detecting transistor PO. The detecting transistor PO has a detecting gate, a detecting drain and a detecting source. The detecting gate is coupled to the detecting drain. The detecting drain is coupled to the detecting node PG 0 , and the detecting source is coupled to the power supply voltage VDD. The detecting transistor PO is the PMOS transistor. In addition, the comparator CP is electrically connected between the detecting node PG 0 and the clamping control circuit 124 a . The comparator CP generates the comparison output CO by comparing a voltage level of the detecting node PG 0 with the reference voltage V REF . The comparator CP may be a sense amplifier.

The clamping control circuit 124 a is electrically connected between the clamping transistor N 0 and the cell detector 122 a . The clamping control circuit 124 a switches the clamping transistor N 0 according to the comparison output CO and the bit-line clamping voltage V BLC . When the clamping transistor N 0 is turned on by the clamping control circuit 124 a , the bit-line current I BL[0] of the bit line BL[ 0 ] is corresponding to the bit-line clamping voltage V BLC multiplied by the weight W[ 0 ]. The bit-line current I BL[0] (I BL[i] with i=0) can be described as follows:

I BL[i] =V BLC ×W [ i ]= V BL[i] ×W [ i ]=( k×I HRS ) or ( k×I LRS ), k= 0,1, . . . n, i= 0  (1).

In detail, the clamping control circuit 124 a includes a two-terminal switching element SW 0 and a clamping control transistor DL-ZT 0 . The two-terminal switching element SW 0 is electrically connected between the bit-line clamping voltage V BLC and the clamping transistor N 0 . The two-terminal switching element SW 0 is controlled by the comparison output CO. The clamping control transistor DL-ZT 0 is electrically connected to the two-terminal switching element SW 0 . The clamping control transistor DL-ZT 0 is switched by the comparison output CO. The clamping control transistor DL-ZT 0 has a control gate, a control drain and a control source. The control gate is coupled to the comparison output CO. The control drain is coupled to the clamping gate of the clamping transistor N 0 . The control source is coupled to the ground voltage VSS. The clamping control transistor DL-ZT 0 is the NMOS transistor.

Similarly, the clamping module 120 b includes a clamping transistor N 1 , a cell detector 122 b and a clamping control circuit 124 b . The detail of the clamping transistor N 1 , the cell detector 122 b and the clamping control circuit 124 b of the clamping module 120 b is the same as the clamping transistor N 0 , the cell detector 122 a and the clamping control circuit 124 a of the clamping module 120 a , and will not be described again herein.

Please refer to FIGS. 2 and 3 . FIG. 3 shows timing diagrams of the memory unit 100 a of FIG. 2 , with the adaptive clamping voltage scheme. “CLK” represents a clock signal. “Level1” and “Level2” represent different bit-line clamping voltages V BLC , respectively, and “Input_multilevel” represents that the different bit-line clamping voltages V BLC have multilevel voltages. The adaptive clamping voltage scheme is to utilize different bit-line clamping voltages V BLC on the non-volatile memory cell 110 to generate different bit-line currents I BL[i] , where i=0 or 1. Through different bit-line clamping voltages V BLC , different cross voltages can be generated on the non-volatile memory cell 110 . The architecture of the memory unit 100 a of the present disclosure can generate different currents without using multiple memory cells, thereby effectively improving the utilization rate of the memory cells. The improved utilization rate can also reduce the power consumption caused by the large current accumulated on the bit line BL[i].

Please refer to FIGS. 2 and 4 . FIG. 4 shows timing diagrams of the memory unit 100 a of FIG. 2 , with different resistance states. When the non-volatile memory cell 110 is in the HRS with i being 0, the bit-line current I BL[0] is low, and the voltage level of the detecting node PG 0 is high. When the non-volatile memory cell 110 is in LRS with i being 0, the bit-line current I BL[0] is high, and the voltage level of the detecting node PG 0 is low. Moreover, when the non-volatile memory cell 110 is in the HRS with i being 1, the bit-line current I BL[1] is low, and the voltage level of the detecting node PG 1 is high. When the non-volatile memory cell 110 is in LRS with i being 1, the bit-line current I BL[1] is high, and the voltage level of the detecting node PG 1 is low.

Please refer to FIGS. 2 and 5 . FIG. 5 shows a schematic view of the memory unit 100 a of FIG. 2 , with the calibration scheme. “NTC” and “TC” represent a non-target cell and a target cell, respectively. “Column MUX” represents a set of the first transmission gate G 1 and the third transmission gate G 3 . The calibration scheme is to utilize non-target resistance cancellation on one of the bit lines BL[ 0 ], BL[ 1 ] by one of the cell detectors 122 a , 122 b to eliminate the non-target resistance current. In other words, the calibration scheme is to eliminate the influence between information by blocking the non-target resistance current. After blocking, the accumulation results of the non-volatile memory cells 110 are only corresponding to the target resistance current. The accumulation results can be achieved on one of the bit lines BL[ 0 ], BL[ 1 ] with the linear target resistance current and minimum impact between data. The cell detectors 122 a , 122 b are used to detect the bit lines BL[ 0 ], BL[ 1 ], respectively. The comparison outputs CO of the cell detectors 122 a , 122 b are used to control the clamping control circuit 124 a , 124 b , respectively. If the detection result of the non-volatile memory cell 110 is a target resistance (i.e., the target cell TC), the clamping control circuit 124 b operates normally. If the detection result of the non-volatile memory cell 110 is a non-target resistance (i.e., the non-target cell NTC), the clamping transistor N 0 is turned off by the clamping control circuit 124 a . A current with only the target resistance can be obtained, and a linear result with the target resistance current is generated on each of the bit lines BL[ 0 ], BL[ 1 ]. Therefore, the memory unit 100 a with the adaptive clamping voltage scheme and the calibration scheme for the multi-level neural network based computing-in-memory applications of the present disclosure utilizes different bit-line clamping voltages V BLC on the non-volatile memory cell 110 to generate different bit-line currents (e.g., any one of I BL[0] and I BL[1] has different values) so as to increase the number of input bits in one operating cycle and improve the results which affect each other after accumulating multiple memory cells.

Please refer to FIGS. 1 and 6 . FIG. 6 shows a flow chart of a computing method 200 of a memory unit 100 with an adaptive clamping voltage scheme and a calibration scheme for a plurality of multi-level neural network based computing-in-memory applications according to a third embodiment of the present disclosure. The computing method 200 includes performing a voltage level applying step S 02 and a computing step S 04 . The voltage level applying step S 02 includes applying a plurality of voltage levels to the reference voltage V REF , the bit-line clamping voltage V BLC and the word line WL[i], respectively. The computing step S 04 includes driving the clamping transistor Ni, the cell detector 122 and the clamping control circuit 124 to generate the bit-line current I BL[i] on the bit line BL[i] according to the reference voltage V REF and the bit-line clamping voltage V BLC . When the clamping transistor Ni is turned on by the clamping control circuit 124 , the bit-line current I BL[i] is corresponding to the bit-line clamping voltage V BLC multiplied by the weight W[i]. Therefore, the computing method 200 of the present disclosure utilizes different bit-line clamping voltages V BLC on the non-volatile memory cell 110 to generate different bit-line currents I BL[i] so as to increase the number of input bits in one operating cycle and improve the results which affect each other after accumulating multiple memory cells.

Please refer to FIGS. 2 and 7 . FIG. 7 shows a flow chart of a computing method 200 a of a memory unit 100 a with an adaptive clamping voltage scheme and a calibration scheme for a plurality of multi-level neural network based computing-in-memory applications according to a fourth embodiment of the present disclosure. The computing method 200 a includes performing a voltage level applying step S 12 and a computing step S 14 .

The voltage level applying step S 12 includes applying a plurality of voltage levels to the reference voltage V REF , the bit-line clamping voltage V BLC and the word lines (e.g., WL[ 0 ], WL[ 1 ], WL[ 2 ]), respectively. In detail, the voltage level applying step S 12 includes performing an input voltage applying step S 122 , a word-line switching step S 124 and a bit-line developing step S 126 . The input voltage applying step S 122 includes applying the bit-line clamping voltage V BLC which is regarded as an input voltage of accumulation. The word-line switching step S 124 includes turning on the word lines by applying the voltage level (e.g., the power supply voltage VDD) to the word lines. The bit-line developing step S 126 includes developing the bit line (e.g., BL[ 0 ] or BL[ 1 ]) during a developing time period.

The computing step S 14 includes driving the clamping transistors N 0 , N 1 , the cell detectors 122 a , 122 b and the clamping control circuits 124 a , 124 b to generate the bit-line currents I BL[0] , I BL[1] on the bit lines BL[ 0 ], BL[ 1 ] according to the reference voltage V REF and the bit-line clamping voltage V BLC . When the clamping transistor N 1 is turned on by the clamping control circuit 124 b , the bit-line current I BL[1] is corresponding to the bit-line clamping voltage V BLC multiplied by the weight W[ 1 ].

In detail, the computing step S 14 includes performing a cell detector checking step S 142 , a first clamping step S 144 , a second clamping step S 146 and a convolutional operating step S 148 .

The cell detector checking step S 142 includes enabling the cell detectors 122 a , 122 b to check the bit-line currents I BL[0] , I BL[1] to generate the comparison output CO according to the reference voltage V REF . A comparator CP of each of the cell detectors 122 a , 112 b is driven to generate the comparison output CO by comparing a voltage level of a detecting node (e.g., PG 0 or PG 1 ) of each of the cell detectors 122 a , 122 b with the reference voltage V REF .

When a voltage level of the comparison output CO is high, the first clamping step S 144 is performed. In the first clamping step S 144 , a two-terminal switching element SW 0 of the clamping control circuit 124 a is turned off. A clamping control transistor DL-ZT 0 of the clamping control circuit 124 a is turned on to pull down a voltage level of a clamping gate of the clamping transistor N 0 , and the clamping transistor N 0 is not controlled by the bit-line clamping voltage V BLC . In other words, when the clamping transistor N 0 is turned off by the clamping control circuit 124 a , the bit-line current I BL[0] is set to zero.

When the voltage level of the comparison output CO is low, the second clamping step S 146 is performed. In the second clamping step S 146 , a two-terminal switching element SW 1 of the clamping control circuit 124 b is turned on, and a clamping control transistor DL-ZT 1 of the clamping control circuit 124 b is turned off. The clamping transistor N 1 is controlled by the bit-line clamping voltage V BLC to adjust the bit-line current I BL[1] . In response to determining that the bit-line clamping voltage V BLC is changed, the bit-line current I BL[1] is changed.

The convolutional operating step S 148 includes performing a convolutional operation according to the bit-line clamping voltage V BLC and the weight W[ 1 ].

Therefore, the computing method 200 a of the present disclosure utilizes different bit-line clamping voltages V BLC on the non-volatile memory cell 110 to generate different bit-line currents (e.g., any one of I BL[0] and I BL[1] has different values) so as to increase the number of input bits in one operating cycle and improve the results which affect each other after accumulating multiple memory cells.

According to the aforementioned embodiments and examples, the advantages of the present disclosure are described as follows.

1. The memory unit with the adaptive clamping voltage scheme and the calibration scheme for the multi-level neural network based computing-in-memory applications and the computing method thereof of the present disclosure can generate different currents without using multiple memory cells, thereby effectively improving the utilization rate of the memory cells. The improved utilization rate can also reduce the power consumption caused by the large current accumulated on the bit line.

2. The memory unit with the adaptive clamping voltage scheme and the calibration scheme for the multi-level neural network based computing-in-memory applications and the computing method thereof of the present disclosure utilize different bit-line clamping voltages on the non-volatile memory cell to generate different bit-line currents so as to increase the number of input bits in one operating cycle and improve the results which affect each other after accumulating multiple memory cells.

Although the present disclosure has been described in considerable detail with reference to certain embodiments thereof, other embodiments are possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein.

It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present disclosure without departing from the scope or spirit of the disclosure. In view of the foregoing, it is intended that the present disclosure cover modifications and variations of this disclosure provided they fall within the scope of the following claims.