Output stage circuit

This application claims the priority benefit of China application no. 202010278121.8, filed on Apr. 10, 2020. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.

The disclosure relates to an output stage circuit, and particularly relates to an output stage circuit capable of avoiding or reducing damage resulting from voltage overshoot.

When the structure of a chip is designed, characteristics of manufactured components may be different due to different semiconductor processes. For example, transistors produced by different semiconductor processes may have different voltage withstand levels. In addition, based on technical specifications and application limitations and advances in semiconductor technology, an input/output signal voltage used in a currently circuit is designed in accordance with rules of an adopted interface. For example, the input/output signal voltage is required to adopt a 3.3V voltage signal to be compatible with a communication protocol of a USB 2.0 interface. In general, if a currently common semiconductor process (for example, a semiconductor process of 28 nm, 16 nm, etc.) is adopted to design a relevant circuit structure for inputting and outputting signals, withstand voltages of available transistors cannot directly match the voltage specification of the input/output signal limited by some interface protocols. For example, some transistors that may only withstand 1.8 V and cannot directly accept the input/output signal with 3.3V voltage, so it is necessary to design an output stage circuit that may withstand the input/output signal with 3.3V voltage.

However, when the output stage circuit is actually used, since there must be a phenomenon of voltage overshoot of the input/output signal, the withstand voltages of some components of the output stage circuit may exceed designed predetermined values, which reduces a service life of the output stage circuit, or even directly burns out a part of components of the output stage circuit or other circuits. Therefore, how to use transistors with the lower withstand voltage to design a reliable output stage circuit to implement transmission of higher voltage signals is currently one of the directions for further research.

The invention is directed to an output stage circuit, the output stage circuit dynamically adjusts a bias voltage according to a value of an output voltage, so that three-terminal voltages of each transistor of an amplifier circuit do not exceed a withstand voltage of the transistor, thereby avoiding or reducing the output stage circuit from being damaged by voltage overshoot and shortening a service life.

The invention provides an output stage circuit comprising a bias voltage generator, a first amplifier circuit and a second amplifier circuit. The bias voltage generator is coupled to an output terminal of the output stage circuit to generate a bias voltage according to an output voltage of the output terminal. The first amplifier circuit is coupled to the output terminal of the output stage circuit, a first power supply terminal and the bias voltage generator. The first amplifier circuit receives a first pre-driving signal, a first predetermined voltage and the bias voltage. According to the first pre-driving signal, the first predetermined voltage and the bias voltage, the first amplifier circuit determines whether to turn on the first amplifier circuit to transmit a first voltage from the first power supply terminal to the output terminal to serve as the output voltage. The second amplifier circuit is coupled to the output terminal, a second power supply terminal and the bias voltage generator. The second amplifier circuit receives a second pre-driving signal, a second predetermined voltage and the bias voltage. According to the second pre-driving signal, the second predetermined voltage and the bias voltage, the second amplifier circuit determines whether to turn on the second amplifier circuit to transmit a second voltage from the second power supply terminal to the output terminal to serve as the output voltage.

Based on the above description, the output stage circuit of the embodiment of the invention is implemented by an amplifier circuit structure of at least three tiers, and combined with a floating bias voltage to prevent three-terminal voltages of each transistor from exceeding a withstand voltage of the transistor. Namely, the bias voltage generator of the output stage circuit dynamically adjusts the bias voltage according to the value of the output voltage. When the value of the output voltage is higher, a value of the bias voltage is increased accordingly. Correspondingly, when the value of the output voltage is lower, the value of the bias voltage is decreased accordingly. In this way, the three-terminal voltages of a part of transistors of the amplifier circuit do not exceed the respective withstand voltages of the part of the transistors due to the dynamic adjustment of the bias voltage, thereby avoiding or reducing the output stage circuit from being damaged by voltage overshoot and shortening the service life.

To make the aforementioned more comprehensible, several embodiments accompanied with drawings are described in detail as follows.

The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

FIG. 1 is a circuit diagram of an output stage circuit 100 .

FIG. 2 is a schematic diagram of an output stage circuit 200 according to an embodiment of the invention.

FIG. 3 is a detailed circuit diagram of the output stage circuit 200 according to an embodiment of the invention.

FIG. 4 is a circuit diagram of a bias voltage generator 210 in FIG. 2 .

FIG. 5 is a waveform diagram of an output voltage and a bias voltage according to an embodiment of the invention.

FIG. 1 is a circuit diagram of an output stage circuit 100 . The output stage circuit 100 in FIG. 1 comprises a two-tier amplifier circuit 110 composed of transistors P 1 , P 2 , N 1 and N 2 , and two pre-drivers 120 and 130 . It is assumed that a withstand voltage of each transistor of the output stage circuit 100 is 1.8V due to limitation of a semiconductor process, and a chip using the output stage circuit 100 needs to transmit a data signal with a maximum voltage of 3.3V at an output terminal Nout of the output stage circuit 100 due to a transmission protocol of a specific interface. The transistors P 1 and P 2 of the embodiment are both P-type metal-oxide-semiconductor field-effect transistors (MOSFETs), and the transistors N 1 and N 2 are both N-type MOSFETs.

The pre-driver 120 receives a first control signal Pctl and pre-drives the first control signal Pctl, and transmits the pre-driven first control signal Pctl to a control terminal (a gate) of the transistor P 1 . The pre-driver 130 receives a second control signal Nctl and pre-drives the second control signal Nctl, and transmits the pre-driven second control signal Nctl to a control terminal (a gate) of the transistor N 1 . In other words, the first control signal Pctl controls whether to turn on the transistor P 1 through the pre-driver 120 ; and the second control signal Nctl controls whether to turn on the transistor N 1 through the pre-driver 130 . Control terminals (gates) of the transistors P 2 and N 2 receive a voltage Vmid. In the embodiment, a voltage value of the voltage Vmid is one half of a voltage value of a first voltage Vcc. In this way, in general, the transistors P 2 and N 2 may protect each of the transistors P 1 -P 2 , N 1 -N 2 in the two-tier amplifier circuit 110 from being damaged by a voltage signal of 3.3V.

However, in practical applications, when a voltage at the output terminal Nout is interfered, for example, jittered due to an interference of a voltage overshoot effect, the circuit structure of the output stage circuit 100 may be easily damaged. For example, in the case where a host end and a device end are both configured with a power supply for data transmission, the output stage circuits of the host end and the device end need to withstand a larger withstand voltage, so that the output stage circuit 100 may be easily damaged; or in the case of adopting a related circuit (such as a transmission driver) of a universal serial bus (USB) 2.0 DP/DM interface, the output stage circuit 100 of FIG. 1 may be easily damaged due to the voltage overshoot effect. The reason for the damage of the output stage circuit 100 is that data transmission performed under a high speed mode of the USB 2.0 DP/DM interface requires that the voltage of the output terminal Nout of the output stage circuit 100 may be as low as −400 mV, and data transmission performed under a full speed mode requires that the voltage of the output terminal Nout of the output stage circuit 100 varies within a range from −500 mV to 3.6 V due to the possible voltage overshoot effect. If these conditions are satisfied, three-terminal voltages of the transistors P 2 and N 2 of the two-tier amplifier circuit 110 may severely exceed the respective withstand voltages (such as 1.8 V) of the transistors P 2 and N 2 , which results in failure or even burnout of the transistors P 2 and N 2 , and affects a service life of the output stage circuit 100 .

Therefore, in the embodiment of the invention, an amplifier circuit structure of at least three tiers is adopted to combine with a floating bias voltage, so that the three-terminal voltages of each transistor of the output stage circuit does not exceed the withstand voltage of the transistor, and each transistor may withstand the voltage of voltage overshoot or undershoot of the output voltage, so as to avoid or reduce the output stage circuit from being damaged by the voltage overshoot, and shortening its service life. An embodiment is provided below for further description.

FIG. 2 is a schematic diagram of an output stage circuit 200 according to an embodiment of the invention. The output stage circuit 200 of the embodiment may be applied to an input/output circuit of a transmission end (TX) using the USB 2.0 interface and having a full/low speed mode, and the output stage circuit 200 may be fabricated by using a 16 nm semiconductor process. Those skilled in the art may adjust an application interface and a transmission protocol applied to the output stage circuit 200 according to their needs, and may adopt other semiconductor processes, for example, semiconductor processes such as 12 nm, 10 nm, 8 nm, 7 nm, 5 nm, 3 nm, etc., to fabricate the output stage circuit 200 .

The output stage circuit 200 mainly comprises a bias voltage generator 210 , a first amplifier circuit 220 and a second amplifier circuit 230 . The output stage circuit 200 may further comprise a first pre-driver 240 and a second pre-driver 242 . The bias voltage generator 210 is coupled to the output terminal Nout of the output stage circuit 200 to generate a bias voltage Vbias according to an output voltage Vout of the output terminal Nout. The first amplifier circuit 220 is coupled to the output terminal Nout of the output stage circuit 200 , a first power supply terminal Nv 1 , the bias voltage generator 210 and the first pre-driver 240 . According to the pre-driven first control signal Pctl, a first predetermined voltage Vmidp and the bias voltage Vbias, the first amplifier circuit 220 determines whether to turn on itself to transmit the first voltage Vcc of the first power supply terminal Nv 1 to the output terminal Nout to serve as the output voltage Vout. The first voltage Vcc of the embodiment may be a power supply voltage, for example, a power supply voltage of 3.3V. The second amplifier circuit 230 is coupled to the output terminal Nout of the output stage circuit 200 , a second power supply terminal Nv 2 , the bias voltage generator 210 and the second pre-driver 242 . According to the pre-driven second control signal Nctl, a second predetermined voltage Vmidn and the bias voltage Vbias, the second amplifier circuit 230 determines whether to turn on itself to transmit a second voltage Vss of the second power supply terminal Nv 2 to the output terminal Nout to serve as the output voltage Vout. The second voltage Vss of the embodiment may be a ground voltage. The first amplifier circuit 220 and the second amplifier circuit 230 respectively comprise at least three transistors connected in series, herein the number of transistors connected in series and comprised by the first amplifier circuit 220 or the second amplifier circuit 230 may be the same or different. Referring to FIG. 3 and FIG. 4 for a detailed circuit structure configuration of each component of the output stage circuit 200 .

In an embodiment of the invention, the series connection refers to among the P-type MOSFETs, for a first P-type MOSFET, a first terminal (a source) of the first P-type MOSFET is coupled to the first voltage Vcc, for a second P-type MOSFET to a penultimate P-type MOSFET, a first terminal (a source) of each P-type MOSFET is coupled to a second terminal (a drain) of a previous P-type MOSFET, and for the last P-type MOSFET, for the last P-type MOSFET, a second terminal (a drain) of the last P-type MOSFET is coupled to the output terminal Nout. The series connection also refers to among the N-type MOSFETs, for a first N-type MOSFET, a first terminal (a source) of the first N-type MOSFET is coupled to the second voltage Vss, for a second N-type MOSFET to a penultimate N-type MOSFET, a first terminal (a source) of each N-type MOSFET is coupled to a second terminal (a drain) of a previous N-type MOSFET, and for the last N-type MOSFET, a second terminal (a drain) of the last N-type MOSFET is coupled to the output terminal Nout.

FIG. 3 is a detailed circuit diagram of the output stage circuit 200 according to an embodiment of the invention. FIG. 3 mainly discloses a connection method of each of the transistors and a voltage value configuration of the first amplifier circuit 220 and the second amplifier circuit 230 . The first amplifier circuit 220 comprises a first switch transistor, such as a transistor P 1 , at least one first stacked transistor, such as a transistor P 2 , and a first bias transistor, such as a transistor P 3 . The second amplifier circuit 230 comprises a second switch transistor, such as a transistor N 1 , at least one second stacked transistor, such as a transistor N 2 , and a second bias transistor, such as a transistor N 3 . In the embodiment, the transistors P 1 to P 3 are all P-type MOSFETs, and the transistors N 1 to N 3 are all N-type MOSFETs. In some embodiments, a resistor used for adjusting a bias voltage may be additionally added between the transistor P 3 and the output terminal Nout, and/or between the transistor N 3 and the output terminal Nout, so as to adjust an output impedance of the output stage circuit 200 .

A first terminal (a source) of the transistor P 1 is coupled to the first power supply terminal Nv 1 to receive the first voltage Vcc. A control terminal (a gate) of the transistor P 1 receives the pre-driven first control signal Pctl. The pre-driving operation is executed by the first pre-driver 240 , the first pre-driver 240 receives the first control signal Pctl and pre-drives the first control signal Pctl. Herein the pre-driving refers to that an upper threshold and a lower threshold of a voltage range of the first control signal Pctl are respectively raised. For example, for raising a lower threshold of the first control signal Pctl with a voltage range of [0 V,0.8 V], the first control signal Pctl of 0 V is pre-driven to 1.65 V; for raising an upper threshold of the first control signal Pctl with the voltage range of [0 V,0.8 V], the first control signal Pctl of 0.8 V is pre-driven to 3.3 V. After the pre-driving operation, the voltage range of [0 V,0.8 V] of the first control signal Pctl is raised to a voltage range of [1.65 V, 3.3 V]. According to an embodiment of the invention, the first pre-driver 240 may be a level shifter. The first pre-driver 240 receives the first control signal Pctl and pre-drives the first control signal Pctl, and transmits the pre-driven first control signal Pctl to the control terminal (the gate) of the transistor P 1 to control whether to turn on the transistor P 1 .

A control terminal (a gate) of the transistor P 2 receives the first predetermined voltage Vmidp, and a first terminal (a source) of the transistor P 2 is coupled to a second terminal (a drain) of the transistor P 1 . A first terminal (a source) of the transistor P 3 is coupled to a second terminal (a drain) of the transistor P 2 , a control terminal (a gate) of the transistor P 3 receives the bias voltage Vbias, and a second terminal (a drain) of the transistor P 3 is coupled to the output terminal Nout.

A first terminal (a source) of the transistor N 1 is coupled to the second power supply terminal Nv 2 to receive the second voltage Vss. A control terminal (a gate) of the transistor N 1 receives the pre-driven second control signal Nctl. The pre-driving operation is executed by the second pre-driver 242 . The second pre-driver 242 receives the second control signal Nctl and pre-drives the second control signal Nctl. The pre-driving refers that an upper threshold of a voltage range of the second control signal Nctl is raised, but a lower threshold of the voltage range of the second control signal Nctl is not changed. For example, the second control signal Nctl of 0 V is pre-driven, and the pre-driven second control signal Nctl is still 0 V. To raise an upper threshold of the second control signal Nctl with the voltage range of [0 V,0.8 V], the second control signal Nctl of 0.8 V is pre-driven, and the pre-driven second control signal Nctl is 1.65 V. As a result, the voltage range of [0 V,0.8 V] of the second control signal Nctl is raised to a voltage range of [0 V, 1.65 V] after the pre-driving operation. According to an embodiment of the invention, the second pre-driver 242 may also be a level shifter. In other words, the second pre-driver 242 receives the second control signal Nctl and pre-drives the second control signal Nctl, and transmits the pre-driven second control signal Nctl to the control terminal (the gate) of the transistor N 1 to control whether to turn on the transistor N 1 .

A control terminal (a gate) of the transistor N 2 receives the second predetermined voltage Vmidn, and a first terminal (a source) of the transistor N 2 is coupled to a second terminal (a drain) of the transistor N 1 . A first terminal (a source) of the transistor N 3 is coupled to a second terminal (a drain) of the transistor N 2 , a control terminal (a gate) of the transistor N 3 receives the bias voltage Vbias, and a second terminal (a drain) of the transistor N 3 is coupled to the output terminal Nout.

In particular, in the embodiment, one transistor P 2 is used as the at least one first stacked transistor, so that the first amplifier circuit 220 comprises at least three transistors connected in series. Those skilled in the art may increase a number of the first stacked transistors according to actual needs, as long as the control terminal (the gate) of each first stacked transistor receives the first predetermined voltage Vmidp, and the first stacked transistors are stacked with each other, so as to increase a voltage tolerance of the first amplifier circuit 220 . Correspondingly, in the embodiment, one transistor N 2 is used as the at least one second stacked transistor, and those skilled in the art may increase a number of the second stacked transistors according to actual needs, as long as the control terminal (the gate) of each second stacked transistor receives the second predetermined voltage Vmidn, and the second stacked transistors are stacked with each other, so as to increase a voltage tolerance of the second amplifier circuit 230 .

According to an embodiment of the invention, the cascaded connection of the at least one first stacked transistors refers to that among the P-type MOSFETs, for a first P-type MOSFET, the first terminal (the source) of the first P-type MOSFET is coupled to the second terminal (the drain) of the transistor P 1 , for the second P-type MOSFET to the penultimate P-type MOSFET, the first terminal (the source) of each P-type MOSFET is coupled to the second terminal (the drain) of the previous P-type MOSFET, and for a first P-type MOSFET, the second terminal (the drain) of the last P-type MOSFET is coupled to the first terminal (the source) of the transistor P 3 . The control terminals (the gates) of these P-type MOSFETs all receive the first predetermined voltage Vmidp. The cascaded connection of the at least one second stacked transistors refers to that among the N-type MOSFETs, for a first N-type MOSFET, the first terminal (the source) of the first N-type MOSFET is coupled to the second terminal (the drain) of the transistor N 1 , for the second N-type MOSFET to the penultimate N-type MOSFET, the first terminal (the source) of each N-type MOSFET is coupled to the second terminal (the drain) of the previous N-type MOSFET, and for the last N-type MOSFET, the second terminal (the drain) of the last N-type MOSFET is coupled to the output terminal Nout. The control terminals (the gates) of these N-type MOSFETs all receive the second predetermined voltage Vmidn.

The control terminals (the gates) of the transistors P 3 and N 3 receive the bias voltage Vbias, herein the voltage of the bias voltage Vbias changes as the voltage of the output voltage Vout changes. For example, when the output voltage Vout is 3.9 V, the bias voltage generator 210 controls the bias voltage Vbias to be 2.2 V, and when the output voltage Vout is −600 mV, the bias voltage generator 210 controls the bias voltage Vbias to be 1.0 V. In this way, the series connection structure of the transistors of the output stage circuit 200 may be effectively prevented from being damaged by the first voltage Vcc of 3.3 V or the output voltage Vout with a level range between −600 mV and 3.9V.

According to an exemplary embodiment of the invention, the first predetermined voltage Vmidp of the embodiment is a sum of a half value of the first voltage Vcc and a value of a floating voltage, for example, 0.1V, so that the first predetermined voltage Vmidp is 3.3 V/2+0.1 V=1.75 V. The second predetermined voltage Vmidn of the embodiment is a difference between a half value of the first voltage Vcc and the value of the floating voltage, so that the second predetermined voltage Vmidn is 3.3 V/2-0.1 V=1.55 V. A purpose of adding and subtracting the floating voltage to adjust the voltage values of the first predetermined voltage Vmidp and the second predetermined voltage Vmidn is to better protect the first stacked transistor (for example, the transistor P 2 ) and the second stacked transistor (for example, the transistor N 2 ) from damage. According to a secondary embodiment of the invention, both of the first predetermined voltage Vmidp and the second predetermined voltage Vmidn may be set to one half of the first voltage Vcc, so that the first predetermined voltage Vmidp and the second predetermined voltage Vmidn are both 3.3 V/2, i.e. 1.65V.

FIG. 4 is a circuit diagram of the bias voltage generator 210 in FIG. 2 . Referring to FIG. 4 , the bias voltage generator 210 of the embodiment comprises a first comparison voltage generating circuit 410 , a second comparison voltage generating circuit 420 , and a comparator 430 . The first comparison voltage generating circuit 410 divides the output voltage Vout into a first comparison voltage VRPD according to a predetermined ratio. In detail, the first comparison voltage generating circuit 410 comprises a first resistor R 1 and a second resistor R 2 . The first resistor R 1 and the second resistor R 2 form a voltage dividing circuit. A first terminal of the first resistor R 1 is coupled to the output voltage Vout, a first terminal of the second resistor R 2 is coupled to a second terminal of the first resistor R 1 to serve as an output terminal of the first comparison voltage generating circuit 410 , and a second terminal of the second resistor R 2 is coupled to the second power supply terminal Nv 2 . So that a relationship between the first comparison voltage VRPD at the output terminal of the first comparison voltage generating circuit 410 and the output voltage Vout is: VRPD=Vout×R 2 /(R 1 +R 2 ).×Vout.

Particularly, when the output stage circuit 200 is applied to a circuit compatible with the USB 2.0 interface standard, the first resistor R 1 and the second resistor R 2 may respectively directly make use of the 15 kΩ pull-down resistors necessary for the USB 2.0 interface. Therefore, in the embodiment of the invention, the circuit of the USB 2.0 interface is directly used to implement the first comparison voltage generating circuit 410 without additionally configuring two resistors. Herein, the ratio of the resistance values of the first resistor R 1 and the second resistor R 2 is a predetermined ratio, making the Vout:VRPD=1:0.56.

The second comparison voltage generating circuit 420 generates a second comparison voltage VM according to the output voltage Vout. In detail, the second comparison voltage generating circuit 420 comprises a third resistor R 3 , a fourth resistor R 4 , a diode 422 , a source follower 424 , and a protective transistor 426 . A first terminal of the third resistor R 3 receives a third voltage V 3 . The third voltage V 3 of the embodiment is one half of the first voltage Vcc. A first terminal of the fourth resistor R 4 is coupled to a second terminal of the third resistor R 3 to serve as an output terminal N 420 of the second comparison voltage generating circuit 420 . The output terminal N 420 of the second comparison voltage generating circuit 420 generates the second comparison voltage VM.

The diode 422 is implemented by a P-type transistor P 4 . A first terminal (a source) of the transistor P 4 serves as an anode of the diode 422 , and a second terminal (a drain) of the transistor P 4 is coupled to a control terminal (a gate) of the transistor P 4 to serve as a cathode of the diode 422 . The anode of the diode 422 is coupled to a second terminal of the fourth resistor R 4 , and the cathode of the diode 422 is coupled to the source follower 424 .

The source follower 424 is implemented by a P-type transistor P 5 . A first terminal (a source) of the transistor P 5 is coupled to the cathode of the diode 422 , and a second terminal (a drain) of the transistor P 5 is coupled to the second power supply terminal Nv 2 . The protective transistor 426 of the embodiment is implemented by an N-type transistor N 4 . A first terminal (a drain) of the transistor N 4 is coupled to a control terminal of the source follower 424 (a gate of the transistor P 5 ), a second terminal (a source) of the transistor N 4 is coupled to the output terminal Nout of the output stage circuit 200 to receive the output voltage Vout, and a control terminal (a gate) of the transistor N 4 is coupled to an output terminal N 430 of the comparator 430 .

A first terminal Ni 1 of the comparator 430 receives the first comparison voltage VRPD. A second terminal Ni 2 of the comparator 430 receives the second comparison voltage VM. The comparator 430 provides a larger one of the first comparison voltage VRPD and the second comparison voltage VM to the output terminal N 430 of the comparator 430 to serve as the bias voltage Vbias. The comparator 430 may be implemented by two P-type transistors P 6 and P 7 . A first terminal (a source) of the transistor P 6 is coupled to a first terminal (a source) of the transistor P 7 to serve as the output terminal N 430 of the comparator 430 . A second terminal (a drain) of the transistor P 6 is coupled to a control terminal (a gate) of the transistor P 7 to serve as the first terminal Ni 1 of the comparator 430 . A second terminal (a drain) of the transistor P 7 is coupled to a control terminal (a gate) of the transistor P 6 to serve as the second terminal Ni 2 of the comparator 430 .

Hereafter, take the predetermined ratio as an example of the ratio of the first resistance R 1 and the second resistance R 2 , with reference of FIG. 4 , to describe the operating principle of the bias voltage generator 210 . Those skilled may adjust the ratio of the first resistance R 1 and the second resistance R 2 to be other value according to their needs.

In the second comparison voltage generating circuit 420 shown in FIG. 4 , resistance values of the third resistor R 3 and the fourth resistor R 4 are the same, and the diode 422 generates a voltage drop Vth at its own two ends. When a voltage overshoot occurs and the voltage value of the output voltage Vout is 3.9V, a voltage value of the first comparison voltage VRPD generated by the first comparison voltage generating circuit 410 is about 2.2V, i.e., 3.9 V×0.56, the aforementioned predetermined ratio of the first resistor R 1 and the second resistor R 2 determines that the ratio between the first comparison voltage VRPD and the output voltage Vout is 0.56.

On the other hand, the transistors P 4 and P 5 of the second comparison voltage generating circuit 420 are turned off so that no current may flow from a terminal where the third voltage V 3 is formed to the second power supply terminal Nv 2 . In this way, the voltage value of the second comparison voltage VM is the same as the voltage value of the third voltage V 3 , which are both 1.65V. Therefore, the output terminal of the comparator 430 may generate the bias voltage Vbias equal to a voltage value of the first comparison voltage VRPD (2.2 V). In this way, three-terminal voltages of each transistor of the first amplifier circuit 220 and the second amplifier circuit 230 of FIG. 3 will not exceed 1.8 V.

Correspondingly, when a voltage undershoot occurs and the voltage value of the output voltage Vout is −600 mV, the voltage value of the first comparison voltage VRPD generated by the first comparison voltage generating circuit 410 is about −300 mV (−600 mV×0.56).

On the other hand, the transistors P 4 and P 5 of the second comparison voltage generating circuit 420 are turned on and no current may flow from the terminal where the third voltage V 3 is formed to the second power supply terminal Nv 2 . In this way, the voltage value of the second comparison voltage VM is a sum of the third voltage V 3 and the voltage drop Vth of the diode 422 (it is assumed that the voltage drop Vth is 0.35 V) divided by 2, which is about 1V, and an equation thereof is, (1.65 V+0.35 V)/2=1.0 V. Therefore, the output terminal of the comparator 430 may generate the bias voltage Vbias equal to the voltage value of the second comparison voltage VM (1.0V). In this way, three-terminal voltages of each transistor of the first amplifier circuit 220 and the second amplifier circuit 230 of FIG. 3 will not exceed 1.8 V.

FIG. 5 is a waveform diagram of the output voltage Vout and the bias voltage Vbias according to an embodiment of the invention. The waveform diagram of FIG. 5 is used for presenting operating characteristics of the bias voltage generator 210 in FIG. 2 to FIG. 4 . A horizontal axis of FIG. 5 represents time points, and a vertical axis of FIG. 5 represents voltage values. At a time point T 1 , when the output voltage Vout is −0.6 V (i.e., −600 mV), the bias voltage Vbias is about 1.0 V. At a time point T 2 , when the output voltage Vout is 3.9 V, the bias voltage Vbias is about 2.2 V.

In summary, the output stage circuit of the embodiment of the invention is implemented by an amplifier circuit structure of at least three tiers, and combined with a floating bias voltage to prevent the three-terminal voltages of each transistor from exceeding the withstand voltage of the transistor. Namely, the bias voltage generator of the output stage circuit dynamically adjusts the bias voltage according to the value of the output voltage. When the value of the output voltage is high, the value of the bias voltage is increased accordingly in a floating manner. Correspondingly, when the value of the output voltage is low, the value of the bias voltage is decreased accordingly in the floating manner. In this way, the three-terminal voltages of a part of the transistors in the amplifier circuit will not exceed the respective withstand voltages of the part of the transistors due to the floating bias voltage, thereby avoiding or reducing the output stage circuit from being damaged by voltage overshoot and shortening the service life thereof.

It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed embodiments without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the invention covers modifications and variations provided they fall within the scope of the following claims and their equivalents.