Relay driver circuit

This application is the U.S. national stage of PCT/JP2019/009236 filed on Mar. 8, 2019, which claims priority of Japanese Patent Application No. JP 2018-054225 filed on Mar. 22, 2018, the contents of which are incorporated herein.

The technology described herein relates to a relay driver circuit, specifically, the relay driver circuit capable of maintaining an operating state of a relay even when a drop occurs in power supply voltage.

A technology for maintaining an operating state of a relay even when a drop occurs in power supply voltage has been known. An example of such a technology is disclosed in Japanese Unexamined Patent Application Publication 2014-116197. In Japanese Unexamined Patent Application Publication 2014-116197, a first switch and a second switch are provided in two systems for driving a relay. A resistor is connected between the second switch and a coil of the relay. The relay is driven with the second switch to which the resistor is connected after a contact of the relay is moved. The relay is driven with the first switch if the drop occurs in power supply voltage to reduce power consumption and maintain the operating state of the relay even if the drop occurs in power supply voltage. Such a technology is disclosed.

As in Japanese Unexamined Patent Application Publication 2014-116197, semiconductor components are used for driving relays in recent years. A drop in power supply voltage, which may cause a drop in control input voltage applied to the semiconductor components, may have an adverse effect on control of relay operation.

In FIG. 2 , two relays (RL 1 and RL 2 ) provided in two stages are connected to a relay driver circuit 10 P. The relay RL 2 in the second stage (the lower stage) may be a load connected to the relay RL 1 in the first stage (the upper stage). In such a configuration, a diode D 1 for protection of a semiconductor component Q 1 may be provided in a control input line LCN connected to a semiconductor component for driving the lower stage relay RL 2 . If a load RD 1 that is connected in parallel to the lower stage relay RL 2 is an inductive load such as a motor, the diode D 1 is provided in the control input line LCN for the protection of the semiconductor component Q 1 from a surge caused by the inductive load. The control input voltage of the semiconductor component Q 1 may drop due to a voltage drop Vf (a forward voltage) of the diode D 1 . The semiconductor component Q 1 may not be able to remain in an on state, that is, the operating state of the lower stage relay RL 2 may not be maintained if a drop in battery voltage Vb (a power supply voltage) is out of tolerance.

A technology described herein is to provide a relay driver circuit that is capable of maintaining an operating state of a lower stage relay when a power supply voltage is low in a configuration that includes a protective component provided in a control input line connected to a semiconductor component for driving the lower stage relay that is a load connected to an upper stage relay.

A relay driver circuit described herein is connected between an upper stage relay and a lower stage relay that is configured to be driven in response to driving of the upper stage relay. The relay driver circuit is configured to drive the lower stage relay. The relay driver circuit includes a semiconductor component, a control input line, a protective component, and a buffer circuit. The semiconductor component switches on and off the lower stage relay. The control input line is electrically connected to a control terminal of the semiconductor component. A power supply voltage is applied to the control input line via the upper stage relay. The protective component is connected in the control input line to protect the semiconductor component. The buffer circuit is connected between the protective component in the control input line and the control terminal of the semiconductor component to compensate for a voltage drop due to the protective component.

According to the configuration, the voltage drop due to the protective component is compensated by the buffer circuit and thus a decrease in power supply voltage due to the protective component is reduced. Although the configuration for driving the lower stage relay, which is a load connected to the upper stage relay, includes the protective component provided in the control input line that is connected to the semiconductor component, an operating state of the lower stage relay is maintained even if the power supply voltage is low.

In the relay driver circuit, the buffer circuit may include a PNP bipolar transistor and an NPN bipolar transistor. The PNP bipolar transistor may include an emitter that is connected to a power supply line and a collector that is electrically connected to a control terminal of the semiconductor component. The NPN bipolar transistor may include a collector that is electrically connected to a base of the PNP bipolar transistor, a base that is electrically connected to an output of the protective component, and an emitter that is grounded. The protective component may include a protective diode that may include an anode that is connected to a contact of the upper stage relay and a cathode that is connected to the base of the NPN bipolar transistor.

According to the configuration, a voltage drop (a forward voltage) due to the diode can be properly compensated by the buffer circuit that includes two bipolar transistors. The forward voltage of the diode is about 0.7 V and a collector-emitter voltage of the PNP bipolar transistor is normally less than 0.7 V. When the power supply voltage is applied via the PNP bipolar transistor, the power supply voltage with a less voltage drop in comparison to a configuration in which the power supply voltage is applied via the diode can be applied to the control terminal of the semiconductor component. Namely, the voltage drop due to the diode is properly compensated.

In the relay driver circuit, the buffer circuit may include a rectifier diode that may include an anode that is electrically connected to the base of the PNP bipolar transistor and a cathode that is electrically connected to the collector of the NPN bipolar transistor.

According to the configuration, if the power supply is a battery, protection against inverse connection of the battery is provided.

Advantageous Effect of the Disclosure

According to the relay driver circuit described herein, although the configuration for driving the lower stage relay, which is a load connected to the upper stage relay, includes the protective component provided in the control input line that is connected to the driver semiconductor component, an operating state of the lower stage relay is maintained even if the power supply voltage is low.

FIG. 1 is a schematic block diagram of a relay system including a relay driver circuit according to an embodiment of the present disclosure.

FIG. 2 is a schematic block diagram of a relay system including a known relay circuit.

FIG. 3 is a schematic block diagram of a relay system including another example of a relay driver circuit.

A relay driver circuit 10 , which is an embodiment according to the present disclosure, will be described with reference to FIG. 1 . The relay driver circuit 10 in this embodiment is installed in a vehicle and a power supply is a battery Ba that is an onboard battery. The relay driver circuit 10 and the power supply are not limited to those for a vehicle.

Circuit Configuration

As illustrated in FIG. 1 , the relay driver circuit 10 is connected between an upper stage relay RL 1 and a lower stage relay RL 2 that is driven in response to driving of the upper stage relay RL 1 . The relay driver circuit 10 is configured to drive the lower stage relay RL 2 . The lower stage relay RL 2 is connected to the upper stage relay RL 1 and in parallel to an inductive load RD 1 including a motor M. The lower stage relay RL 2 and the inductive load RD 1 become active when the upper stage relay RL 1 is actuated.

The relay driver circuit 10 includes a semiconductor component Q 1 , a control input line LCN, a protective diode D 1 , and a buffer circuit 20 .

The semiconductor component Q 1 may include an N-channel MOSFET as illustrated in FIG. 1 . The semiconductor component Q 1 is configured to switch on and off the lower stage relay RL 2 in response to on and off of the upper stage relay RL 1 . Specifically, the semiconductor component Q 1 is configured to start and stop a flow of an exciting current through an exciting coil L 2 in the lower stage relay RL 2 . Bias resistors (R 1 , R 2 ) are connected to a gate G of the semiconductor component Q 1 .

The control input line LCN is electrically connected to the gate G of the semiconductor component Q 1 . The gate G is a control terminal. When the upper stage relay RL 1 is in the on state, a battery voltage Vb (a power supply voltage) is applied to the control input line LCN via a relay contact 1 of the upper stage relay RL 1 .

A protective diode D 1 (an example of a protective component) is provided in the control input line LCN. The protective diode D 1 protects the semiconductor component Q 1 from a surge caused by the inductive load RD 1 , such as a motor that is connected to the upper stage relay RL 1 , transmitted through the control input line LCN. An anode A of the protective diode D 1 is connected to the relay contact 1 of the upper stage relay RL 1 via the control input line LCN. A cathode of the protective diode D 1 is connected to a base B of an NPN bipolar transistor TR 1 , which will be described later, via a bias resistor R 3 .

The buffer circuit 20 is connected between the protective diode D 1 in the control input line LCN and the gate G of the semiconductor component Q 1 to compensate for the voltage drop Vf (the forward voltage) due to the protective diode D 1 .

Specifically, as illustrated in FIG. 1 , the buffer circuit 20 includes the NPN bipolar transistor (hereinafter referred to as the NPN transistor) TR 1 , a PNP bipolar transistor (hereinafter referred to as the PNP transistor) TR 2 , a rectifier diode D 2 , and bias resistors (R 3 , R 4 , R 5 , and R 6 ).

An emitter E of the NPN transistor TR 1 is connected to a ground so that the emitter E is grounded. A collector C of the NPN transistor TR is connected to a cathode K of the rectifier diode D 2 . The collector C is electrically connected to a base B of the PNP transistor TR 2 via the rectifier diode D 2 and the bias resistor R 5 . The base B of the NPN transistor TR 1 is electrically connected to the cathode K (an output of the protective component) of the protective diode D 1 via the bias resistor R 3 .

The emitter E of the PNP transistor TR 2 is connected to a power supply line LV. The collector C of the PNP transistor TR 2 is electrically connected to the gate G of the semiconductor component Q 1 via the bias resistor R 1 . The base B of the PNP transistor TR 2 is connected to the anode A of the rectifier diode D 2 via the bias resistor R 5 .

The anode A of the rectifier diode D 2 is electrically connected to the base B of the PNP transistor TR 2 via the bias resistor R 5 . The cathode K of the rectifier diode D 2 is connected to the collector C of the NPN transistor. The rectifier diode D 2 is a protection against inverse connection of the battery Ba. If the battery Ba is inversely connected, a current flows from the ground to the power supply line LV via the resistor R 4 , the base B to the collector C of the NPN transistor TR 1 , resistor R 5 , and the resistor R 6 in this sequence if the rectifier diode D 2 is not provided. Therefore, an inverse voltage is applied between the base B and the emitter E of the NPN transistor TR 1 and the base B and the emitter E of the PNP transistor TR 2 . This may result in damages to the transistors.

Operation of the Buffer Circuit

Next, operation of the buffer circuit 20 having the above configuration will be described.

When the upper stage relay RL 1 is switched on through actuation of an upper stage relay actuating switch SW 1 , the battery voltage Vb is applied to the buffer circuit 20 via the control input line LCN and the protective diode D 1 . A base current flows through the NPN transistor TR 1 and the NPN transistor TR 1 turns on. A base current flows through the PNP transistor TR 2 and the PNP transistor TR 2 turns on.

The battery voltage Vb is applied to the gate G of the semiconductor component Q 1 via the PNP transistor TR 2 . The semiconductor component Q 1 turns on and thus the lower stage relay RL 2 is switched on.

Normally, a collector-emitter voltage drop in the PNP transistor TR 2 is equal to or less than 0,1 V, which is sufficiently smaller than the voltage drop Vf due to the protective diode D 1 (normally, 0.7 V). In comparison to the known example illustrated in FIG. 2 , a voltage closer to the battery voltage Vb can be applied to the gate G of the semiconductor component Q 1 (more precisely, bias resistors R 1 and R 2 ). In the configuration that includes the protective diode D 1 in the control input line LCN, the on state of the semiconductor component Q 1 is maintained and thus the on state of the lower stage relay RL 2 is maintained even if the battery voltage Vb is further dropped in comparison to the known example.

Effects of the Embodiment

The voltage drop Vf due to the protective diode D 1 is compensated by the buffer circuit 20 . Namely, with the buffer circuit 20 , a decrease in battery voltage Vb due to the protective diode D 1 can be reduced. Although the configuration for driving the lower stage relay RL 2 , which is the load connected to the upper stage relay RL 1 , includes the protective diode D 1 that is connected in the control input line LCN that is connected to the semiconductor component Q 1 (the driver semiconductor component), the operating state of the lower stage relay RL 2 is maintained even if the battery voltage Vb is lower in comparison to the configuration that does not include the buffer circuit 20 . This improves functionality and safety of a vehicle system.

The buffer circuit 20 properly compensates for the voltage drop Vf (the forward voltage) due to the protective diode D 1 with two bipolar transistors (TR 1 and TR 2 ), that is, with a simple configuration. Normally, the forward voltage of a diode is about 0.7 V and thus a voltage drop due to an on-resistance of the PNP bipolar transistor TR 2 is equal to or less than 0.1 V. When applying the battery voltage Vb to the gate terminal G (the control terminal) of the semiconductor component Q 1 via the PNP bipolar transistor TR 2 , the battery voltage Vb with less voltage drop can be applied to the gate terminal G in comparison to a configuration in which the battery voltage Vb is applied via the protective diode D 1 . The voltage drop Vf due to the protective diode D 1 is properly compensated and reduced.

The present disclosure described herein is not limited to the embodiment described above and illustrated in the drawing. For example, the following embodiments will be included in the technical scope of the technology described herein.

In the above embodiment, the buffer circuit 20 includes two bipolar transistors (TR 1 and TR 2 ). However, the configuration of the buffer circuit 20 is not limited to such a configuration. For example, as illustrated in FIG. 3 , the NPN transistor TR 1 and the PNP transistor TR 2 of the buffer circuit 20 may be replaced with an N-channel MOSFET 1 and a P-channel MOSFET 2 , respectively.

In the above embodiment, the protective diode D 1 is provided as an example of the protective component. However, the protective component is not limited to the protective diode D 1 . For example, if the surge caused by the inductive load RD 1 is significantly small, a resistor having a low resistance may be used for the protective component.

In the above embodiment, the rectifier diode D 2 is included in the buffer circuit 20 for the protection against inverse connection of the battery. However, the rectifier diode D 2 may be omitted.