Switching power supply circuit with synchronous rectification and associated control circuit and control method

This application claims the benefit of CN application 201911254525.7, filed on Dec. 10, 2019, and incorporated herein by reference.

The present invention relates generally to electrical circuits, and more particularly, relates to switching power supply circuits with synchronous rectification.

In an isolated switching power supply, an input voltage is received at a primary side of a transformer, and a diode at a secondary side of the transformer is replaced by a controllable synchronous rectifier (SR) switch. This synchronous rectification scheme is widely used at the secondary side of the isolated switching power supply because of its high conversion efficiency.

In the isolated switching power supply, a drain to source voltage of the SR switch at the secondary side may be adopted to determine the ON and OFF of the SR switch. A slew rate of the drain to source voltage of the SR switch is also detected to avoid the false trigger due to the ringing of the drain to source voltage of the SR switch at the same time. However, with the increase of switching frequency of the isolated switching power supply, a slew rate of the drain to source voltage ringing becomes closer to the slew rate of the drain to source voltage when it is normally turned ON. As a result, accurate turning ON of the SR switch is in demand for application with increased switching frequency.

Embodiments of the present invention are directed to secondary control circuits used in a switching power supply circuit with synchronous rectification. The switching power supply circuit comprises an energy storage component and a SR switch coupled to a secondary side of the energy storage component. The SR switch has a drain terminal, a source terminal and a gate terminal. The secondary control circuit comprises a turning-ON control circuit, a mode determination circuit and a gate driver circuit. The turning-ON control circuit is configured to provide a turning-ON control signal based on a comparison of the drain to source sensing voltage of the SR switch and a turn ON threshold. The mode determination circuit is configured to provide a mode signal to determine a turn ON delay based on based on a detection to a transient event or the drain to source sensing voltage ringing of the SR switch. The mode signal has a first level indicating a fast mode and a second level indicating a slow mode. The gate driver circuit is configured to drive the SR switch, wherein when the turning-ON control signal is asserted, the gate driver circuit charges a gate voltage of the SR switch after the turn ON delay based on the mode signal, to turn ON the SR switch.

Embodiments of the present invention are directed to methods to control a SR switch in a switching power supply circuit including an energy storage component coupled to the SR switch. The SR switch comprises a drain terminal, a source terminal and a gate terminal. The method comprises generating a turning-ON control signal based on comparing a drain to source sensing voltage with a turn ON threshold, generating a mode signal to determine a turn ON delay by detecting a transient event or the drain to source sensing voltage ringing of the SR switch, and when the turning ON control signal is asserted, charging a gate voltage of the SR switch after the turn ON delay based on the mode signal, to turn ON the SR switch. The mode signal is high level indicating a slow mode and is low level indicating a fast mode.

Non-limiting and non-exhaustive embodiments are described with reference to the following drawings. The drawings are only for illustration purpose. These drawings are not necessarily drawn to scale. The relative sizes of elements illustrated by the drawings may differ from the relative size depicted.

FIG. 1 schematically illustrates a flyback converter 100 with synchronous rectification.

FIG. 2 illustrates working waveforms of the flyback converter 100 shown in FIG. 1 in discontinuous current mode (DCM) operation.

FIG. 3 illustrates a circuit block diagram of a switching power supply circuit 200 with synchronous rectification in accordance with an embodiment of the present invention.

FIG. 4 illustrates a method 300 for turning-on a SR switch of the switching power supply circuit 200 shown in FIG. 3 in accordance with an embodiment of the present invention.

FIG. 5 illustrates a circuit block diagram of a mode determination circuit 203 shown in FIG. 3 in accordance with an embodiment of the present invention.

FIG. 6 illustrates a work flow of the mode determination circuit 203 shown in FIG. 5 in accordance with an embodiment of the present invention.

FIG. 7 illustrates a circuit block diagram of a gate driver circuit 204 A in accordance with an embodiment of the present invention.

FIG. 8 illustrates a circuit block diagram of a gate driver circuit 204 B in accordance with another embodiment of the present invention.

FIG. 9 illustrates working waveforms of a switching power supply circuit in accordance with an embodiment of the present invention.

FIG. 10 illustrates working waveforms of a switching power supply circuit in accordance with another embodiment of the present invention.

The use of the same reference label in different drawings indicates the same or like components.

Reference will now be made in detail to the preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. While the invention will be described in conjunction with the preferred embodiments, it will be understood that they are not intended to limit the invention to these embodiments. On the contrary, the invention is intended to cover alternatives, modifications and equivalents, which may be included within the spirit and scope of the invention as defined by the appended claims. Furthermore, in the following detailed description of the present invention, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be obvious to one of ordinary skill in the art that the present invention may be practiced without these specific details. In other instances, well-known methods, procedures, components, and circuits have not been described in detail so as not to unnecessarily obscure aspects of the present invention.

In the following description, a flyback converter with synchronous rectification, as an example, is considered to describe a problem to be solved by this invention. FIG. 1 schematically illustrates a flyback converter 100 with synchronous rectification.

The flyback converter 100 shown in FIG. 1 has a transformer T, a primary switch Q 1 coupled to a primary side of the transformer T, and a SR switch Q 2 coupled to a secondary side of the transformer T. The primary side of transformer T receives an input voltage Vin, and the secondary side of the transformer T provides an output voltage Vout. The SR switch Q 2 comprises a drain terminal D, a source terminal S and a gate terminal G. A drain to source voltage VDS of the SR switch Q 2 is detected to generate a secondary control signal CTRL for turning-ON and turning-OFF of the SR switch Q 2 .

FIG. 2 illustrates working waveforms of the flyback converter 100 shown in FIG. 1 in DCM operation. At time t 0 , the primary switch Q 1 is turned OFF, the energy stored in the primary side of the transformer T is transferred to the secondary side of the transformer T, a current generated on the secondary side winding flows through a body diode of the SR switch Q 2 , the body diode of the SR switch Q 2 is forward-conducted, and the drain to source voltage VDS of the SR switch Q 2 is quickly reduced to below 0V and to be a negative value. When the drain to source voltage VDS of the SR switch Q 2 is decreased to reach a turn ON threshold Vth_on, the secondary control signal CTRL quickly becomes a high level, to turn ON the SR switch Q 2 . At time t 1 , the drain to source voltage VDS of the SR switch Q 2 is increased to reach a turn OFF threshold Vth_off, the secondary control signal CTRL quickly becomes a low level to turn OFF the SR switch Q 2 . In DCM operation, the demagnetizing ringing may drop the drain to source voltage VDS below 0V. If the drain to source voltage VDS reaches the turn ON threshold Vth_on during the ringing, the SR switch Q 2 may be turned ON quickly by mistake. For example, FIG. 2 shows a false turn-on situation at time t 2 , the drain to source voltage VDS rings below the turn ON threshold Vth_on, the secondary control signal CTRL becomes the high level, the SR switch Q 2 is turned ON quickly by mistake. Not only does this increase power loss and high voltage spike, but may also lead to shoot-through if the primary switch Q 1 is turned ON within the minimum on time.

The problem of false turn-on of the SR switch can be solved by the present invention. FIG. 3 illustrates a circuit block diagram of a switching power supply circuit 200 with synchronous rectification in accordance with an embodiment of the present invention. As shown in FIG. 3 , the switching power supply circuit 200 comprises an energy storage component T 1 , a primary switch S 1 coupled to a primary side of the energy storage component T 1 , a primary control circuit IC 1 for controlling the primary switch S 1 , a SR switch S 2 coupled to a secondary side of the energy storage component T 1 , and a secondary control circuit IC 2 for controlling the SR switch S 2 . The primary side of the energy storage component T 1 receives an input voltage Vin, and the secondary side of the energy storage component T 1 provides an output voltage Vout.

In the embodiment of FIG. 3 , the secondary control circuit IC 2 has pins P 0 ˜P 3 . The secondary control circuit IC 2 is configured to be an integrated circuit and to generate a secondary control signal VG at pin P 3 for controlling the SR switch S 2 . The SR switch S 2 comprises a drain terminal D, a source terminal S and a gate terminal G. The secondary control circuit IC 2 comprises a turning-ON control circuit 201 , a turning-OFF control circuit 202 , a mode determination circuit 203 and a gate driver circuit 204 . As shown in FIG. 3 , the secondary control circuit IC 2 has a pin P 1 coupled to the S terminal of the SR switch S 2 and a pin P 0 coupled to the D terminal of the SR switch S 2 . A subtracting circuit 205 receives voltages at the S terminal and the D terminal of the SR switch S 2 , and provides a drain to source sensing voltage VDS of the SR switch S 2 at its output terminal. In other embodiments, the drain to source sensing voltage VDS of the SR switch S 2 can be sensed by other components.

The turning-ON control circuit 201 has a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is configured to receive the drain to source sensing voltage VDS of the SR switch S 2 , the second input terminal is configured to receive a turn ON threshold Vth_on, the turning-ON control circuit 201 is configured to compare the drain to source sensing voltage VDS of the SR switch S 2 with the turn ON threshold Vth_on and generates a turn ON control signal SR_on at the output terminal. In one embodiment, when the drain to source sensing voltage VDS is decreased to below the turn ON threshold Vth_on, the turning-ON control circuit 201 provides the turning-ON control signal SR_on having a high level, and the turning-ON control signal SR_on is asserted. When the turning-ON control signal SR_on has a low level, and the turning-ON control signal SR_on is de-asserted.

The turning-OFF control circuit 202 has a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is configured to receive the drain to source sensing voltage VDS, the second input terminal is configured to receive a turn OFF threshold Vth_off, the turning-OFF control circuit 202 is configured to compare the drain to source sensing voltage VDS with the turn OFF threshold Vth_off, and to generate a turning-OFF control signal SR_off at the output terminal. In one embodiment, when the drain to source sensing voltage VDS is increased to above the turn OFF threshold Vth_off, the turning-OFF control circuit 202 provides the turn OFF control signal SR_off having a high value, and the turning-OFF control signal SR_off is asserted.

The mode determination circuit 203 is configured to determine a turn ON delay according to the operation of the switching power supply circuit 200 . The turn ON delay indicates that how long a body diode of the SR switch S 2 conducts before the SR switch S 2 is turned ON. In one embodiment, the mode determination circuit 203 is configured to generate a mode signal MS, when the mode signal MS becomes high level, the mode is determined to be a slow mode, and a larger turn ON delay is selected to delay the turning-ON of the SR switch S 2 . When the mode signal MS becomes low level, the mode is determined to be a fast mode, and a small turn ON delay is selected to delay the turning-ON of the SR switch S 2 .

If any of the following situation is detected, the mode determination circuit 203 will determine the detection results as the slow mode: 1) any transient events; 2) VDS ringing of the SR switch S 2 . Once any transient events or VDS ringing of the SR switch S 2 in DCM operation occur, the mode signal MS becomes the high level indicating the slow mode and a larger turn ON delay is determined. With a larger and appropriate turn ON delay, the body diode conduction duration of the SR switch S 2 is longer, the shoot-through is avoided. When the switching power supply circuit 200 is working on a stable state without VDS ringing of the SR switch S 2 , the mode signal MS is the low level indicating the fast mode, the small turn ON delay is selected. With the small turn ON delay, the body diode conduction duration of the SR switch S 2 is short, which improves the total efficiency. In one embodiment, to keep the body diode conduction loss on a fairly low level, the turn ON delay for the slow mode is selected to be not larger than 5% of the switching cycle of the switching power supply circuit 200 .

In one hand, the mode determination circuit 203 is configured to detect a transient event. The transient event can be caused within the switching power supply circuit 200 by variations of the input voltage Vin and/or changes in a loading current. In one embodiment, in response to the detected transient event, the secondary control signal VG is regulated at least in part by varying an on-time of the SR switch Q 2 during the transient events. When no transient event is detected by the mode determination circuit 203 , the on-time of the SR switch Q 2 is kept to be a constant value.

In one embodiment, the transient event can be detected by detecting whether a change ratio of the conduction time of the SR switch Q 2 cycle by cycle exceeds a preset value (e.g., 5%). In another embodiment, the transient event can be detected by detecting a decrease of the output voltage Vout of the switching power supply circuit 200 with respect to a reference voltage. In yet another embodiment, a transient event is based on a signal representative of a peak current flowing through the SR switch Q 2 .

In the other hand, the mode determination circuit 203 is configured to have a slew rate detection function and is configured to detect VDS ringing of the SR switch S 2 in DCM operation. In one embodiment, the VDS ringing is detected by detecting whether the time duration of the drain to source sensing voltage VDS higher than a detection threshold Vdet_th is less than a window length TW.

Those skilled in the art will appreciate that embodiments of the present invention may be practiced in other ways and the embodiments described herein are merely example embodiments of the invention.

In the embodiment of FIG. 3 , the mode determination circuit 203 has a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is configured to receive the drain to source sensing voltage VDS, a second input terminal is configured to receive the secondary control signal VG, and the mode determination circuit 203 is configured to provide the mode signal MS at the output terminal.

The gate driver circuit 204 has a first input terminal, a second input terminal, a third input terminal and an output terminal, wherein the first input terminal is configured to receive the mode signal MS, the second input terminal is configured to receive the turning-ON control signal SR_on, the third input terminal is configured to receive the turning-OFF control signal SR_off. The gate driver circuit 204 is configured to control the turning-ON of the SR switch S 2 based on the mode signal MS and the turning-ON control signal SR_on, and is further configured to control the turning-OFF of the SR switch S 2 based on the turning-OFF control signal SR_off.

In detail, when the mode signal MS is low level, the fast mode and the small turn ON delay is determined, when the turning-ON control signal SR_on is asserted, the gate driver circuit 204 starts to charge a gate voltage of the SR switch S 2 after the small turn ON delay. The gate voltage of the SR switch S 2 is increased to turn ON the SR switch S 2 . When the mode signal MS is high level, the slow mode and the larger turn ON delay is determined, once the turning-ON control signal SR_on is asserted, the gate driver circuit 204 starts to charge the gate voltage of the SR switch S 2 after the larger turn ON delay. The gate voltage of the SR switch S 2 is increased to turn ON the SR switch S 2 . When the turning-OFF control signal SR_off is asserted, the gate driver circuit 204 turns ON a discharge switch coupled between the gate terminal of the SR switch S 2 and a ground, to provide a discharge path, the gate voltage of the SR switch S 2 is decreased, and the SR switch S 2 is turned OFF.

In one embodiment, the mode determination circuit 203 further has a third input terminal coupled to a discrete off-chip resistor R 1 through a pin P 2 of the secondary control circuit IC 2 . A voltage signal VTW on the resistor R 1 is an adjustable signal representative of the window length TW and can be adjusted by change the resistance of the resistor R 1 so that the window length TW can be regulated.

Embodiments of the invention are described herein in the context of one practical non-limiting application, namely, a flyback converter with synchronous rectification. Embodiments of the invention, however, are not limited to such applications, and the techniques described herein may also be utilized in other switching power supply circuit, such as LLC resonant converter with synchronous rectification.

FIG. 4 illustrates a method 300 for turning-on a SR switch of the switching power supply circuit 200 shown in FIG. 3 in accordance with an embodiment of the present invention. The method 300 for turning-on the SR switch comprises: asserting the turning-ON control signal, and when the mode is determined to be the fast mode according to the operation of switching power supply circuit 200 , determining a small turn ON delay and charging the gate voltage of the SR switch after the small turn ON delay; when the mode is determined to be the slow mode, determining a larger turn ON delay and charging the gate voltage of the SR switch after the larger turn ON delay. In one embodiment, the turn ON delay for the slow mode is 150 ns, the turn ON delay for the fast mode is 50 ns.

In a further embodiment, when the mode is determined to be the slow mode and the turning-ON control signal SR_on is asserted, and charging the gate voltage of the SR switch with a lower charge current after the larger turn ON delay. When the mode is determined to be the fast mode and the turning-ON control signal SR_on is asserted, and charging the gate voltage of the SR switch with a high charge current after the small turn ON delay. In one embodiment, the charge current for slow mode is 0.25 A, the charge current for fast mode is 2 A.

FIG. 5 illustrates a circuit block diagram of a mode determination circuit 203 shown in FIG. 3 in accordance with an embodiment of the present invention. As shown in FIG. 5 , the mode determination circuit 203 comprising a first determination circuit 405 , a second determination circuit 406 , a logic circuit 408 and a timer circuit 409 .

The first determination circuit 405 is configured to detect the VDS ringing in DCM operation. The first determination circuit 405 has first input terminal, a second input terminal and an output terminal, wherein the first input terminal is coupled to receive the drain to source sensing voltage VDS, the second input terminal is coupled to receive the voltage signal VTW representative of the window length TW. A time duration TS of the drain to source sensing voltage VDS higher than the detection threshold Vdet_th is compared with the window length TW, and based on the comparison result, the first determination circuit 405 provides a first mode signal MS 1 at the output terminal. In one embodiment, when the time duration TS is detected to less than the window length TW, the first determination circuit 405 provides the first mode signal MS 1 having high level.

In the embodiment of FIG. 5 , the first determination circuit 405 comprises a TW setting circuit 411 , a first comparison circuit 412 and a VDS ringing detection circuit 413 . The TW setting circuit 411 is coupled to receive the voltage signal VTW, to set the window length TW for VDS ringing detection. The first comparison circuit 412 has a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is coupled to receive the drain to source sensing voltage VDS of the SR switch S 2 , the second input terminal is coupled to receive the detection threshold Vdet_th. The VDS ringing detection circuit 413 has a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is coupled to the TW setting circuit 411 to receive the window length TW, the second input terminal is coupled to the output terminal of the first comparison circuit 412 , the VDS ringing detection circuit 412 records the time duration TS of the drain to source sensing voltage VDS higher than the detection threshold Vdet_th, and compares the time duration TS with the window length TW, provides the first mode signal MS 1 at the output terminal according to the comparison result.

The second determination circuit 406 is configured to detect the transient event. In the embodiment of FIG. 5 , the second determination circuit 406 has a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is coupled to receive the secondary control signal VG, the second input terminal is coupled to receive a preset value K 1 . In one embodiment, the preset value K 1 is 5%. The second determination circuit 406 is configured to detect the conduction time of the SR switch cycle by cycle and to provide a change ratio K 0 of the conduction time of the SR switch Q 2 cycle by cycle. The second determination circuit 406 provides a second mode signal MS 2 at the output terminal based on the comparison of the change ratio K 0 and the preset value K 1 . In one embodiment, when the change ratio K 0 exceeds the preset value K 1 , the second determination circuit 406 provides the second mode signal MS 2 having high level.

The logic circuit 408 comprises a OR gate circuit 407 and a flip-flop FF 1 . Wherein the OR gate circuit 407 has a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is coupled to receive the first mode signal MS 1 , the second input terminal is coupled to receive the second mode signal MS 2 . The flip-flop FF 1 has a setting terminal, a resetting terminal and an output terminal, wherein the setting terminal is coupled to the output terminal of the OR gate circuit 407 , the resetting terminal is coupled to the output terminal of the flip-flop FF 1 through the timer circuit 409 . The flip-flop FF 1 provides the mode signal MS at the output terminal. In one embodiment, when any of the first mode signal MS 1 and the second mode signal MS 2 has high level, the setting terminal of the flip-flop FF 1 is triggered, and the flip-flop FF 1 provides the mode signal MS having high level, the slow mode is determined.

When the time duration of the mode signal MS with high level exceeds a time limit set by the timer circuit 409 , the resetting terminal of the flip-flop FF 1 is triggered, the flip-flop FF 1 outputs the mode signal MS having low level, the mode determination circuit 203 exits the slow mode and enters into the fast mode.

FIG. 6 illustrates a work flow of the mode determination circuit 203 shown in FIG. 5 in accordance with an embodiment of the present invention. This work flow comprises steps 501 ˜ 509 .

At step 501 , the mode signal MS is on a low level, and the mode is determined to be the fast mode.

In one hand, at step 502 , a conduction time of the SR switch is recorded as T N .

At step 503 , the conduction time T N is compared with last cycle's conduction time T N-1 of the SR switch.

At step 504 , a change ratio K 0 of the conduction time of the SR switch is calculated, K 0 =|T N −T N-1 |/T N-1 . The change ratio K 0 is compared with a preset value K 1 . If the change ratio K 0 exceeds the preset value K 1 , go to step 508 . If not, go back to step 501 . In one embodiment, the preset value is 5%. In other words, when T N >105% T N-1 or T N <95% T N-1 , go to step 508 .

At step 508 , the mode signal MS is on a high level, the mode is determined to be the slow mode.

In the other hand, at step 505 , the drain to source sensing voltage VDS is compared with the detection threshold Vdet_th.

At step 506 , the time duration of the drain to source sensing voltage VDS higher than the detection Vdet_th is recorded as TS.

At step 507 , the time duration TS is compared with the window length TW, if TS<TW, go to step 508 , otherwise, go back to step 501 .

At step 509 , when the time duration of the mode signal MS with high level exceeds a time limit, exits the slow mode and enters into the fast mode.

The sequence of the text in any of the claims does not imply that process steps must be performed in a temporal or logical order according to such sequence unless it is specifically defined by the language of the claim. The process steps may be interchanged in any order without departing from the scope of the invention as long as such an interchange does not contradict the claim language and is not logically nonsensical.

FIG. 7 illustrates a circuit block diagram of a gate driver circuit 204 A in accordance with an embodiment of the present invention. As shown in FIG. 7 , the gate driver circuit 204 A comprises a current source IS 0 , a selective delay circuit 241 A, a logic circuit 242 A and a discharge switch 244 A. The current source IS 0 has a power supply terminal and an output terminal, wherein the power supply terminal is coupled to receive a power supply voltage VDD, the current source IS 0 provides a charge current IG at the output terminal. The logic circuit 242 A comprises a flip-flop FF 2 . The flip-flop FF 2 has a setting terminal, a resetting terminal, an output terminal and a reversing output terminal, wherein the setting terminal is configured to receive the turning-ON control signal SR_on, the resetting terminal is configured to receive the turning-OFF control signal SR_off. The selective delay circuit 241 A has an input terminal, a control terminal, an enable terminal and an output terminal, wherein the input terminal is coupled to the output terminal of the current source IS 0 , the control terminal is coupled to receive the mode signal MS, the enable terminal is coupled to the output terminal of the flip-flop FF 2 , the output terminal is coupled to the gate terminal G of the SR switch S 2 for providing a charge current to charge the gate voltage of the SR switch S 2 based on the mode signal MS and the corresponding turn ON delay.

When the mode signal MS is low level, a small turn ON delay is determined, when the turning-ON control signal SR_on is asserted, the selective delay circuit 241 A starts to charge the gate voltage of the SR switch S 2 with the charge current IG after the small turn ON delay. With a small turn ON delay, the body diode conduction loss is kept in a fairy low level, the total efficiency is good. When the mode signal MS is high level, a larger turn ON delay is determined, when the turning-ON control signal SR_on is asserted, the selective delay circuit 241 A starts to charge the gate voltage of the SR switch S 2 with the charge current IG after the larger turn ON delay. With the larger turn ON delay, the shoot-through problem can be avoided. The discharge switch 244 A is coupled between the gate terminal of the SR switch S 2 and ground, has a control terminal coupled to the reversing output terminal of the flip-flop FF 2 . When the turning-OFF control signal SR_off is asserted, the discharge switch 244 A is turned ON to provide a discharge path, the gate voltage of the SR switch S 2 is decreased, and the SR switch S 2 is turned OFF.

FIG. 8 illustrates a circuit block diagram of a gate driver circuit 204 B in accordance with another embodiment of the present invention. In the embodiment of FIG. 8 , the gate driver 204 B comprises a signal delay circuit 241 B, a logic circuit 242 B, a first current source IS 1 and a second current source IS 2 , a selecting circuit 243 B and a discharge switch 244 B. The signal delay circuit 241 B has an input terminal, a control terminal and an output terminal, wherein the input terminal is configured to receive the turning-ON control signal SR_on, the control terminal is configured to receive the mode signal MS, based on the mode signal MS, the signal delay circuit 241 B delays the turning-ON control signal SR_on by a corresponding turn ON delay, and provides a delayed turning ON control signal SR_on 1 . In detail, when the mode signal MS is low level, the delayed turning-ON control signal SR_on 1 lags the turning-ON control signal SR_on by the small turn ON delay. When the mode signal MS is high level, the delayed turning-ON control signal SR_on 1 lags the turning-ON control signal SR_on by the larger turn ON delay.

The logic circuit 242 B comprises a flip-flop FF 3 , the flip-flop FF 3 has a setting terminal, a resetting terminal, an output terminal and a reversing output terminal, wherein the setting terminal is coupled to the output terminal of the signal delay circuit 241 B to receive the delayed turning-ON control signal SR_on 1 , the resetting terminal is configured to receive the turning-OFF control signal SR_off.

The first and second current sources IS 1 and IS 2 , respectively, have a power supply terminal coupled to receive a power supply voltage VDD and an output terminal configured to provides a first charge current IG 1 and a second charge current IG 2 , respectively. The first charge current IG 1 is higher than the second charge current IG 2 . The selecting circuit 243 B has a first input terminal, a second input terminal, a control terminal, an enable terminal and an output terminal, wherein the first input terminal is coupled to the output terminal of the first current source IS 1 to receive the first charge current IG 1 , the second input terminal is coupled to the output terminal of the second current source IS 2 to receive the second charge current IG 2 , the control terminal is coupled to receive the mode signal MS, the enable signal is coupled to the output terminal of the flip-flop FF 3 , based on the mode signal MS, when the turning-ON control signal SR_on is asserted, the selecting circuit 243 B selects one of the first charge current IG 1 and the second charge current IG 2 , and charges the gate terminal voltage of the SR switch S 2 with the selected charge current. When the mode signal MS has a low level, the selecting circuit 243 B selects the first charge current IG 1 to the gate terminal of the SR switch S 2 , and charges the gate voltage of the SR switch S 2 with the first charge current IG 1 . When the mode signal MS has high level, the selecting circuit 243 B selects the second charge current IG 2 to the gate terminal of the SR switch S 2 , and charges the gate voltage of the SR switch S 2 with the second charge current IG 2 . The discharge switch 244 B is coupled between the gate terminal of the SR switch S 2 and ground, the control terminal of the discharge switch 244 B is coupled to the reversing terminal of the flip-flop FF 3 . When the turning-OFF control signal SR_off is asserted, the discharge switch 244 B is turned ON to generate a discharge path, and the gate voltage of the SR switch is decreased and the SR switch S 2 is turned OFF.

Several of the details of the embodiments described below with reference to FIG. 9 and FIG. 10 . FIG. 9 illustrates working waveforms of a switching power supply circuit in accordance with an embodiment of the present invention. As shown in FIG. 9 , at time t 11 , the drain to source sensing voltage VDS decreases to below the turn ON threshold Vth_on, the turning-on control signal SR_on is asserted, the gate voltage of the SR switch is charged with the high charge current IG 1 after the small turn ON delay, the gate voltage of the SR switch increases until to the maximum voltage Vmax, to turn ON the SR switch. In one embodiment, the high charge current IG 1 is 2 A, the small turn ON delay is 50 ns.

At time t 12 , the drain to source sensing voltage VDS is increased to above the turn OFF threshold Vth_off, the turning-OFF control signal SR_off is asserted, the discharge switch is turned ON, and the gate voltage of the SR switch is decreased, the SR switch is turned OFF.

At time t 13 , the time duration TS of the drain to source sensing voltage VDS higher than the detection threshold Vdet_th is less than the window length TW, the mode signal MS transits from low level to high level, the slow mode is determined.

At time t 14 , the turning-ON control signal SR_on is asserted again, and the mode signal MS is high level, the gate voltage of the SR switch is charged with a lower charge current IG 2 after the larger turn ON delay, the gate voltage of the SR switch increases until to the maximum voltage Vmax. In one embodiment, the lower charge current IG 2 is 250 mA, the larger turn ON delay is 150 ns.

FIG. 10 illustrates working waveforms of a switching power supply circuit in accordance with another embodiment of the present invention. As shown in FIG. 10 , at time t 21 , the turning-ON control signal SR_on is asserted, the mode signal MS is low level. The gate voltage of the SR switch is charged with the high charge current IG 1 after the small turn ON delay, the gate voltage of the SR switch increases until to the maximum voltage Vmax, to turn ON the SR switch.

At time t 22 , the turning-OFF control signal SR_off is asserted and the SR switch is turned OFF. At the same time, the conduction time of the SR switch is recorded as T N . When T N >105% T N-1 , the mode signal MS transits from low level to high level.

At time t 23 , the turning-ON control signal SR_on is asserted again, the mode signal MS is high level, and the slow mode is determined. The gate voltage of the SR switch is charged with the lower charge current IG 2 after the larger turn ON delay, the gate voltage of the SR switch increases to control the turning-ON of the SR switch, the gate voltage of the SR switch increases until the maximum voltage Vmax.

In this document, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Numerical ordinals such as “first,” “second,” “third,” etc. simply denote different singles of a plurality and do not imply any order or sequence unless specifically defined by the claim language. The sequence of the text in any of the claims does not imply that process steps must be performed in a temporal or logical order according to such sequence unless it is specifically defined by the language of the claim. The process steps may be interchanged in any order without departing from the scope of the invention as long as such an interchange does not contradict the claim language and is not logically nonsensical.

Obviously many modifications and variations of the present invention are possible in light of the above teachings. It is therefore to be understood that within the scope of the appended claims the invention may be practiced otherwise than as specifically described. It should be understood, of course, the foregoing disclosure relates only to a preferred embodiment (or embodiments) of the invention and that numerous modifications may be made therein without departing from the spirit and the scope of the invention as set forth in the appended claims. Various modifications are contemplated and they obviously will be resorted to by those skilled in the art without departing from the spirit and the scope of the invention as hereinafter defined by the appended claims as only a preferred embodiment(s) thereof has been disclosed.