Control method of power conversion circuit, and related power conversion circuit

This application is a continuation of International Application No. PCT/CN2018/125802 filed on Dec. 29, 2018, which claims priority to Chinese Patent Application No. 201810098063.3 filed on Jan. 31, 2018. The disclosures of the aforementioned applications are hereby incorporated by reference in their entireties.

This application relates to the field of power supply technologies, and in particular, to a control method of a power conversion circuit, and a related power conversion circuit.

Power conversion circuits are widely used for conversion from electric energy at one voltage level to electric energy at another voltage level. For example, in DC-DC conversion, a DC-DC conversion circuit performs working procedures such as voltage transformation, rectification, and filtering on a source input voltage, and finally outputs a needed voltage to a load. A power conversion circuit usually includes a switch circuit, a transformer, a rectifier circuit, and a filter circuit. To implement orderly and stable power conversion, highly frequent control operations usually need to be performed on the switch circuit in the power conversion circuit. Therefore, energy losses in the power conversion circuit mainly result from a switching loss, a conduction loss, and a current switching loss that are in the switch circuit. However, in the prior art, a switching loss, a conduction loss, and a current switching loss that are in a switch circuit usually cannot be reduced at the same time, and technical integration is still faced with a serious challenge.

Embodiments of the present application provide a control method of a power conversion circuit, and a related power conversion circuit, so as to reduce a switching loss, a conduction loss, and a current switching loss that are in the power conversion circuit.

According to a first aspect, an embodiment of the present application provides a control method of a power conversion circuit, where the power conversion circuit includes a three-level switch circuit, a resonant circuit, a transformer, a rectifier circuit, and a filter circuit, three input ends of the three-level switch circuit are respectively connected to a DC voltage output end P, a reference voltage output end UREF, and a DC voltage output end N, an output end SM of the three-level switch circuit is connected to an input end of the resonant circuit, an output end of the resonant circuit is connected to a primary-side winding of the transformer, a secondary-side winding of the transformer is connected to an input end of the rectifier circuit, and an output end of the rectifier circuit is connected to an input end of the filter circuit; and

the three-level switch circuit includes a switch unit UC 1 and a switch unit UC 4 , one end of the UC 1 is connected to the P, another end of the UC 1 is connected to the UREF, an output end of the UC 1 is X 1 , the UC 1 includes a first switching transistor Q 1 connected between the P and the X 1 , one end of the UC 4 is connected to the N, another end of the UC 4 is connected to the UREF, an output end of the UC 4 is X 4 , and the UC 4 includes a first switching transistor Q 4 connected between the DC voltage output end N and the X 4 ; and the three-level switch circuit further includes a second switching transistor Q 2 connected between the X 1 and the SM, a second switching transistor Q 3 connected between the X 4 and the SM, a third switching transistor S 1 connected between the P and the SM, and a third switching transistor S 2 connected between the N and the SM, where the Q 1 , Q 2 , Q 3 , Q 4 , S 1 , and S 2 each include a transistor, each of the transistors is connected in parallel to a body diode, and a direction of the body diode is set as follows: the body diode is turned on when the transistor connected in parallel to the body diode is reverse biased.

While operating, all the switching transistors Q 1 , Q 2 , Q 3 , Q 4 , S 1 , and S 2 are controlled in an orderly manner by a control unit; turn-on and turn-off of different switching transistors are controlled, so as to output AC voltages VSs and alternating currents ISs with different magnitudes and directions.

A control process of the power conversion circuit in this embodiment of the present application includes a case in which the three-level switch circuit works in a positive half cycle of a pulse width modulation signal, and a case in which the three-level switch circuit works in a negative half cycle of a pulse width modulation signal. The following describes the control method provided in this embodiment of the present application, mainly from a perspective of the case in which the three-level switch circuit works in the positive half cycle of the pulse width modulation signal.

When the three-level switch circuit works in the positive half cycle of the pulse width modulation signal, the method includes the following steps: controlling all the transistors to be turned off, where a body diode of the S 1 , a body diode of the Q 1 , and a body diode of the Q 2 are all turned on based on a current freewheeling function of the resonant circuit; controlling the S 1 to be turned on, to set up a first working state of the power conversion circuit; and after the first working state lasts for a time length T 1 , controlling the Q 1 and the Q 2 to be turned on.

In this embodiment of the present application, the S 1 and the S 2 have a property of a low conduction loss, and the Q 1 , the Q 2 , the Q 3 , and the Q 4 have a property of a low turn-off loss.

It can be learned that, the power conversion circuit provided in this embodiment of the present application includes the three-level switch circuit and the resonant circuit. In a process of controlling the three-level switch circuit, when all the transistors are turned off, the body diodes of the related transistors (for example, the S 1 , the Q 1 , and the Q 2 ) are turned on based on the current freewheeling function of the resonant circuit, and voltages of the body diodes of the related transistor are a voltage drop across a diode (close to 0). Then, when the S 1 is being turned on, the S 1 has a zero-voltage switch (ZVS) characteristic in a turn-on process, and then, when the Q 1 and the Q 2 are being turned on, the Q 1 and the Q 2 also have a ZVS characteristic. This reduces switching losses of the related switching transistors in turn-on processes. In addition, because the S 1 is controlled to be turned on before the Q 1 and the Q 2 are turned on, when the Q 1 and the Q 2 are turned on, a small part of a current switches from a branch circuit in which the S 1 is located, to a branch circuit in which the Q 1 and the Q 2 are located, and impedance of the branch circuit in which the Q 1 and the Q 2 are located is greater than that of the branch circuit in which S 1 is located. Therefore, only an extremely small part of the current needs to be switched. This can avoid extra electromagnetic interference (EMI) resulting from a rapid change of the current in a short time, and reduce a current switching loss. In addition, after the S 1 the Q 1 , and the Q 2 are all turned on, a majority of the current flows through the S 1 , and the S 1 has the property of a low conduction loss. Therefore, a conduction loss in the circuit can be greatly reduced. In other words, implementing this embodiment of the present application can reduce the switching loss, the conduction loss, and the current switching loss in the power conversion circuit at the same time.

With reference to the first aspect, in a first possible implementation, after the controlling the Q 1 and the Q 2 to be turned on, the method further includes a process of turning off the switching transistors.

A first possible turn-off process is: controlling the S 1 to be turned off before the Q 1 is turned off, and controlling the Q 1 to be turned off before the Q 2 is turned off, to switch from the first working state to a second working state.

A second possible turn-off process is: controlling the S 1 to be turned off before the Q 2 is turned off, and controlling the Q 2 to be turned off before the Q 1 is turned off, to switch from the first working state to a second working state.

In this embodiment of the present application, a conduction loss of the S 1 is less than a sum of conduction losses of the Q 1 and the Q 2 , a conduction loss of the S 2 is less than a sum of conduction losses of the Q 3 and the Q 4 , a sum of turn-off losses of the Q 1 and the Q 2 is less than a turn-off loss of the S 1 , and a sum of turn-off losses of the Q 3 and the Q 4 is less than a turn-off loss of the S 2 . Therefore, in the process of turning off the switching transistors, the S 1 is controlled to be turned off before the Q 1 and the Q 2 are turned off, and at last, the Q 1 and the Q 2 are turned off. Because the Q 1 and the Q 2 have a low turn-off loss, a switching loss in the turn-off process is reduced.

With reference to the first aspect, in a second possible implementation, a circuit structure of the three-level switch circuit has a plurality of implementation forms. In a possible circuit structure, the UC 1 further includes a diode DH connected between the UREF and the X 1 , where the DH is configured to set up the second working state when the S 1 and the Q 1 are both turned off; and the UC 4 further includes a diode DB connected between the UREF and the X 4 . A turn-off process for this circuit structure may be designed by referring to the first possible turn-off process.

With reference to the second possible implementation of the first aspect, in a possible implementation, the three-level switch circuit has a plurality of variant structures. In a variant structure, a transistor K 1 and a transistor K 2 are added to the three-level switch circuit described in the first aspect. The K 1 is connected in parallel to a body diode KD 1 , and a direction of the KD 1 is set as follows: the KD 1 is turned on when the K 1 is reverse biased. The K 2 is connected in parallel to a body diode KD 2 , and a direction of the KD 2 is set as follows: the KD 2 is turned on when the K 2 is reverse biased. A collector of the K 1 is connected to a connection point between the DH and the DB, an emitter of the K 1 is connected to an emitter of the K 2 , and a collector of the K 2 is connected to a connection point between the Q 2 and the Q 3 , so as to be connected to the SM. The K 1 and the K 2 are configured to set up the second working state when the S 1 and the Q 1 are both turned off. A turn-off process for this circuit structure may be designed by referring to the first possible turn-off process.

With reference to the second possible implementation of the first aspect, in another variant structure, in the three-level switch circuit, a transistor Q 5 and a transistor Q 6 are used in place of the DH and the DB. The Q 5 is connected in parallel to a body diode D 5 , and a direction of the D 5 is set as follows: the D 5 is turned on when the Q 5 is reverse biased. The Q 6 is connected in parallel to a body diode D 6 , and a direction of the D 6 is set as follows: the D 6 is turned on when the Q 6 is reverse biased. A collector of the Q 5 is connected to the output end X 1 of the UC 1 , and an emitter of the Q 5 is connected to the UREF. An emitter of the Q 6 is connected to the output end X 4 of the UC 4 , and a collector of the Q 6 is connected to the UREF. The Q 6 is configured to set up the second working state when the S 1 and the Q 2 are both turned off. A turn-off process for this circuit structure may be designed by referring to the second possible turn-off process.

With reference to the second possible implementation of the first aspect, in another variant structure, in the three-level switch circuit, the UC 1 and the UC 4 include a capacitor C connected between the X 1 and the X 4 , where the capacitor C is used in place of the DH and the DB. One end of the capacitor C is connected to the output end X 1 of the UC 1 , and another end of the capacitor C is connected to the output end X 4 of the UC 4 . The capacitor C is configured to set up the second working state when the S 1 and the Q 2 are both turned off. A turn-off process for this circuit structure may be designed by referring to the second possible turn-off process.

With reference to the first aspect, in a third possible implementation, referring to the implementation processes of the foregoing circuit structures and the control method, when the three-level switch circuit works in the negative half cycle of the pulse width modulation signal, the method further includes the following steps: controlling all the transistors to be turned off, where the body diodes are turned on based on the current freewheeling function of the resonant circuit; controlling the S 2 to be turned on, to set up a third working state of the power conversion circuit; and after the third working state lasts for a time length T 2 , controlling the Q 3 and the Q 4 to be turned on.

With reference to the third possible implementation of the first aspect, after the controlling the Q 3 and the Q 4 to be turned on, the method further includes a process of turning off the switching transistors, where the process includes: controlling the S 2 to be turned off before the Q 4 is turned off, and controlling the Q 4 to be turned off before the Q 3 is turned off, to switch from the third working state to a fourth working state.

According to a second aspect, an embodiment of the present application provides a power conversion circuit, where the power conversion circuit includes a three-level switch circuit, a resonant circuit, a transformer, a rectifier circuit, and a filter circuit, three input ends of the three-level switch circuit are respectively connected to a DC voltage output end P, a reference voltage output end UREF, and a DC voltage output end N, an output end SM of the three-level switch circuit is connected to an input end of the resonant circuit, an output end of the resonant circuit is connected to a primary-side winding of the transformer, a secondary-side winding of the transformer is connected to an input end of the rectifier circuit, and an output end of the rectifier circuit is connected to an input end of the filter circuit;

the three-level switch circuit includes a switch unit UC 1 and a switch unit UC 4 , one end of the UC 1 is connected to the P, another end of the UC 1 is connected to the UREF, an output end of the UC 1 is X 1 , the UC 1 includes a first switching transistor Q 1 connected between the P and the X 1 , one end of the UC 4 is connected to the N, another end of the UC 4 is connected to the UREF, an output end of the UC 4 is X 4 , and the UC 4 includes a first switching transistor Q 4 connected between the DC voltage output end N and the X 4 ; and

the three-level switch circuit further includes a second switching transistor Q 2 connected between the X 1 and the SM, a second switching transistor Q 3 connected between the X 4 and the SM, a third switching transistor S 1 connected between the P and the SM, and a third switching transistor S 2 connected between the N and the SM, where the Q 1 , Q 2 , Q 3 , Q 4 , S 1 , and S 2 each include a transistor, each of the transistors is connected in parallel to a body diode, and a direction of the body diode is set as follows: the body diode is turned on when the transistor is reverse biased; and the power conversion circuit is configured to implement the method according to any one of the first aspect or the possible implementations of the first aspect.

With reference to the second aspect, in a possible implementation, the UC 1 further includes a diode DH connected between the UREF and the X 1 , where DH is configured to set up the second working state when the S 1 and the Q 1 are both turned off; and the UC 4 further includes a diode DB connected between the UREF and the X 4 .

In a possible embodiment, besides the DH and the DB, the three-level switch circuit further includes a transistor K 1 and a transistor K 2 connected between the UREF and the SM; the K 1 and the K 2 are respectively connected in parallel to a body diode KD 1 and a body diode KD 2 ; a direction of the KD 1 is set as follows: the KD 1 is turned on when the K 1 is reverse biased; and a direction of the KD 2 is set as follows: the KD 2 is turned on when the K 2 is reverse biased.

With reference to the second aspect, in a possible implementation, the UC 1 further includes a transistor Q 5 connected between the UREF and the X 1 ; the Q 5 is connected in parallel to a body diode D 5 ; a direction of the D 5 is set as follows: the D 5 is turned on when the Q 5 is reverse biased; the UC 4 further includes a transistor Q 6 connected between the UREF and the X 4 ; the Q 6 is connected in parallel to a body diode D 6 ; and a direction of the D 6 is set as follows: the D 6 is turned on when the Q 6 is reverse biased.

With reference to the second aspect, in a possible implementation, the UC 1 and the UC 4 include a capacitor C connected between the X 1 and the X 4 .

According to a third aspect, an embodiment of the present application provides a chopper. The chopper includes a three-level switch circuit and a resonant circuit, where the three-level switch circuit is specifically the three-level switch circuit described in the second aspect, and the resonant circuit is specifically the resonant circuit described in the second aspect.

According to a fourth aspect, an embodiment of the present application further provides a non-volatile storage medium, where the non-volatile storage medium is configured to store an instruction used to implement the method according to any one of the first aspect or the possible implementations of the first aspect.

It can be learned that, in a process of controlling the transistors in the power conversion circuit in the embodiments of the present application, when all the transistors are turned off, the body diodes of the related transistors (for example, the S 1 , the Q 1 , and the Q 2 ) are turned on based on the current freewheeling function of the resonant circuit, the voltages of the body diodes of the related transistor are a voltage drop across a diode (close to 0). Then, when the S 1 is being turned on, the S 1 has the ZVS characteristic in the turn-on process, and then, when the Q 1 and the Q 2 are being turned on, the Q 1 and the Q 2 also have the ZVS characteristic. This reduces the switching losses in the turn-on processes. In addition, in the embodiments of the present application, a transistor with a low conduction loss is used for the S 1 , and transistors with a low turn-off loss are used for the Q 1 and the Q 2 . In a conducted state, a majority of a current flows through the S 1 , and therefore, a conduction loss in the circuit can be greatly reduced. Because the S 1 is controlled to be turned on before the Q 1 and the Q 2 are turned on, when the Q 1 and the Q 2 are turned on, in a process in which the current switches from a path 1 to a path 2 , only an extremely small part of the current needs to be switched. This can avoid extra EMI resulting from a rapid change of the current in a short time, and reduce a current switching loss. Finally, in the turn-off process, the S 1 is controlled to be turned off before the Q 1 and the Q 2 are turned off, and at last, the Q 1 and the Q 2 are turned off. Because the Q 1 and the Q 2 have a low turn-off loss, the switching loss in the turn-off process is reduced.

FIG. 1 is a structural diagram of a framework of a power conversion circuit according to an embodiment of the present application;

FIG. 2 is a structural diagram of a framework of another power conversion circuit according to an embodiment of the present application;

FIG. 3 is a schematic structural diagram of a power conversion circuit according to an embodiment of the present application;

FIG. 4 is a schematic logic diagram of a control unit according to an embodiment of the present application;

FIG. 5 is a schematic flowchart of a control method of a power conversion circuit according to an embodiment of the present application;

FIG. 6 is a schematic diagram of an application scenario of a power conversion circuit according to an embodiment of the present application;

FIG. 7 is a schematic diagram of an application scenario of a power conversion circuit according to an embodiment of the present application;

FIG. 8 is a schematic diagram of an application scenario of a power conversion circuit according to an embodiment of the present application;

FIG. 9 is a schematic diagram of signal control and electric-property changes of some transistors according to an embodiment of the present application;

FIG. 10 is a schematic structural diagram of another power conversion circuit according to an embodiment of the present application;

FIG. 11 is a schematic diagram of signal control of some transistors according to an embodiment of the present application;

FIG. 12 is a schematic structural diagram of another power conversion circuit according to an embodiment of the present application;

FIG. 13 is a schematic diagram of signal control of some transistors according to an embodiment of the present application;

FIG. 14 is a schematic structural diagram of another power conversion circuit according to an embodiment of the present application; and

FIG. 15 is a schematic diagram of signal control of some transistors according to an embodiment of the present application.

The following describes related embodiments of the present application with reference to accompanying drawings.

A power conversion circuit provided in an embodiment of the present application is first described. As shown in FIG. 1 , the power conversion circuit proposed in this embodiment of the present application includes an input power source 1 , a voltage divider circuit 2 , a three-level switch circuit 3 , a resonant circuit 4 , a transformer 5 , a rectifier circuit 6 , and a filter circuit 7 . These circuits are sequentially connected. The three-level switch circuit 3 and the resonant circuit 4 form a chopper in this embodiment of the present application. Specifically, the input power source 1 , for example, may be a DC power source, and the input power source 1 is connected to the voltage divider circuit 2 . The voltage divider circuit 2 is configured to perform voltage division on the input power source. The voltage divider circuit 2 may include a plurality of voltage divider capacitors connected in series, for example, may include two voltage divider capacitors C 1 and C 2 connected in series. The chopper includes the three-level switch circuit 3 and the resonant circuit 4 , and is configured to convert an input direct current to a sinusoidal alternating current, and provide an AC voltage VS and a current IS on an output phase wire. Specifically, the three-level switch circuit includes a group of power switching transistors, a group of diodes, and (or) a group of capacitors. An output of the three-level switch circuit 3 is connected to the voltage divider circuit, to be specific, input ends of the three-level switch circuit 3 are respectively connected to three voltage output ends provided by the voltage divider circuit 2 : a DC voltage output end P, a reference voltage output end UREF, and a DC voltage output end N. An output of the three-level switch circuit 3 is connected to an input of the resonant circuit 4 . The resonant circuit 4 includes an inductor and a capacitor, and the inductor and the capacitor are connected in series to form a resonant cavity (for example, the resonant circuit 4 is an LLC resonant circuit). One end of the resonant cavity is connected to a middle point of the three-level switch circuit 3 , and another end of the resonant cavity is connected to the UREF (a middle point between the voltage divider capacitor C 1 and the voltage divider capacitor C 2 ) in the voltage divider circuit after passing through a primary-side winding of the transformer. The primary-side winding of the transformer 5 is connected to an output of the resonant circuit 4 , and a secondary-side winding of the transformer is connected to the rectifier circuit 6 . Specifically, the rectifier circuit 6 includes a rectifier bridge (a secondary side bridge arm) and is configured to rectify the input current. An output of the rectifier circuit 6 is connected to an input of the filter circuit 7 . The filter circuit 7 includes a capacitor and is configured to filter the input current.

It should be noted that, the related circuits and connection relationships in the power conversion circuit shown in FIG. 1 are merely examples of this embodiment of the present application, and impose no limitation. In actual application, the power conversion circuit may have a plurality of implementations. For example, referring to FIG. 2 , in an implementation, the foregoing related circuits proposed in this embodiment of the present application form a three-phase power conversion circuit. The three-phase power conversion circuit also includes the input power source 1 , the voltage divider circuit 2 , the three-level switch circuit 3 , the resonant circuit 4 , the transformer 5 , the rectifier circuit 6 , and the filter circuit 7 . However, a few of the circuits have different circuit deployments and circuit connections. To be specific, the three-level switch circuit includes a three-level switch circuit 31 , a three-level switch circuit 32 , and a three-level switch circuit 33 connected in parallel, and the resonant circuit includes a resonant circuit 41 , a resonant circuit 42 , and a resonant circuit 43 connected in parallel. Middle points of the three-level switch circuit 31 , the three-level switch circuit 32 and the three-level switch circuit 33 are respectively connected to the resonant circuit 41 , the resonant circuit 42 , and the resonant circuit 43 , to provide a three-phase input to the primary-side winding of the transformer. The secondary-side winding of the transformer provides a three-phase output to a rectifier circuit 61 , a rectifier circuit 62 , and a rectifier circuit 63 . After being rectified, all of the output is output to the filter circuit for filtering.

In the chopper that includes the three-level switch circuit and the resonant circuit, the three voltage output ends (N, UREF, and P) provided by the voltage divider circuit provide inputs to the three-level switch circuit, and an output end SM of the three-level switch circuit outputs, for different working states, voltages which are −U/2, UREF, and +U/2. Referring to FIG. 3 , in a specific implementation, the three-level switch circuit includes two switch units: a switch unit UC 1 and a switch unit UC 4 that are controlled by a control unit (shown in FIG. 4 ). One end of the switch unit UC 1 is connected to a positive DC voltage input end P of a positive voltage source, another end of the switch unit UC 1 is connected to a reference voltage output end UREF, and an output end of the UC 1 is X 1 . One end of the switch unit UC 4 is connected to a negative DC voltage input end N, another end of the switch unit UC 4 is connected to the reference voltage output end UREF, and an output end of the UC 4 is X 4 . Specifically, the UC 1 includes a first switching transistor Q 1 , and the Q 1 is a transistor. A collector of the Q 1 is connected to the P, and an emitter of the Q 1 is connected to the output end X 1 . The Q 1 is connected in parallel to a body diode D 1 , and a direction of the D 1 is set as follows: the D 1 is turned on when the Q 1 is reverse biased. Optionally, the UC 1 further includes a diode DH. An anode of the DH is connected to the UREF, and a cathode of the DH is connected to the output end X 1 . The UC 4 includes a first switching transistor Q 4 , and the Q 4 is a transistor. An emitter of the Q 4 is connected to the N, and a collector of the Q 4 is connected to the output end X 4 . The Q 4 is connected in parallel to a body diode D 4 , and a direction of the D 4 is set as follows: the D 4 is turned on when the Q 4 is reverse biased. Optionally, the UC 4 further includes a diode DB. A cathode of the DB is connected to the UREF, and an anode of the DB is connected to the output end X 4 .

The shown three-level switch circuit further includes a second switching transistor Q 2 and a second switching transistor Q 3 that are controlled by the control unit. The Q 2 and the Q 3 are both transistors. A collector of the Q 2 is connected to the X 1 , and an emitter of the Q 2 is connected to the output end SM of the three-level switch circuit. The Q 2 is connected in parallel to a body diode D 2 , and a direction of the D 2 is set as follows: the D 2 is turned on when the Q 2 is reverse biased. An emitter of the Q 3 is connected to the X 4 , and a collector of the Q 3 is connected to the output end SM of the three-level switch circuit. The Q 3 is connected in parallel to a body diode D 3 , and a direction of the D 3 is set as follows: the D 3 is turned on when the Q 3 is reverse biased.

The three-level switch circuit further includes a third switching transistor S 1 and a third switching transistor S 2 that are controlled by the control unit. The S 1 and the S 2 are both transistors. A collector of the S 1 is connected to the P, and an emitter of the S 1 is connected to the SM. An emitter of the S 2 is connected to the N, and a collector of the S 2 is connected to the SM. One end of the resonant circuit is connected to the SM, and another end of the resonant circuit is connected to the UREF after passing through the primary-side winding of the transformer, to provide current freewheeling for the three-level switch circuit.

When the S 1 is turned on, and the transistor Q 1 in the switch unit UC 1 and the Q 2 are turned on, a voltage at the modulation signal output end SM is basically equal to a DC voltage (+U/2) at the voltage input end P for the UC 1 . This corresponds to a first working state of the three-level switch circuit. When the S 1 and the Q 1 are turned off, and the Q 2 remains turned on, a voltage at the output end SM is basically equal to a voltage of the reference voltage output end UREF ( 0 ). This corresponds to a second working state of the three-level switch circuit. When the S 2 is turned on, and the transistor Q 4 in the switch unit UC 4 and the Q 3 are turned on, a voltage at the output end SM is basically equal to a DC voltage (−U/2) at the voltage output end N for the UC 4 . This corresponds to a third working state of the three-level switch circuit. When the S 2 and the Q 4 are turned off, and the Q 3 remains turned on, a voltage at the output end SM is basically equal to the voltage of the reference voltage output end UREF ( 0 ). This corresponds to a fourth working state of the three-level switch circuit.

In an implementation, a conduction loss of the S 1 is less than a sum of conduction losses of the Q 1 and the Q 2 , a conduction loss of the S 2 is less than a sum of conduction losses of the Q 3 and the Q 4 , a sum of turn-off losses of the Q 1 and the Q 2 is less than a turn-off loss of the S 1 , and a sum of turn-off losses of the Q 3 and the Q 4 is less than a turn-off loss of the S 2 . In the first working state, a conduction voltage drop across the Q 1 and the Q 2 is greater than that across the S 1 , and therefore, a majority of a conducted current flows through the S 1 , and only a small part of the conducted current flows through the Q 1 and the Q 2 . Because the S 1 has a lower conduction loss, a conduction loss of the chopper can be greatly reduced during this conduction. Similarly, in the third working state, a conduction voltage drop across the Q 3 and the Q 4 is greater than that across the S 2 , and therefore, a majority of a conducted current flows through the S 2 , and only a small part of the conducted current flows through the Q 3 and the Q 4 . Because the S 2 has a lower conduction loss, a conduction loss of the chopper can be greatly reduced during this conduction.

In actual working mode, all the switching transistors Q 1 , Q 2 , Q 3 , Q 4 , S 1 , and S 2 are controlled in an orderly manner by the control unit; turn-on and turn-off of different switching transistors are controlled, so that the chopper outputs AC voltages VSs and alternating currents ISs with different magnitudes and directions. The following describes the control unit in this embodiment of the present application. FIG. 4 is a schematic diagram of controlling different switching transistors by the control unit provided in this embodiment of the present application. The control unit implements orderly control on the switching transistors Q 1 , Q 2 , Q 3 , Q 4 , S 1 , and S 2 by outputting pulse width modulation signals G 1 and G 2 . When the three-level switch circuit works in a positive half cycle of a pulse width modulation signal, the pulse width modulation signal G 1 is output. When the three-level switch circuit works in a negative half cycle of a pulse width modulation signal, the pulse width modulation signal G 2 is output. A pulse width modulation signal is usually a high frequency signal, and after being processed in the control unit, the pulse width modulation signal is converted to control signals that can be used to control the switching transistors directly. Control signals (control signals 1 to 6 shown in the figure) finally used for the different transistors are discrete logic signals consistent with the pulse width modulation signals G 1 and G 2 , that is, signals whose magnitudes can be equal to 0 or 1. After the pulse width modulation signal is converted to the control signals, when a magnitude of a control signal used for a control input end of a transistor is equal to 0, the transistor is turned off; when the magnitude is 1,the transistor is turned on.

In addition, delay modules (delay modules 1 to 4 shown in the figure) are further disposed in control branches in which the Q 1 , Q 2 , Q 3 , and Q 4 are located. The related delay modules are activated during trailing edges of the pulse width modulation signals G 1 and G 2 , and allow output ends of the delay modules to output the pulse width modulation signal after a delay of a preset time length T. The delay modules are configured, so that when the control signals converted from the pulse width modulation signal G 1 switch from 0 to 1, the S 1 is turned on, whereas the Q 1 will be turned on after a preset time length T 11 , and the Q 2 will be turned on after a preset time length T 21 ; when the control signals converted from the pulse width modulation signal G 1 switch from 1 to 0, the S 1 is turned off, whereas the Q 1 will be turned off after a preset time length T 12 , and the Q 2 will be turned off after a preset time length T 22 . Similarly, when the control signals converted from the pulse width modulation signal G 2 switch from 0 to 1, the S 2 is turned on, whereas the Q 3 will be turned on after a preset time length T 31 , and the Q 4 will be turned on after a preset time length T 41 ; when the control signals converted from the pulse width modulation signal G 2 switch from 1 to 0, the S 2 is turned off, whereas the Q 3 will be turned off after a preset time length T 32 , and the Q 4 will be turned off after a preset time length T 42 . It should be noted that, the time lengths of T 11 , T 12 , T 21 , T 22 , T 31 , T 32 , T 41 , and T 42 may be the same or may be different, and values of these preset time lengths are all greater than or equal to 0.

Based on the chopper, the power conversion circuit, and the control unit that are described above, the following describes a control method of the power conversion circuit (namely, a chopper control method) provided in an embodiment of the present application. The method includes a case in which the three-level switch circuit works in a positive half cycle of a pulse width modulation signal, and a case in which the three-level switch circuit works in a negative half cycle of a pulse width modulation signal. The following describes the control method for the case in which the three-level switch circuit works in the positive half cycle of the pulse width modulation signal. Apparently, a person skilled in the art can easily obtain, based on the descriptions, related information about the case in which the three-level switch circuit works in the negative half cycle of the pulse width modulation signal, and therefore, details are not described in the following. In addition, for ease of solution description, a direction in which a current flows from the output end SM to the resonant circuit may be predefined as a positive direction. Referring to FIG. 5 , the method includes but is not limited to the following steps.

S 101 : Control all the switching transistors Q 1 , Q 2 , Q 3 , Q 4 , S 1 , and S 2 to be off

When a powered-on inductive load is powered off, a strong inductive load (for example, a coil) in the resonant circuit generates an electromotive force. In this case, the strong inductive load, serving as a power source, and a branch circuit of the three-level switch circuit form a loop that continuously supplies a current, so as to generate a current freewheeling loop. For example, referring to FIG. 6 , each of the Q 1 , the Q 2 , and the S 1 is connected in parallel to a reverse body diode, and therefore, the current freewheeling loop includes a branch circuit “resonant circuit-DS 1 -P” and a branch circuit “resonant-D 2 -D 1 -P”. To be specific, body diodes DS 1 , D 2 and D 1 are turned on, and at this moment, voltages of the S 1 (or Q 1 +Q 2 ) are low (only a voltage drop across a diode). This provides a zero-voltage switch (ZVS) condition for turning on the S 1 or the Q 1 and the Q 2 at a next moment.

S 102 : Control the switching transistor S 1 to be turned on.

The body diode of the S 1 is already on before the S 1 is turned on, and therefore, the S 1 is turned on at a zero voltage (or a voltage close to a zero voltage), so that the S 1 has a ZVS characteristic, and a conduction loss of the S 1 is low in a turn-on process. Referring to FIG. 7 , after the S 1 is turned on, the current continues to flow through the S 1 and the output end SM to the resonant circuit. The S 1 has an attribute of a low conduction voltage drop, and therefore, after the S 1 is turned on, a conduction loss resulting from the current on the S 1 is low.

After the S 1 is turned on, the three-level switch circuit sets up a first working state. In this case, the S 1 transmits power from the end P to the end SM, that is, the end SM may output a DC voltage (+U/2) to a subsequent circuit.

S 103 : After the switching transistor S 1 is in an on state for a period of time, control the switching transistors Q 1 and Q 2 to be turned on with a delay. A turn-on time of the Q 1 and a turn-on time of the Q 2 may be the same, or may be different.

After the Q 1 and the Q 2 are both turned on, because a conduction voltage drop across the Q 1 and the Q 2 is large, only a small part of the current flows through the Q 1 and the Q 2 , and a majority of the current still flows through the S 1 . Referring to FIG. 8 , the majority of the current flows through a path 1 , the small part of the current flows through a path 2 , and the two parts of the current converge at the output end SM and flow to the resonant circuit. Therefore, in this process, a conduction loss generated by the Q 1 and the Q 2 is also low.

It should be noted that, in actual application, delayed turn-on times of the Q 1 and the Q 2 may be adjusted based on optimal working states of the Q 1 , Q 2 , and the S 1 , so as to reduce a conduction loss of the three-level switch circuit to the greatest extent possible.

After the S 1 , the Q 1 , and the Q 2 are turned on, the three-level switch circuit remains in the first working state. In this case, the S 1 , the Q 1 , and the Q 2 together transmit power (the S 1 transmits a majority of the power) from the end P to the end SM, that is, the end SM may output a DC voltage (+U/2) to a subsequent circuit.

S 104 : Control the switching transistor S 1 to be turned off before the Q 1 and the Q 2 are turned off

Because the Q 1 and the Q 2 are turned off with a delay, at this moment, the Q 1 and the Q 2 still remain in an on state. Therefore, when the S 1 is turned off, the current flowing through the S 1 decreases to 0, whereas the current flowing through the Q 1 and the Q 2 increases. In this case, the three-level switch circuit still remains in the first working state.

S 105 : Control the switching transistor Q 1 to be turned off

In a possible embodiment, for example, in the embodiment shown in FIG. 3 , when the Q 1 is turned off, the Q 2 is still in an on state, and the three-level switch circuit switches from the first working state to a second working state. In this case, the current loop includes “UREF-DH-Q 2 -SM”, in other words, the SM outputs a level to the UREF.

S 106 : Control the switching transistor Q 2 to be turned off. After the Q 2 is turned off, all the switching transistors are in an off state again, and wait to be turned on in a next cycle.

It should be noted that, in a possible embodiment, step S 105 is enabled before step S 106 ; in another possible embodiment, step S 106 may alternatively be enabled before step S 105 . In other words, the Q 1 may be controlled to be turned off before the Q 2 is turned off, based to an actual circuit structure (for example, a circuit structure shown in FIG. 3 ) of the switch unit UC 1 . Alternatively, the Q 2 may be controlled to be turned off before the Q 1 is turned off, based on an actual circuit structure (for example, the following circuit structures shown in FIG. 12 and FIG. 14 ) of the switch unit UC 1 . This is not limited in this embodiment of the present application.

For better understanding of the control method described in this embodiment of the present application, the following describes electric-property changes of related switching transistors in a control process with reference to related accompanying drawings. FIG. 9 shows time sequence control and electric-property change statuses of the related switching transistors (S 1 , Q 1 , Q 2 ) when the three-level switch circuit works in a positive half cycle of a pulse width modulation signal. A person skilled in the art can easily infer, from descriptions about electric-property control in this case, descriptions about a case in which the three-level switch circuit works in a negative half cycle of a pulse width modulation signal. Therefore, details about time sequence control and electric-property change statuses of the related switching transistors (S 1 , Q 1 , Q 2 ) in the case of the negative half cycle are not described.

FIG. 9 shows control time sequences of related signals of the control unit. The control unit periodically outputs pulse width modulation signals GS 1 , GQ 1 , and GQ 2 to the S 1 , the Q 1 , and the Q 2 , respectively. When a magnitude of a control signal converted from a pulse width modulation signal is 1, a corresponding switching transistor is turned on. When a magnitude of a control signal converted from a pulse width modulation signal is 0, a corresponding switching transistor is turned off. FIG. 9 further shows change statuses of currents flowing through the related switching transistors (S 1 , Q 1 , and Q 2 ) under control of the input signals, and shows change statuses of voltages of the Q 1 and the Q 2 (or at two ends of the S 1 ) under control of the input signals, that is, a change status of a voltage between the connection point P and the connection point SM.

As shown in FIG. 9 , it is assumed that, before a time t 1 , the S 1 , the Q 1 , and the Q 2 are all in an on state. In this case, the three-level switch circuit is in the first working state, and the end SM outputs a voltage +U/2. Because a conduction voltage drop across the Q 1 and the Q 2 is large, a small part of the current flows through the Q 1 and the Q 2 , where IQ 1 and IQ 2 are smaller, and a majority of the current still flows through the S 1 , where IS 1 is larger. Because the S 1 has a property of a low conduction loss, a conduction loss in the three-level switch circuit is relatively low. At this moment, the voltages of the Q 1 and the Q 2 (the voltages of the S 1 ) are also relatively small and close to 0.

At the time t 1 , the pulse width modulation signal GS 1 for the S 1 changes to 0, in other words, a control signal converted from the pulse width modulation signal GS 1 changes to 0, and therefore, the S 1 is turned off; however, the pulse width modulation signal for the Q 2 is delayed to t 2 due to a delay module, and the pulse width modulation signal for the Q 3 is delayed to t 3 due to a delay module. After the S 1 is turned off, before the time t 2 , power between the P and the SM is transmitted through the Q 1 and the Q 2 , so that currents IQ 1 and IQ 2 correspondingly increase. The voltages of the Q 1 and the Q 2 (the voltages of the S 1 ) are also relatively small and close to 0. In this case, the three-level switch circuit is in the first working state, and the end SM outputs the voltage +U/2.

At the time t 2 , the pulse width modulation signal GQ 1 for the Q 1 changes to 0, in other words, a control signal converted from the pulse width modulation signal GQ 1 changes to 0, and therefore, the Q 1 is turned off. The three-level switch circuit starts to switch to the loop “UREF-DH-Q 2 -SM”, and the three-level switch circuit switches from the first working state to the second working state. The IQ 2 starts to decrease, and the voltages of the Q 1 and the Q 2 (the voltages of the S 1 ) start to increase. Because the Q 1 and the Q 2 have an attribute of a low turn-off loss, a turn-off loss of the Q 1 is low in this process.

At the time t 3 , the Q 2 is turned off, and the voltages of the Q 1 and the Q 2 (the voltages of the S 1 ) increase to a maximum magnitude (+U/2). It should be noted that, after the Q 2 is turned off, in a time period from t 3 to t 4 , the three-level switch circuit may perform related control actions in the negative half cycle of the pulse width modulation signal, and details are not described herein.

In a time period from t 4 to t 5 , after the related control actions in the negative half cycle are completed, all the switching transistors Q 1 , Q 2 , Q 3 , Q 4 , S 1 , and S 2 are controlled to be off. A strong inductive load in the resonant circuit generates an electromotive force. In this case, the strong inductive load, serving as a power source, and a branch circuit of the three-level switch circuit form a loop that continuously supplies a current, so as to generate a current freewheeling loop. The voltages of the Q 1 and the Q 2 (the voltages of the S 1 ) start to decrease, and even reverse. Because each of the Q 1 , the Q 2 , and the S 1 is connected in parallel to a reverse body diode, the current freewheeling loop includes a branch circuit “resonant circuit-DS 1 -P” and a branch circuit “resonant circuit-D 2 -D 1 -P”, and a direction of a current is a negative direction. The diodes DS 1 , D 2 , and D 1 are turned on. At this moment, the voltages of the S 1 and the voltages of the Q 1 and the Q 2 are low (only a voltage drop across a diode). This provides a ZVS condition for turning on the S 1 at a next moment.

At the time t 5 , the control signal converted from the pulse width modulation signal GS 1 for the S 1 changes to 1, and therefore, the S 1 is turned on. The current IS 1 flowing through the S 1 increases from 0. At this moment, because the voltages of the S 1 are small (close to 0), the S 1 has a ZVS characteristic in a turn-on process, and a conduction loss of the S 1 is low. After the S 1 is turned on, the current flowing through the S 1 increases rapidly. The S 1 has the attribute of a low conduction voltage drop, and therefore, after the S 1 is turned on, a conduction loss resulting from the current on the S 1 is low. In this case, the three-level switch circuit sets up the first working state. The S 1 transmits power from the end P to the end SM, and the end SM may output a DC voltage (+U/2) to a subsequent circuit. The voltages of the S 1 and the voltages of the Q 1 and the Q 2 are small (close to 0).

At a time t 6 , the control signal converted from the pulse width modulation signal GQ 1 for the Q 1 changes to 1, and therefore, the Q 1 is turned on; and a control signal converted from the pulse width modulation signal GQ 2 for the Q 2 changes to 1, and therefore, the Q 2 is turned on. When the Q 1 and the Q 2 are being turned on, the voltages of the Q 1 and the Q 2 are small (close to 0). Therefore, the Q 1 and the Q 2 also have a ZVS characteristic in a turn-on process. Because a conduction voltage drop across the Q 1 and the Q 2 is large, only a small part of the current flows through the Q 1 and the Q 2 , where IQ 1 and IQ 2 are smaller, and a majority of the current still flows through the S 1 , where IS 1 is larger. Because the S 1 has the property of a low conduction loss, a conduction loss in the three-level switch circuit is relatively low. In this case, the three-level switch circuit is in the first working state, and the end SM outputs the voltage +U/2.

It should be noted that, in this embodiment of the present application, time lengths of different time periods such as t 1 to t 2 , t 2 to t 3 , t 3 to t 4 , t 4 to t 5 , and t 5 to t 6 are all greater than or equal to 0, and the time lengths of the different time periods may be set depending on an actual application status.

The power conversion circuit provided in the embodiments of the present application includes the chopper, and the chopper further includes the three-level switch circuit and the resonant circuit. In a process of controlling the chopper, when all the transistors are turned off, the body diodes of the related transistors (for example, the S 1 , the Q 1 , and the Q 2 ) are turned on based on the current freewheeling function of the resonant circuit, and the voltages of the related transistor are a voltage drop across a diode (close to 0). Then, when the S 1 is being turned on, the S 1 has the ZVS characteristic in the turn-on process, and then, when the Q 1 and the Q 2 are being turned on, the Q 1 and the Q 2 also have the ZVS characteristic. This reduces switching losses in the turn-on processes. In addition, in the embodiments of the present application, a transistor with a low conduction loss is used for the S 1 , and transistors with a low turn-off loss are used for the Q 1 and the Q 2 . In a conducted state, the majority of the current flows through the S 1 , and therefore, the conduction loss in the circuit can be greatly reduced. Because the S 1 is controlled to be turned on before the Q 1 and the Q 2 are turned on, when the Q 1 and the Q 2 are turned on, in a process in which the current switches from the path 1 to the path 2 , only an extremely small part of the current needs to be switched. This can avoid extra electromagnetic interference (EMI) resulting from a rapid change of the current in a short time, and reduce a current switching loss. Finally, in a turn-off process, the S 1 is controlled to be turned off before the Q 1 and the Q 2 are turned off, and at last, the Q 1 and the Q 2 are turned off. Because the Q 1 and the Q 2 have the low turn-off loss, a switching loss in the turn-off process is reduced.

The following describes other power conversion circuit structures provided in embodiments of the present application. In the other power conversion circuit structures, corresponding three-level switch circuits have different circuit structures and possible different control manners of some switching transistors.

FIG. 10 is a diagram of a possible power conversion circuit structure. A difference between the power conversion circuit structure and the circuit structure shown in FIG. 3 lies in that a transistor K 1 and a transistor K 2 are added to a three-level switch circuit. The K 1 is connected in parallel to a body diode KD 1 , and a direction of the KD 1 is set as follows: the KD 1 is turned on when the K 1 is reverse biased. The K 2 is connected in parallel to a body diode KD 2 , and a direction of the KD 2 is set as follows: the KD 2 is turned on when the K 2 is reverse biased. A collector of the K 1 is connected to a connection point between DH and DB, an emitter of the K 1 is connected to an emitter of the K 2 , and a collector of the K 2 is connected to a connection point between Q 2 and Q 3 , so as to be connected to SM.

In this circuit structure, for a manner of controlling different transistors by a control unit, refer to FIG. 11 , for example. FIG. 11 shows pulse width modulation signals (GS 1 , GQ 1 , GQ 2 , and GK 1 ) that are respectively output by the control unit to S 1 , Q 1 , the Q 2 , and the K 1 . It can be learned that, in the control manner, in a turn-on phase of the S 1 , the Q 1 , and the Q 2 , the S 1 is controlled to be turned on before the Q 1 and the Q 2 are turned on, so that the three-level switch circuit sets up a first working state; and in a turn-off phase of the S 1 , the Q 1 , and the Q 2 , the S 1 is controlled to be turned off before the Q 1 is turned off, and then the Q 1 is controlled to be turned off before the Q 2 is turned off. In a time period in which the Q 1 is off but the Q 2 is not yet turned off, the K 1 is controlled to be turned on, so that the three-level switch circuit switches from the first working state to a second working state. At last, when the Q 2 is turned off, the K 1 is also turned off. For a specific analyzing process, refer to related descriptions in the embodiment of FIG. 9 , and details are not described herein again.

FIG. 12 is a diagram of a possible power conversion circuit structure. A difference between the power conversion circuit structure and the circuit structure shown in FIG. 3 lies in that, in a three-level switch circuit, a transistor Q 5 and a transistor Q 6 are used in place of the DH and the DB. The Q 5 is connected in parallel to a body diode D 5 , and a direction of the D 5 is set as follows: the D 5 is turned on when the Q 5 is reverse biased. The Q 6 is connected in parallel to a body diode D 6 , and a direction of the D 6 is set as follows: the D 6 is turned on when the Q 6 is reverse biased. A collector of the Q 5 is connected to an output end X 1 of UC 1 , and an emitter of the Q 5 is connected to UREF. An emitter of the Q 6 is connected to an output end X 4 of UC 4 , and a collector of the Q 6 is connected to the UREF.

In this circuit structure, for a manner of controlling different transistors by a control unit, refer to FIG. 13 , for example. FIG. 13 shows pulse width modulation signals (GS 1 , GQ 1 , GQ 2 , and GQ 6 ) that are respectively output by the control unit to S 1 , Q 1 , Q 2 , and the Q 6 . It can be learned that, in the control manner, in a turn-on phase of the S 1 , the Q 1 , and the Q 2 , the S 1 is controlled to be turned on before the Q 1 and the Q 2 are turned on, so that the three-level switch circuit sets up a first working state; and in a turn-off phase of the S 1 , the Q 1 , and the Q 2 , the S 1 is controlled to be turned off before the Q 2 is turned off, and then the Q 2 is controlled to be turned off before the Q 1 is turned off. In addition, when the Q 2 is to be turned off, the Q 6 is controlled to be turned on, so that the three-level switch circuit switches from the first working state to a second working state after the Q 2 is turned off. At last, when the Q 1 is turned off, the Q 6 is also turned off. For a specific analyzing process, refer to related descriptions in the embodiment of FIG. 9 , and details are not described herein again.

FIG. 14 is a diagram of a possible power conversion circuit structure. A difference between the power conversion circuit structure and the circuit structure shown in FIG. 3 includes the following: in a three-level switch circuit, a capacitor C is used in place of the DH and the DB. One end of the capacitor C is connected to an output end X 1 of UC 1 , and another end of the capacitor C is connected to an output end X 4 of UC 4 .

In this circuit structure, for a manner of controlling different transistors by a control unit, refer to FIG. 15 . FIG. 15 shows pulse width modulation signals (GS 1 , GQ 1 , and GQ 2 ) that are respectively output by the control unit to S 1 , Q 1 , and Q 2 . It can be learned that, in the control manner, in a turn-on phase of the S 1 , the Q 1 , and the Q 2 , the S 1 is controlled to be turned on before the Q 1 and the Q 2 are turned on, so that the three-level switch circuit sets up a first working state; and in a turn-off phase of the S 1 , the Q 1 , and the Q 2 , the S 1 is controlled to be turned off before the Q 2 is turned off, and then the Q 2 is controlled to be turned off before the Q 1 is turned off. In a period in which the Q 2 is off but the Q 1 is not yet turned off, the three-level switch circuit switches from the first working state to a second working state. For a specific analyzing process, refer to related descriptions in the embodiment of FIG. 9 , and details are not described herein again.

It should be noted that, in the foregoing embodiments, descriptions of each embodiment have a respective focus. For a part that is not described in detail in an embodiment, refer to related descriptions in other embodiments.