Semiconductor package including semiconductor chip having point symmetric chip pads

The present application claims priority under 35 U.S.C. 119(a) to Korean Application No. 10-2020-0017892, filed on Feb. 13, 2020, which is incorporated herein by references in its entirety.

1. Technical Field

The present disclosure generally relates to a semiconductor package and, more particularly, to a semiconductor chip having a chip pad of a point-symmetric structure and a semiconductor package including the same.

2. Related Art

The semiconductor industry has evolved to manufacture semiconductor products having light weight, small size, high speed, multi-functionality, high performance, and high reliability at low cost, and one of the important technologies to achieve this is semiconductor package technology. Semiconductor package technology is a technology of mounting a semiconductor chip having a circuit portion formed through a wafer process on a package substrate, a technology of securing an electrical connection between the semiconductor chip and an external electronic device through the package substrate, and a technology of protecting the semiconductor chip from an external environment.

Due to package products becoming lighter and shorter, studies are being conducted on connection pads for electrically connecting semiconductor chips to package substrates. The studies on the connection pads include studies on the design of package substrates and the pads disposed on the semiconductor chips.

A semiconductor package according to an aspect of the present disclosure may include a package substrate and a plurality of semiconductor chips stacked on the package substrate. Each of the semiconductor chips may include a chip body, at least one first side power pad and at least one first side ground pad that are disposed at a first side portion on one surface of the chip body, and at least one second side power pad and at least one second side ground pad that are disposed at a second side portion opposite to the first side portion on the one surface of the chip body. One of the at least one second side power pad may be disposed point-symmetrically to a corresponding one of the at least one first side power pad with respect to a reference point on the one surface of the chip body, and one of the at least one second side ground pad may be disposed point-symmetrically to a corresponding one of the at least one first side ground pad with respect to the reference point on the one surface of the chip body.

A semiconductor package according to another aspect of the present disclosure may include a package substrate, and a plurality of semiconductor chips stacked on the package substrate. Each of the semiconductor chips may include a chip body, at least one first side power pad, at least one first side ground pad, and at least one signal pad that are disposed at a first side portion on one surface of the chip body, and at least one second side power pad and at least one second side ground pad that are disposed at a second side portion opposite to the first side portion on the one surface of the chip body. One of the at least one second side power pad may be disposed point-symmetrically to a corresponding one of the at least one first side power pad with respect to a reference point on the one surface of the chip body, and one of the at least one second side ground pad may be disposed point-symmetrically to a corresponding one of the at least one first side ground pad with respect to the reference point on the one surface of the chip body.

A semiconductor package according to another aspect of the present disclosure may include a package substrate including a first bond finger array and a second bond finger array that are spaced apart from each other and arranged in a line, respectively. In addition, the semiconductor package may include a lower semiconductor chip disposed between the first and second bond finger arrays, and an upper semiconductor chip disposed on the lower semiconductor chip. The lower semiconductor chip and the upper semiconductor chip have substantially the same pad arrangement with each other. Each of the semiconductor chips may include a chip body, at least one first side power pad, at least one first side ground pad, and at least one signal pad that are disposed at a first side portion on one surface of the chip body, and at least one second side power pad and at least one second side ground pad that are disposed at a second side portion opposite to the first side portion on the one surface of the chip body. One of the at least one second side power pad may be disposed point-symmetrically to a corresponding one of the at least one first side power pad with respect to a reference point on the one surface of the chip body, and one of the at least one second side ground pad may be disposed point-symmetrically to a corresponding one of the at least one first side ground pad with respect to the reference point on the one surface of the chip body. The at least one first side power pad of the lower semiconductor chip and the at least one second side power pad of the upper semiconductor chip may be disposed to overlap each other, and the at least one first side ground pad of the lower semiconductor chip and the at least one second side ground pad of the upper semiconductor chip may be disposed to overlap each other.

FIG. 1 is a cross-sectional view schematically illustrating a semiconductor package according to an embodiment of the present disclosure.

FIG. 2 is a plan view schematically illustrating a package substrate according to an embodiment of the present disclosure.

FIG. 3 is view schematically illustrating a first semiconductor chip according to an embodiment of the present disclosure.

FIG. 4 is view schematically illustrating a second semiconductor chip according to an embodiment of the present disclosure.

FIGS. 5 and 6 are views schematically illustrating electrical connections between a package substrate and a semiconductor chip according to embodiments of the present disclosure.

The terms used herein may correspond to words selected in consideration of their functions in presented embodiments, and the meanings of the terms may be construed to be different according to one of ordinary skill in the art to which the embodiments belong. If defined in detail, the terms may be construed according to the definitions. Unless otherwise defined, the terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which associated embodiments belong. In the description of the present disclosure, words such as “first” and “second” and “upper” and “lower” are for distinguishing members, and are not used to limit the members themselves by implying a specific number or order of elements.

Same reference numerals refer to same elements throughout the specification. Even though a reference numeral is not indicated or described with reference to a drawing, the reference numeral may be indicated or described with reference to another drawing. In addition, even though a reference numeral is not shown in a drawing, it may be indicated or described with reference to another drawing.

In the specification of the present disclosure, a semiconductor package is illustrated using the orthogonal axes x-y-z of a right-handed Cartesian coordinate system. In this case, the x-direction may mean a direction parallel to the x-axis. Likewise, the y-direction and z-direction may mean directions parallel to the y-axis and the z-axis, respectively.

FIG. 1 is a cross-sectional view schematically illustrating a semiconductor package according to an embodiment of the present disclosure. Referring to FIG. 1 , the semiconductor package 1 may include a package substrate 100 and a plurality of semiconductor chips 200 and 300 stacked on the package substrate 100 . The plurality of semiconductor chips 200 and 300 may have substantially the same pad arrangement. As an example, the arrangement of power pads, ground pads, and signal pads of the plurality of semiconductor chips 200 and 300 may be substantially the same. In an embodiment, the plurality of semiconductor chips 200 and 300 may be chips of the same type. The package substrate 100 and the semiconductor chips 200 and 300 may be electrically connected by bonding wires 401 , 402 , 403 , and 404 .

The package substrate 100 may have a substrate body 110 . The substrate body 110 may have a first surface 110 S 1 and a second surface 110 S 2 opposite to the first surface 110 S 1 .

First and second bond finger arrays 120 a and 120 b may be disposed on the first surface 110 S 1 of the substrate body 110 . The first and second bond finger arrays 120 a and 120 b may each include a plurality of bond fingers (not illustrated) for wire-bonding with the semiconductor chips 200 and 300 . The plurality of bond fingers may include power fingers, ground fingers, and signal fingers. The first bond finger array 120 a may be disposed on a first side portion 110 E 1 of the substrate body 110 . The second bond finger array 120 b may be disposed on a second side portion 110 E 2 of the substrate body 110 . The arrangement of the plurality of bond fingers of the first and second bond finer arrays 120 a and 120 b will be described below using a plan view of FIG. 2 .

First and second connection structures 130 a and 130 b may be disposed on the second surface 110 S 2 of the substrate body 110 . The first and second connection structures 130 a and 130 b may be connected to an external printed circuit board or an external electronic system. Through the first and second connection structures 130 a and 130 b , the package substrate 100 may be supplied with power from the external printed circuit board or electronic system or exchange electrical signals with each other. In FIG. 1 , the number of the first and second connection structures 130 a and 130 b is shown as four, respectively, but is not limited thereto, and various other modifications are possible.

The first and second connection structures 130 a and 130 b may receive electric signals that are distinguished from each other from the external printed circuit board or the electronic system. That is, the electric signal received through any one of the first connection structures 130 a may be transmitted to the corresponding one of the signal fingers of the first bond finger array 120 a through first internal wirings 112 a 1 , 112 a 2 , and 112 a 3 . In addition, the electric signal received through any one of the second connection structures 130 b may be transmitted to the corresponding one of the signal fingers of the second bond finger array 120 b through second internal wirings 112 b 1 , 112 b 2 , and 112 b 3 . That is, an electrical signal path from the first connection structures 130 a to the signal fingers of the first bond finger array 120 a and an electrical signal path from the second connection structures 130 b to the signal fingers of the second bond finger array 120 b may be independent of each other. The first and second internal wirings 112 a 1 , 112 a 2 , 112 a 3 , 112 b 1 , 112 b 2 , and 112 b 3 may include first blind vias 112 a 1 and 112 b 1 , internal circuit layers 112 a 2 and 112 b 2 , and second blind vias 112 a 3 and 112 b 3 .

Referring to FIG. 1 , the plurality of semiconductor chips 200 and 300 , with the lower semiconductor chip 200 disposed on the package substrate 110 and the upper semiconductor chip 300 disposed on the lower semiconductor chip 200 , are disclosed. The package substrate 110 and the lower semiconductor chip 200 may be bonded by a first adhesive layer 510 . The lower semiconductor chip 200 and the upper semiconductor chip 300 may be bonded by a second adhesive layer 520 . The first and second adhesive layers 510 and 520 may each, for example, include a non-conductive paste or a non-conductive film.

The lower semiconductor chip 200 may have a chip body 210 . The chip body 210 may have a first surface 210 S 1 and a second surface 210 S 2 opposite to the first surface 210 S 1 . First and second chip pads 220 a and 220 b may be disposed on the first surface 210 S 1 of the chip body 210 . The first and second chip pads 220 a and 220 b may function as connection pads for wire bonding with the package substrate 100 . The first chip pad 220 a may be disposed on a first side portion 210 E 1 of the chip body 210 . The second chip pad 220 b may be disposed on a second side portion 210 E 2 of the chip body 210 . In an embodiment, the first chip pad 220 a and the second chip pad 220 b may each, for example, include a power pad and a ground pad. In addition, any one of the first chip pad 220 a and the second chip pad 220 b may further include a signal pad. As an example, as illustrated in a plan view of FIG. 3 , the first chip pad 220 a may have a power pad, a ground pad, and a signal pad, and the second chip pad 220 b may have a power pad and a ground pad. The pad arrangement of the first and second chip pads 220 a and 220 b will be described below in detail using the plan view of FIG. 3 .

Meanwhile, the first and second chip pads 220 a and 220 b may be connected to corresponding fingers of the first and second bond finger arrays 120 a and 120 b by first and second bonding wires 401 and 402 , respectively.

Referring to FIG. 1 , the upper semiconductor chip 300 may be stacked on the lower semiconductor chip 200 . The upper semiconductor chip 300 and the lower semiconductor chip 200 may have substantially the same pad arrangement. As an example, the arrangement of the power pads, ground pads, and signal pads of the upper semiconductor chip 300 and the lower semiconductor chip 200 may be substantially the same as each other. In an embodiment, the upper semiconductor chip 300 may be the same type of chip as the lower semiconductor chip 200 . As an example, the configuration of the upper semiconductor chip 300 may be substantially the same as that of the lower semiconductor chip 200 . In an embodiment, the upper semiconductor chip 300 may be disposed to overlap the lower semiconductor chip 200 . At this time, the first side portion 310 E 1 of the upper semiconductor chip 300 and the second side portion 210 E 2 of the lower semiconductor chip 200 may overlap, and the second side portion 310 E 2 of the upper semiconductor chip 300 and the first side portion 210 E 1 of the lower semiconductor chip 200 may overlap. In other words, as described later in connection with FIG. 6 , when the upper semiconductor chip 300 is staked on the lower semiconductor chip 200 , the upper semiconductor chip 300 may be stacked while being rotated 180° relative to the center point C 200 of the lower semiconductor chip 200 .

The upper semiconductor chip 300 may have a chip body 310 . The chip body 310 may have a first surface 310 S 1 and a second surface 310 S 1 opposite to the first surface 310 S 1 , First and second chip pads 320 a and 320 b may be disposed on the first surface 310 S 1 of the chip body 310 . The first and second chip pads 320 a and 320 b may function as connection pads for wire bonding with the package substrate 100 . The first chip pad 320 a may be disposed on a first side portion 310 E 1 of the chip body 310 . The second chip pad 320 b may be disposed on a second side portion 310 E 2 . In an embodiment, the first chip pad 320 a and the second chip pad 320 b may each include, for example, power pads and ground pads. In addition, any one of the first chip pad 320 a and the second chip pad 320 b may further include signal pads. As an example, as illustrated in a plan view of FIG. 4 , the first chip pad 320 a may have a power pad, a ground pad, and a signal pad, and the second chip pad 320 b may have power pads and ground pads. The pad arrangement of the first and second chip pads 320 a and 320 b will be described below in detail using the plan view of FIG. 4 .

The first chip pad 320 a may be connected to a corresponding finger in the second bond finger array 120 b by a fourth bonding wire 404 . Similarly, the second chip pad 320 b may be connected to a corresponding finger in the first bonding finger array 120 a by a third bonding wire 403 .

FIG. 2 is a plan view schematically illustrating a package substrate according to an embodiment of the present disclosure. The package substrate 100 of FIG. 2 may be the package substrate 100 of the semiconductor package 1 of FIG. 1 . Referring to FIGS. 1 and 2 , the package substrate 100 may include a substrate body 110 having a first surface 110 S 1 and a second surface 110 S 2 opposite to the first surface 110 S 1 . The substrate body 110 may have a length Li along the x-direction and a width W 1 along the y-direction. In addition, the package substrate 100 may have a central axis CX extending in the y-direction at ½ of the length Li.

First and second bond finger arrays 120 a and 120 b may be disposed on the first surface 110 S 1 of the substrate body 110 . The first bond finger array 120 a may be disposed on a first side portion 110 E 1 of the substrate body 110 , and the second bond finger array 120 b may be disposed on a second side portion 110 E 2 of the substrate body 110 . The first and second side portions 110 E 1 and 110 E 2 may be located outside a semiconductor chip mounting area 100 A in which the lower semiconductor chip 200 is disposed. The first and second side portions 110 E 1 and 110 E 2 may be located opposite to each other on the basis of the semiconductor chip mounting area 100 A. As described below in connection with FIGS. 3 and 5 , the first side portion 110 E 1 of the substrate body 110 may be disposed adjacent to the first side portion 210 E 1 of the lower semiconductor chip 200 , and the second side portion 110 E 2 of the substrate body 110 may be disposed adjacent to the second side portion 210 E 2 of the lower semiconductor chip 200 .

In an embodiment, the first bond finger array 120 a may include two power fingers 120 a P 1 and 120 a P 2 , two ground fingers 120 a G 1 and 120 a G 2 , and four signal fingers 120 a S 1 , 120 a S 2 , 120 a S 3 , and 120 a S 4 . The power fingers 120 a P 1 and 120 a P 2 , the ground fingers 120 a G 1 and 120 a G 2 , and the signal fingers 120 a S 1 , 120 a S 2 , 120 a S 3 , and 120 a S 4 may be aligned in a line LR 110 along one direction (i.e., the y-direction) at the first side portion 110 E 1 . When the power fingers 120 a P 1 and 120 a P 2 , the ground fingers 120 a G 1 and 120 a G 2 , and the signal fingers 120 a S 1 , 120 a S 2 , 120 a S 3 , and 120 a S 4 are aligned in a line LR 110 , the fingers adjacent to each other may be spaced apart from each other at a predetermined distance d 1 with respect to the y-direction.

As a specific example, the first bond finger array 120 a may include a first side first power finger 120 a P 1 , a first side first signal finger 120 a S 1 , a first side first ground finger 120 a G 1 , a first side second signal finger 120 a S 2 , a first side second power finger 120 a P 2 , a first side third signal finger 120 a S 3 , a first side second ground finger 120 a G 2 , and a first side fourth signal finger 120 a S 4 which are sequentially disposed along the y-direction.

Meanwhile, the number of the power fingers, the number of the ground fingers, and the number of the signal fingers of the first bond finger array 120 a may not necessarily be limited to the number described above. In an embodiment, the number of the power fingers, the number of the ground fingers, and the number of the signal fingers of the first bond finger array 120 a may be determined in correspondence with the number of power pads, the number of ground pads, and the number of signal pads disposed on the lower and upper semiconductor chips 200 and 300 , as described below with reference to FIGS. 3 and 4 .

In addition, the arrangement order of the power fingers, the ground fingers, and the signal fingers of the first bond finger array 120 a may not necessarily be limited to the above-described order. The arrangement order of the power fingers, the ground fingers, and the signal fingers of the first bond finger array 120 a may be determined in correspondence with the arrangement order of the power pads, the ground pads, and the signal pads disposed on the lower and upper semiconductor chips 200 and 300 , as described below with reference to FIGS. 3 to 6 .

Meanwhile, the second bond finger array 120 b may include two power fingers 120 b P 1 and 120 b P 2 , two ground fingers 120 b G 1 and 120 b G 2 , and four signal fingers 120 b S 1 , 120 b S 2 , 120 b S 3 , and 120 b S 4 . The power fingers 120 b P 1 and 120 b P 2 , the ground fingers 120 b G 1 and 120 b G 2 , and the signal fingers 120 b S 1 , 120 b S 2 , 120 b S 3 , and 120 b S 4 may be aligned in a line RR 110 along one direction (i.e., the y-direction) at the second side portion 110 E 2 . When the power fingers 120 b P 1 and 120 b P 2 , the ground fingers 120 b G 1 and 120 b G 2 , and the signal fingers 120 b S 1 , 120 b S 2 , 120 b S 3 and 120 b S 4 are aligned in a line RR 110 , the fingers adjacent to each other may be spaced apart from each other at a predetermined distance d 1 with respect to the y-direction.

As a specific example, the second bond finger array 120 b may include a second side fourth signal finger 120 b S 4 , a second side second ground finger 120 b G 2 , a second side third signal finger 120 b S 3 , a second side second power finger 120 b P 2 , a second side second signal finger 120 b S 2 , a second side first ground finger 120 b G 1 , a second side first signal finger 120 b S 1 , and a second side first power finger 120 b P 1 which are sequentially disposed along the y-direction.

Meanwhile, the number of the power fingers, the number of the ground fingers, and the number of the signal fingers of the second bond finger array 120 b may not necessarily be limited to the number described above. In an embodiment, the number of the power fingers, the number of the ground fingers, and the number of the signal fingers of the second bond finger array 120 b may be determined in correspondence with the number of power pads, the number of ground pads, and the number of signal pads disposed on the lower and upper semiconductor chips 200 and 300 , as described below with reference to FIGS. 3 and 4 .

In addition, the arrangement order of the power fingers, the ground fingers, and the signal fingers of the second bond finger array 120 b may not necessarily be limited to the above-described order. The arrangement order of the power fingers, the ground fingers, and the signal fingers of the second bond finger array 120 b may be determined in correspondence with the arrangement order of the power pads, the ground pads, and the signal pads disposed on the lower and upper semiconductor chips 200 and 300 , as described below with reference to FIGS. 3 to 6 .

In an embodiment, the positions of the pads of the first bond finger array 120 a aligned in the y-direction and the positions of the pads of the second bond finger array 120 b aligned in the y-direction may be symmetrical to each other with respect to the central axis CX.

In an embodiment, the signal fingers 120 a S 1 , 120 a S 2 , 120 a S 3 , and 120 a S 4 of the first bond finger array 120 a may be electrically separated from the signal fingers 120 b S 1 , 120 b S 2 , 120 b S 3 , and 120 b S 4 of the second bond finger array 120 b . In other words, the signal fingers 120 a S 1 , 120 a S 2 , 120 a S 3 , and 120 a S 4 of the first bond finger array 120 a and the signal fingers 120 b S 1 , 120 b S 2 , 120 b S 3 , and 120 b S 4 of the second bond finger array 120 b may constitute independent signal paths that are distinguished from each other. In an embodiment, referring back to FIG. 1 , the signal fingers 120 a S 1 , 120 a S 2 , 120 a S 3 , and 120 a S 4 of the first bond finger array 120 a may be connected to the first connection structures 130 a through the first internal wirings 112 a 1 , 112 a 2 , and 112 a 3 . The signal fingers 120 b S 1 , 120 b S 2 , 120 b S 3 , and 120 b S 4 of the second bond finger array 120 b may be connected to the second connection structures 130 b through the second internal wirings 112 b 1 , 112 b 2 , and 112 b 3 .

As described later with reference to FIGS. 5 and 6 , the signal fingers 120 a S 1 , 120 a S 2 , 120 a S 3 , and 120 a S 4 of the first bond finger array 120 a may be connected to the signal pads 220 a S 1 , 220 a S 2 , 220 a S 3 , and 220 a S 4 of the lower semiconductor chip 200 . On the other hand, the signal fingers 120 b S 1 , 120 b S 2 , 120 b S 3 , and 120 b S 4 of the second bond finger array 120 b may be connected to the signal pads 320 a S 1 , 320 a S 2 , 320 a S 3 , and 320 a S 4 of the upper semiconductor chip 300 . That is, data signal and address command signal for the lower semiconductor chip 200 can be transmitted through the signal fingers 120 a S 1 , 120 a S 2 , 120 a S 3 , and 120 a S 4 of the first bond finger array 120 a . In addition, data signal and address command signal for the upper semiconductor chip 300 can be transmitted through the signal fingers 120 b S 1 , 120 b S 2 , 120 b S 3 , and 120 b S 4 of the second bond finger array 120 b . As a result, each of the lower semiconductor chip 200 and the upper semiconductor chip 300 can exchange electric signals with the package substrate 100 by an independent signal path, respectively.

On the other hand, the power fingers 120 a P 1 and 120 a P 2 and the ground fingers 120 a G 1 and 120 a G 2 of the first bond finger array 120 a and the power fingers 120 b P 1 and 120 b P 2 and the ground fingers 120 b G 1 and 120 b G 2 of the second bond finger array 120 b may be shared by the lower semiconductor chip 200 and the upper semiconductor chip 300 , as described below in connection with FIG. 6 .

FIG. 3 is view schematically illustrating a first semiconductor chip according to an embodiment of the present disclosure. Referring to FIG. 3 , the first semiconductor chip 200 may be the lower semiconductor chip 200 described above with reference to FIG. 1 .

Referring to FIGS. 1 and 3 , the first semiconductor chip 200 may include a chip body 210 , a first chip pad 220 a disposed at a first side portion 210 E 1 on a first surface 210 S 1 of the chip body 210 , and a second chip pad 220 b disposed at a second side portion 210 E 2 on the first surface 210 S 1 of the chip body 210 .

In an embodiment, the first chip pad 220 a may include two power pads 220 a P 1 and 220 a P 2 , two ground pads 220 a G 1 and 220 a G 2 , and four signal pads 220 a S 1 , 220 a S 2 , 220 a S 3 , and 220 a S 4 . The power pads 220 a P 1 and 220 a P 2 , the ground pads 220 a G 1 and 220 a G 2 , and the signal pads 220 a S 1 , 220 a S 2 , 220 a S 3 , and 220 a S 4 may be aligned in a line LR 210 along one direction (i.e., the y-direction) at the first side portion 210 E 1 .

As a specific example, the first chip pad 220 a may include a first side first power pad 220 a P 1 , a first side first signal pad 220 a S 1 , a first side first ground pad 220 a G 1 , a first side second signal pad 220 a S 2 , a first side second power pad 220 a P 2 , a first side third signal pad 220 a S 3 , a first side second ground pad 220 a G 2 , and a first side fourth signal pad 220 a S 4 which are sequentially disposed along the y-direction.

Meanwhile, the number of the first side power pads, the number of the first side ground pads, and the number of the first side signal pads of the first chip pad 220 a may not necessarily be limited to the number described above. In addition, the arrangement order of the first side power pads, the number of the first side ground pads, and the number of the first side signal pads of the first chip pad 220 a may not necessarily be limited to the above-described order and various modifications are possible.

In an embodiment, the second chip pad 220 b may include two power pads 220 b P 1 and 220 b P 2 , and two ground pads 220 b G 1 and 220 b G 2 . The power pads 220 b P 1 and 220 b P 2 and the ground pads 220 b G 1 and 220 b G 2 may be aligned in a line RR 210 along one direction (i.e., the y-direction) at the second side portion 210 E 2 .

As a specific example, the second chip pad 220 b may include a second side second ground pad 220 b G 2 , a second side second power pad 220 b P 2 , a second side first ground pad 220 b G 1 , and a second side first power pad 220 b P 1 which are sequentially disposed along the y-direction. Meanwhile, the number of the second side power pads and the number of the second side ground pads of the second chip pad 220 b may be substantially the same as the number of the first side power pads and the number of the first side ground pads of the first chip pad 220 a . In addition, the second side power pads and the second side ground pads may be arranged to correspond to the first side power pads and the first side ground pads of the first chip pad 220 a . When compared to the first chip pad 220 a , the second chip pad 220 b may not include a signal pad.

In an embodiment, any one of the second side power pads 220 b P 1 and 220 b P 2 may be disposed point-symmetrically to the corresponding one of the first side power pads 220 a P 1 and 220 a P 2 with respect to a reference point C 210 on the first surface 210 S 1 . Any one of the second side ground pads 220 b G 1 and 220 b G 2 may be disposed point-symmetrically to the corresponding one of the first side ground pads 220 a G 1 and 220 a G 2 with respect to the reference point C 210 on the first surface 210 S 1 . Here, the reference point C 210 on the first surface 210 S 1 may be the center point of a shape of the chip body 210 that is projected onto the first surface 210 S 1 . As an example, when the chip body 210 has a rectangular shape on the first surface 210 S 1 , the center point may be an intersection of two diagonal lines connecting the vertices facing each other in the rectangle.

As a specific example, the first side first power pad 220 a P 1 and the second side first power pad 220 b P 1 may be disposed point-symmetrically to each other with respect to the reference point C 210 . The first side second power pad 220 a P 2 and the second side second power pad 220 b P 2 may be disposed point-symmetrically to each other with respect to the reference point C 210 . The first side first ground pad 220 a G 1 and the second side first ground pad 220 b G 1 may be disposed point-symmetrically to each other with respect to the reference point C 210 . The first side second ground pad 220 a G 2 and the second side second ground pad 220 b G 2 may be disposed point-symmetrically to each other with respect to the reference point C 210 .

In an embodiment, the first side first power pad 220 a P 1 and the second side first power pad 220 b P 1 may have the same shape. The first side second power pad 220 a P 2 and the second side second power pad 220 b P 2 have the same shape. The first side first ground pad 220 a G 1 and the second side first ground pad 220 b G 1 may have the same shape. The first side second ground pad 220 a G 2 and the second side second ground pad 220 b G 2 may have the same shape.

In an embodiment, when the first side first and second power pads 220 a P 1 and 220 a P 2 , the first side first and second ground pads 220 a G 1 and 220 a G 2 , and the first side first to fourth signal pads 220 a S 1 , 220 a S 2 , 220 a S 3 , and 220 a S 4 are aligned in a line LR 210 to have the arrangement order of FIG. 3 , the power pads and ground pads adjacent to each other may be spaced apart from each other at a predetermined distance d 2 in the y-direction. When the second side first and second power pads 220 b P 1 and 220 b P 2 , and the second side first and second ground pads 220 b G 1 and 220 b G 2 are aligned in a line RR 210 to have the arrangement order of FIG. 3 , the power pads and ground pads adjacent to each other may be spaced apart from each other at the predetermined distance d 2 in the y-direction.

FIG. 4 is view schematically illustrating a second semiconductor chip according to an embodiment of the present disclosure. Referring to FIG. 4 , the second semiconductor chip 300 may be the upper semiconductor chip 300 of the semiconductor package 1 described above in connection with FIG. 1 . The second semiconductor chip 300 of FIG. 4 may have substantially the same pad arrangement as the first semiconductor chip 200 of FIG. 3 . That is, the arrangement of the power pads, ground pads, and signal pads of the second semiconductor chip 300 may be substantially the same as that of the first semiconductor chip 200 . In an embodiment, the second semiconductor chip 300 may be the same type of chip as the first semiconductor chip 200 . The configuration of the second semiconductor chip 300 may be substantially the same as that of the first semiconductor chip 200 .

The second semiconductor chip 300 may include a chip body 310 , a first chip pad 320 a disposed at a first side portion 310 E 1 on a first surface 310 S 1 of the chip body 310 , and a second chip pad 320 b disposed at a second side portion 310 E 2 on the first surface 310 S 1 of the chip body 310 .

In an embodiment, the first chip pad 320 a may include first side first and second power pads 320 a P 1 and 320 a P 2 , first side first and second ground pads 320 a G 1 and 320 a G 2 , and first side first to fourth signal pads 320 a S 1 , 320 a S 2 , 320 a S 3 , and 320 a S 4 . The first side first and second power pads 320 a P 1 and 320 a P 2 , the first side first and second ground pads 320 a G 1 and 320 a G 2 , and the first side first to fourth signal pads 320 a S 1 , 320 a S 2 , 320 a S 3 , and 320 a S 4 may be aligned in a line LR 310 along one direction (i.e., the y-direction) at the first side portion 310 E 1 .

In an embodiment, the second chip pad 320 b may include second side first and second power pads 320 b P 1 and 320 b P 2 , and second side first and second ground pads 320 b G 1 and 320 b G 2 . The second side first and second power pads 320 b P 1 and 320 b P 2 and the second side first and second ground pads 320 b G 1 and 320 b G 2 may be aligned in a line RR 310 along one direction (i.e., the y-direction) at the second side portion 310 E 2 . When compared to the first chip pad 320 a , the second chip pad 320 b may not have the signal pads.

In an embodiment, any one of the second side power pads 320 b P 1 and 320 b P 2 may be disposed point-symmetrically to the corresponding one of the first side power pads 320 a P 1 and 320 a P 2 with respect to a reference point C 310 on the first surface 310 S 1 . Any one of the second side ground pads 320 b G 1 and 320 b G 2 may be disposed point-symmetrically to the corresponding one of the first side ground pads 320 a G 1 and 320 a G 2 with respect to the reference point C 310 on the first surface 310 S 1 . Here, the reference point C 310 on the first surface 310 S 1 may be the center point of a shape of the chip body 310 that is projected onto the first surface 310 S 1 . As an example, when the chip body 310 has a rectangular shape on the first surface 310 S 1 , the center point may be an intersection of two diagonal lines connecting the vertices facing each other in the rectangle.

As a specific example, the first side first power pad 320 a P 1 and the second side first power pad 320 b P 1 may be disposed point-symmetrically to each other with respect to the reference point C 310 . The first side second power pad 320 a P 2 and the second side second power pad 320 b P 2 may be disposed point-symmetrically to each other with respect to the reference point C 310 . The first side first ground pad 320 a G 1 and the second side first ground pad 320 b G 1 may be disposed point-symmetrically to each other with respect to the reference point C 310 . The first side second ground pad 320 a G 2 and the second side second ground pad 320 b G 2 may be disposed point-symmetrically to each other with respect to the reference point C 310 .

In an embodiment, when the first side first and second power pads 320 a P 1 and 320 a P 2 , the first side first and second ground pads 320 a G 1 and 320 a G 2 , and the first side first to fourth signal pads 320 a S 1 , 320 a S 2 , 320 a S 3 , and 320 a S 4 are aligned in a line LR 310 to have the arrangement order of FIG. 4 , the power pads and ground pads adjacent to each other may be spaced apart from each other at a predetermined distance d 3 in the y-direction. When the second side first and second power pads 320 b P 1 and 320 b P 2 and the second side first and second ground pads 320 b G 1 and 320 b G 2 are aligned in a line RR 310 to have the arrangement order of FIG. 4 , the power pads and ground pads adjacent to each other may be spaced apart from each other at the predetermined distance d 3 in the y-direction.

FIGS. 5 and 6 are views schematically illustrating electrical connections between a package substrate and a semiconductor chip according to an embodiment of the present disclosure. FIG. 5 is a view for explaining a form in which a lower semiconductor chip 200 is mounted on the package substrate 100 in the semiconductor package 1 described above with reference to FIG. 1 . Here, the lower semiconductor chip 200 may have the same configuration as the first semiconductor chip 200 described above in connection with FIG. 3 . FIG. 6 is a view for explaining a form in which an upper semiconductor chip 300 is stacked on the lower semiconductor chip 200 in the semiconductor package 1 described above with reference to FIG. 1 . Here, the upper semiconductor chip 300 may have the same configuration as the second semiconductor chip 300 described above in connection with FIG. 4 .

Referring to FIG. 5 , the lower semiconductor chip 200 may be disposed in a semiconductor chip mounting area 110 A of a substrate body 110 . The lower semiconductor chip 200 may be bonded to the substrate body 110 by the first adhesive layer 510 described above with reference to FIG. 1 . The pads of a first chip pad 220 a on the lower semiconductor chip 200 may be wire-bonded to corresponding fingers of a first bond finger array 120 a on the package substrate 100 , respectively. As a specific example, for the lower semiconductor chip 200 , the power pads 220 a P 1 and 220 a P 2 , the ground pads 220 a G 1 and 220 a G 2 , and the signal pads 220 a S 1 , 220 a S 2 , 220 a S 3 , and 220 a S 4 of the first chip pad 220 a may be connected to the corresponding power fingers 120 a P 1 and 120 a P 2 , the ground fingers 120 a G 1 and 120 a G 2 , and the signal fingers 120 a S 1 , 120 a S 2 , 120 a S 3 , and 120 a S 4 of the first bond finger array 120 a , respectively. As illustrated in FIG. 5 , the pads of the first chip pad 220 a may be wire-bonded in a one-to-one (1:1) ratio with the fingers of the first bond finger array 120 a . Further, the pads of the first chip pad 220 a may be disposed adjacent to the wire-bonded fingers of the first bond finger array 120 a along the x-direction.

In addition, the pads of the second chip pad 220 b on the lower semiconductor chip 200 may be wire-bonded to the corresponding fingers of the second bond finger array 120 b on the package substrate 100 . Specifically, the power pads 220 b P 1 and 220 b P 2 and the ground pads 220 b G 1 and 220 b G 2 of the second chip pad 220 b may be connected to the corresponding power fingers 120 b P 1 and 120 b P 2 , and the ground fingers 120 b G 1 and 120 b G 2 of the second bond finger array 120 b , respectively. As illustrated in FIG. 5 , the pads of the second chip pad 220 b may be wire-bonded in a 1:1 ratio with the fingers of the second bond finger array 120 b . Further, the pads of the second chip pad 220 b may be disposed adjacent to the wire-bonded fingers of the second bond finger array 120 b along the x-direction. However, pads connected to the signal fingers 120 b S 1 , 120 b S 2 , 120 b S 3 , and 120 b S 4 of the second bond finger array 120 b might not exist among the pads of the second chip pad 220 b because the second chip pad 220 b does not have signal pads.

Referring to FIG. 6 together with FIG. 5 , the upper semiconductor chip 300 may be stacked on the lower semiconductor chip 200 . As described above with reference to FIG. 1 , a second adhesive layer 520 may bond the lower semiconductor chip 200 and the upper semiconductor chip 300 . In FIG. 6 , for convenience of description, the upper semiconductor chip 300 is illustrated to be stacked by being offset at a predetermined distance from the lower semiconductor chip 200 , but in practice, the upper semiconductor chip 300 may be disposed to overlap the lower semiconductor chip 200 without off-set. In an embodiment, the lower semiconductor chip 200 and the upper semiconductor chip 300 may have substantially the same pad arrangement. That is, the arrangements of the power pads, ground pads, and signal pads of the upper semiconductor chip 300 and the lower semiconductor chip 200 may be substantially the same. In an embodiment, the lower semiconductor chip 200 and the upper semiconductor chip 300 may be the same type of chips. The configuration of the lower semiconductor chip 200 and the configuration of the upper semiconductor chip 300 may be substantially the same.

When the upper semiconductor chip 300 is stacked on the lower semiconductor chip 200 , the upper semiconductor chip 300 may be disposed to overlap the lower semiconductor chip 200 , while being rotated 180° relative to the center point C 310 with respect to the lower semiconductor chip 200 . The lower and upper semiconductor chips 200 and 300 may have signal pads 220 a S 1 , 220 a S 2 , 220 a S 3 , 220 a S 4 , 320 a S 1 , 320 a S 2 , 320 a S 3 , and 320 a S 4 only at the first sides 210 E 1 and 310 E 1 of the chip bodies 210 and 310 of the lower and upper semiconductor chips 200 and 300 , respectively. Accordingly, by disposing the upper semiconductor chip 300 to overlap the lower semiconductor chip 200 after rotating the upper semiconductor chip 300 by 180° with respect to the lower semiconductor chip 200 , the signal pads 220 a S 1 , 220 a S 2 , 220 a S 3 , and 220 a S 4 of the lower semiconductor chip 200 can be connected to the signal fingers 120 a S 1 , 120 a S 2 , 120 a S 3 , and 120 a S 4 of the first bond finger array 120 a of the package substrate 100 , and the signal pads 320 a S 1 , 320 a S 2 , 320 a S 3 , and 320 a S 4 of the upper semiconductor chip 300 can be connected to the signal fingers 120 b S 1 , 120 b S 2 , 120 b S 3 , and 120 b S 4 of the second bond finger array 120 b . As described above, the signal fingers 120 a S 1 , 120 a S 2 , 120 a S 3 , and 120 a S 4 of the first bond finger array 120 a and the signal fingers 120 b S 1 , 120 b S 2 , 120 b S 3 , and 120 b S 4 of the second bond finger array 120 b may be connected to different signal paths of the package substrate 100 , respectively. Accordingly, the lower semiconductor chip 200 and the upper semiconductor chip 300 may exchange data signals and address command signals via independent signal paths of the package substrate 100 , respectively.

In addition, as described above, according to the embodiment of the present disclosure, the lower semiconductor chip 200 and the upper semiconductor chip 300 may have substantially the same pad arrangement. That is, the arrangements of the power pads, the ground pads, and the signal pads of the lower semiconductor chip 200 and the upper semiconductor chip 300 may be substantially the same. In an embodiment, the lower semiconductor chip 200 and the upper semiconductor chip 300 may be the same type of chips. Further, in each of the semiconductor chips, any one of the second side power pads may be disposed point-symmetrically to the corresponding one of the first side power pads with respect to a center point on one surface. In addition, any one of the second side ground pads may be disposed point-symmetrically to the corresponding one of the first side ground pads with respect to the center point on the one surface.

Accordingly, when the lower semiconductor chip 200 and the upper semiconductor chip 300 are sequentially stacked on the package substrate 100 in a direction perpendicular to the package substrate 100 , the first side first and second pawer pads 220 a P 1 and 220 a P 2 of the lower semiconductor chip 200 and the second side first and second pawer pads 320 b P 1 and 320 b P 2 of the upper semiconductor chip 300 may overlap each other, and the first side first and second ground pads 220 a G 1 and 220 a G 2 of the lower semiconductor chip 200 and the second side first and second ground pads 320 b G 1 and 320 b G 2 of the upper semiconductor chip 300 may overlap each other. In addition, the second side first and second pawer pads 220 b P 1 and 220 b P 2 of the lower semiconductor chip 200 and the first side first and second pawer pads 320 a P 1 and 320 a P 2 of the upper semiconductor chip 300 may overlap each other, and the second side first and second ground pads 220 b G 1 and 220 b G 2 of the lower semiconductor chip 200 and the first side first and second ground pads 320 a G 1 and 320 a G 2 of the upper semiconductor chip 300 may overlap each other.

As a result, the same types of power pads and ground pads that overlap each other of the lower semiconductor chip 200 and the upper semiconductor chip 300 may be commonly connected to the corresponding power fingers and ground fingers of the package substrate 100 , respectively. As an example, the first side first power pad 220 a P 1 of the lower semiconductor chip 200 and the second side first power pad 320 b P 1 of the upper semiconductor chip 300 may be commonly wire-bonded to the first side first power finger 120 a P 1 of the first bond finger array 120 a of the package substrate 100 . The first side second power pad 220 a P 2 of the lower semiconductor chip 200 and the second side second power pad 320 b P 2 of the upper semiconductor chip 300 may be commonly wire-bonded to the first side second power finger 120 a P 2 of the first bond finger array 120 a of the package substrate 100 . Similarly, the first side first ground pad 220 a G 1 of the lower semiconductor chip 200 and the second side first ground pad 320 b G 1 of the upper semiconductor chip 300 may be commonly wire-bonded to the first side first ground finger 120 a G 1 of the first bond finger array 120 a of the package substrate 100 . The first side second ground pad 220 a G 2 of the lower semiconductor chip 200 and the second side second ground pad 320 b G 2 of the upper semiconductor chip 300 may be commonly wire-bonded to the first side second ground finger 120 a G 2 of the first bond finger array 120 a of the package substrate 100 .

In the same way, the second side first power pad 220 b P 1 of the lower semiconductor chip 200 and the first side first power pad 320 a P 1 of the upper semiconductor chip 300 may be commonly wire-bonded to the second side first power finger 120 b P 1 of the second bond finger array 120 b of the package substrate 100 . The second side second power pad 220 b P 2 of the lower semiconductor chip 200 and the first side second power pad 320 a P 2 of the upper semiconductor chip 300 may be commonly wire-bonded to the second side second power finger 120 b P 2 of the second bond finger array 120 b of the package substrate 100 . Similarly, the second side first ground pad 220 b G 1 of the lower semiconductor chip 200 and the first side first ground pad 320 a G 1 of the upper semiconductor chip 300 may be commonly wire-bonded to the second side first ground finger 120 b G 1 of the second bond finger array 120 b of the package substrate 100 . The second side second ground pad 220 b G 2 of the lower semiconductor chip 200 and the first side second ground pad 320 a G 2 of the upper semiconductor chip 300 may be commonly wire-bonded to the second side second ground finger 120 b G 2 of the second bond finger array 120 b of the package substrate 100 .

As described above, according to an embodiment of the present disclosure, the semiconductor package includes a package substrate and a plurality of semiconductor chips stacked on the package substrate. The plurality of semiconductor chips may each have the same pad arrangement. The semiconductor chip includes a chip body, first chip pads disposed at a first side portion on one surface of the chip body, and second chip pads disposed at a second side portion on the one surface.

The first chip pads may have at least one first side power pad and at least one first side ground pad. The second chip pads may have at least one second side power pad and at least one second side ground pad. In this case, any one of the second side power pads may be disposed point-symmetrically to the corresponding one of the first side power pads with respect to a reference point on one surface, and any one of the second side ground pads may be disposed point-symmetrically to the corresponding one of the first side ground pads with respect to the reference point on the one surface.

When a pair of semiconductor chips having the above-described configuration are stacked to overlap each other in a direction perpendicular to the package substrate, the first side power pads of the lower semiconductor chip and the second side power pads of the upper semiconductor chip may be disposed to overlap each other, and the first side ground pads of the lower semiconductor chip and the second side ground pads of the upper semiconductor chip may be disposed to overlap each other. The second side power pads of the lower semiconductor chip and the first side power pads of the upper semiconductor chip may be disposed to overlap each other, and the second side ground pads of the lower semiconductor chip and the first side ground pads of the upper semiconductor chip may be disposed to overlap each other.

As a result, the power pads overlapping each other of the lower semiconductor chip and the upper semiconductor chip may be wire-bonded in common to one power finger of the package substrate. Similarly, the ground pads overlapping each other of the lower semiconductor chip and the upper semiconductor chip may be wire-bonded in common to one ground finger of the package substrate.

As described above, in the embodiment of the present disclosure, the power pads and the ground pads of the upper semiconductor chip and the lower semiconductor chip can share the power fingers and the ground fingers of the package substrate. Accordingly, the numbers of the power fingers and the ground fingers disposed on the package substrate can be reduced by the number shared. Accordingly, the integration degree of the power fingers and the ground fingers on the package substrate can be improved. Therefore, spaces for arranging the power fingers and the ground fingers on the package substrate can be reduced, thereby obtaining a plane size reduction effect of the entire package. In addition, by reducing the arrangement spaces of the power fingers and the ground fingers on the package substrate, it is possible to additionally secure a space for pattern design on the package substrate. That is, it is possible to improve the degree of freedom of design for various other patterns implemented on the package substrate.

Embodiments of the present disclosure have been disclosed for illustrative purposes. Those skilled in the art will appreciate that various modifications, additions, and substitutions are possible, without departing from the scope and spirit of the present disclosure and the accompanying claims.