Current-mirror based level shifter circuit and methods for implementing the same

This application claims priority from Indian Patent Application No. 202041009375, filed on Mar. 4, 2020, in the Indian. Patent Office, the disclosure of which is incorporated herein by reference in its entirety.

The present disclosure relates to level shifter circuits, and more particularly to methods and apparatus for implementing a current-mirror based level shifter circuit.

In general, circuits that use higher power supply voltages, and the circuits that use different supply voltages may communicate with each other using a level shifter circuit. The level shifter circuit is a circuit that translates logical signals of one voltage level to logical signals of another voltage level. A high voltage level shifter circuit maybe typically used for low voltage to high voltage control signal conversion. For example, a large scale liquid crystal display (LCD) system requires 20 volts to 40 volts to turn on thin-film transistors (TFTs), however an input signal applied to the LCD driver may be 3 volts. In this case, the high voltage level shifter circuit may be used for voltage conversion from 3 volts to 20 volts.

Further, a current-mirror circuit may be used as a basic building block in linear analog integrated circuits. The current-mirror circuit may be employed as biasing elements, active loads (e.g., such as in amplifier stages) or as all-purpose current sources (e.g., such as bit current cells in analog-to-digital converters). The current-mirror is a current input/output device which, ideally, has zero input impedance and infinite output impedance, so that current output remains a fixed function of current input, regardless of variations in output load, and variations in output voltage or fluctuations in applied power source.

FIG. 1 a illustrates a related art different voltage in multi-domains of a System on Chip (SoC). Currently, in lower technology nodes, the conventional systems may be changed from a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) to a Fin shaped Field Effect Transistor (FinFET) for scaling down the layout in circuit. Due to scaling of the layout, the minimum operating voltage (Vmin) may become lower, and with multiple power domains present in an SoC, the level shifter circuits with less propagation delay that can shift voltage to a wide range may be required.

FIG. 1 b illustrates a related art cross-coupled level shifter circuit. The related art cross-coupled level shifter circuit shown in the FIG. 1B is an up-level shifter for translating a lower voltage domain (VDD) to a higher voltage domain (VDDO). The related art cross-coupled level shifter circuit comprises of approximately 23 transistors and may be functional with respect to an enable signal. Accordingly, when the enable signal is high, the related art circuit may translate the voltage level and when the enable signal is low, the conventional circuit may retain output at an active low state. However, the related art cross-coupled circuit may have limited shifting range and may be less robust for higher voltage shifting ranges.

FIG. 1 c illustrates a related art level shifter circuit having a current-mirror configuration. A digital circuit such as the related art level shifter circuit includes the current-mirror configuration. Further, the related art level shifter circuit may include a first and a second current supply transistors that may be configured to provide an output signal to an output node based on an input signal. A leakage current control circuit in the related art circuit may be configured to maintain the first and second current supply transistors in an off state in response to the output signal. An output compensation circuit coupled to the output node may be configured to maintain a voltage level of the output node based on a level of output signal.

However, the related art methods and apparatus may not provide a robust method for wide voltage shifting range by utilizing less area on the layout of the circuit. Further, the related art current-mirror configuration based level-shifter circuits may have more static current and more leakage current.

Example embodiments provide a current-mirror based level shifter circuit and methods for the implementation and operation of the current-mirror based level shifter circuit.

Further, example embodiments provide methods and apparatus for mitigating a contention current and a switching current in the current-mirror based level shifter circuit.

Further still, example embodiments provide methods and apparatus for disabling the path between circuits based on the output of previous circuit.

Further still, example embodiments provide methods and apparatus far level shifting a low voltage input signal to a wide range high voltage signal.

Provided herein is an exemplary current-mirror-based level shifter circuit including a current-mirror circuit, wherein the current-mirror circuit is configured to generate at a first node, based on a input signal and a feedback signal, a first output signal; a feedback control circuit coupled to the current-mirror circuit at the first node, wherein the feedback control circuit comprises a first inverter circuit, a first diode-connected p-channel metal oxide semiconductor (PMOS) transistor and a second diode-connected PMOS transistor, wherein the feedback control circuit is configured to provide, to the first node based on an inverted input signal and the feedback signal, a first level-shifted output signal, wherein the first inverter circuit is configured to receive the first output signal from the first node; a power-down circuit, wherein the power-down circuit is coupled to the first node, wherein, when the current-mirror-based level shifter circuit is in power-down mode, the power-down circuit is configured to: bring the first node to a low voltage level, thereby powering down the current-mirror-based level shifter circuit, and maintain a stable ground voltage level at an output of the current-mirror-based level shifter circuit; and a second inverter circuit coupled to the feedback control circuit, wherein the second inverter circuit is configured to generate a final level-shifted output signal.

Accordingly, the embodiments herein provide a method for implementing a current-mirror based level shifter circuit. The method including: generating, by a current-mirror circuit at a first node, a first output signal based on an input signal and a feedback signal; generating, by a feedback control circuit coupled to the current-mirror circuit at the first node, a level shifted output signal based on receiving an inverted input signal and the feedback signal, wherein the feedback control circuit comprises a first inverter circuit, a first diode-connected p-channel metal oxide semiconductor (PMOS) transistor and a second diode-connected PMOS transistor, providing, to the first node based on the inverted input signal and the feedback signal, a first level-shifted output signal; receiving, by the first inverter circuit, the first output signal from the first node; powering down, by a power down circuit coupled to the first node, when an inverted enable signal is high, the current-mirror-based level shifter circuit to maintain a stable ground voltage level at an output of the current-mirror-based level shifter circuit, wherein the powering down comprises bringing the first node to a low voltage level; and generating, by a second inverter circuit and based on the feedback signal, a final level-shifted output signal.

Provided herein is an exemplary current-mirror-based level shifter circuit including a current-mirror circuit; a first inverter circuit, configured to receive an output from the current-mirror circuit, and generate an inverted current-mirror output signal; a feedback control circuit; a second inverter circuit, wherein the feedback control circuit and the second inverter circuit are configured to: receive the inverted current-mirroroutput signal, and generate a final level shifted output signal; and a power-down circuit, wherein the power-down circuit is configured to power down the current-mirror-based level shifter circuit by bringing an input of the first inverter circuit to a ground voltage, when an inverted enable signal is high.

Also provided herein is a method for implementing a current-mirror-based level shifter circuit, the method comprising: receiving, by a first inverter circuit, an output from a current-mirror circuit; generating, by the first inverter circuit, an inverted current-mirror output signal; receiving, by a second inverter circuit, a voltage from a first node, wherein the first node is connected to an output of a feedback control circuit, to an output of the current-mirror circuit, and to a power-down circuit; generating by the second inverter circuit, a final level-shifted output signal based on the voltage from the first node; and powering down, by the power-down circuit, the current-mirror-based level shifter circuit bringing the first node to a ground voltage level when an inverted enable signal is high.

Example embodiments herein will be more clearly understood from the following description with reference to the drawings, in which:

FIG. 1 a illustrates a related art different voltage in multi-domains of an SoC;

FIG. 1 b illustrates a related art cross-coupled level shifter circuit;

FIG. 1 c illustrates a related art level shifter circuit having a current-mirror configuration;

FIG. 2 illustrates a current-mirror based level shifter circuit at a block diagram level;

FIG. 3 a illustrates a circuit diagram of a current-mirror based level shifter circuit, according to an example embodiment;

FIG. 3 b illustrates a circuit diagram of the current-mirror based level shifter circuit comprising variable width/length (w/l) transistors, according to an example embodiment;

FIG. 4 a is a flow chart depicting a method for implementing the current-mirror based level shifter circuit, according to an example embodiment;

FIG. 4 b is flow chart depicting a method for mitigating a contention current and a switching current in PMOS transistors, according to an example embodiment;

FIG. 4 c is flow chart depicting a method for generating n inverted enable signal (nEN), according to an example embodiment;

FIG. 4 d is flow chart depicting a method for receiving a feedback signal from a first inverter circuit and an inverted first input signal, according to an example embodiment;

FIG. 4 e is flow chart depicting a method for powering down the current-mirror based level shifter circuit, according to an example embodiment;

FIG. 4 f is flow chart depicting a method for generating a level shifted final output signal, according to an example embodiment.

Example embodiments herein and the various features and advantageous details thereof are explained more fully with reference to the non-limiting embodiments that are illustrated in the accompanying drawings and detailed in the following description. Descriptions of well-known components and processing techniques are omitted so as to not unnecessarily obscure the embodiments herein. The description herein is intended merely to facilitate an understanding of ways in which the example embodiments herein can be practiced and to further enable those of skill in the art to practice the example embodiments herein. Accordingly, this disclosure should not be construed as limiting the scope of the example embodiments herein.

In embodiments herein, when an element is referred to as being “coupled”, “connected” or “responsive” to another element, it can be directly coupled, connected or responsive to the other element or intervening elements may also be present. As used herein the term “and/or” includes any and all combinations of one or more of the associated listed items and may be abbreviated by “/”. It will also be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element.

The embodiments herein achieve a current-mirror based level shifter circuit and methods for the implementation and operation of the current-mirror based level shifter circuit. Referring now to the drawings, and more particularly to FIGS. 2 through 4 f , where similar reference characters denote corresponding features consistently throughout the figures, there are shown example embodiments.

FIG. 2 illustrates an inverter circuit 210 a with an input A and an output na, an inverter circuit 210 b with an input EN and an output nEN according to an example embodiment. FIG. 2 also illustrates a high voltage domain power supply 220 and a low voltage domain power supply 230 . In addition, FIG. 2 illustrates a current mirror circuit 202 , a feedback control circuit 204 a , a power down circuit 206 , an inverter circuit 204 b and an inverter circuit 208 with output Y.

A is an input signal.

EN is an enable signal.

z is an intermediate level-shifted output.

x is an internal voltage which is influenced by one or more of the current mirror circuit 202 the feedback control circuit 204 a and the power down circuit 206 .

The power down circuit 206 is able to pull the voltage x to ground.

FIG. 3 a illustrates a circuit diagram of a current-mirror based level shifter circuit 300 , according to an example embodiment.

Further details of the circuit components of FIG. 2 are given in FIG. 3 a . For example, further details of FIG. 2 item 210 a are given by FIG. 3 a item 310 a . This correspondence is shown as follows using { FIG. 2 item, FIG. 3 a item}. Specifically, the labelling correspondence is applicable for the remaining items between FIGS. 2 and 3 a as follows: { 210 a details in 310 a }, { 210 b details in 310 b }, { 202 details in 302 }, { 206 details in 306 }, { 204 a / 204 b details in 304 a / 304 b }, { 208 details in 308 }).

The current-mirror based level shifter circuit 300 includes a plurality of circuit blocks such as a current-mirror circuit 302 , a feedback control circuit 304 a , a first inverter circuit 304 b , a power down circuit 306 , a second inverter circuit 308 , a third inverter circuit 310 a and a fourth inverter circuit 310 b . The output from the current-mirror circuit 302 can be a first output signal. The output from the feedback control circuit 304 a can be a feedback signal. The output from the second inverter circuit 308 can be an inverted level shifted output signal. The output from the third inverter circuit 310 a can be an inverted input signal. The output from the fourth inverter circuit 310 b can be an inverted enable signal. The circuit blocks/circuits may be interchanged or altered according to design specific requirements. Example embodiments herein may implement the current-mirror based level shifter circuit 300 using a Complementary Metal Oxide Semiconductor (CMOS) transistor. Although, the example embodiments described herein may be implemented using a CMOS transistor, which may be formed using a CMOS fabrication process, it is to be appreciated that embodiments are not limited to such transistor devices and/or such a fabrication process, and the other suitable devices, such as, for example, Field Effect Transistor (FET), finFETs (fin shaped Field Effect Transistors), bipolar junction transistors (BJTs), Metal Oxide Semiconductor Field Effect Transistor (MOSFET), Junction FET Transistor (JFET) and so on, and/or fabrication processes (e.g., bipolar, BiCMOS, and so on), may be similarly employed, with or without modification to the integrated circuits as described in the embodiments herein. Moreover, although embodiments herein are typically fabricated in a silicon wafer, embodiments herein can alternatively be fabricated in wafers comprising other materials, including but not limited to Gallium Arsenide, Indium Phosphide, and so on. However, it is to be understood that the current-mirror based level shifter circuit 300 may be implemented for translating signals from one logic level or voltage domain to another, and so on. Also, the current-mirror based level shifter circuit 300 may include a plurality of PMOS transistors and/or a plurality of NMOS transistors. The PMOS transistors and/or NMOS transistors may be added/removed based on the design specific requirements or to save area in the current-mirror based level shifter circuit 300 , and to overcome metal routing congestion or contention current.

The current-mirror based level shifter circuit 300 may be used in at least one of, but not limited to, a low-voltage Application Specific Integrated Circuit (ASIC), an IoT (Internet of thing) chips, a multiple power domain SoC, an interfacing device, a Secure Digital (SD) card, a memory card, a SIM card, a Compact Flash (CF) card, an audio codec, a Universal Asynchronous Receiver Transmitter (UART), a Film Transistor-Liquid Crystal Display (FT-LCD) panels, a piezoelectric motor driver, and so on. For example, the current-mirror based level shifter circuit 300 may be used to control analog switches where the signals involved are bipolar in nature and require dual (+/−5 Volt) supplies. In addition, the current-mirror circuit 302 may copy a current through one active device by controlling the current in another active device of the apparatus or device, keeping the output current constant regardless of loading. Further, the current being copied can be a varying signal current. The current-mirror circuit 302 can bean inverting current amplifier that may also reverse the current direction. The current-mirror circuit 302 may also include a current-controlled current source (CCCS). The current-mirror circuit 302 may be used to provide bias currents and active loads to other circuits in the current-mirror based level shifter circuit 300 . The current-mirror circuit 302 can be implemented with at least one topology such as, but not limited to, a Widlar mirror, a Wilson current, a simple mirror, a cascode mirror, a full cascade mirror, a wide swing mirror, and so on.

In an example embodiment, the current-mirror circuit 302 may include PMOS transistors P 1 , P 2 and P 3 . The PMOS transistor P 2 and the PMOS transistor P 3 are connected in series between a power supply voltage VDDO and the output node of the current-mirror circuit 302 , and a PMOS transistor P 1 is connected in parallel to the PMOS transistors P 2 and P 3 . Further, a gate terminal of the PMOS transistor P 1 is connected to a gate terminal of the PMOS transistor P 2 . The gate terminal of the PMOS transistor P 1 is connected to its drain terminal.

Furthermore, the current-mirror circuit 302 may include NMOS transistors N 1 , N 2 and N 5 connected in parallel with the NMOS transistors N 3 and N 4 . The NMOS transistors N 3 and N 4 are connected in series between the output node of the current-mirror circuit 302 and the ground voltage VSS and connected to the PMOS transistors P 2 and P 3 in series between the power supply voltage VDDO, and the ground voltage VSS. The NMOS transistors N 1 , N 2 and N 5 are connected to PMOS transistor P 1 in series between the power supply voltage VDDO and the ground voltage VSS. The transistor N 1 receives the first input signal as ‘A’. The transistor N 2 receives the feedback signal as ‘Z’. The transistors N 3 and N 4 receive an inverted first input signal as ‘na’, The transistor N 5 receives the enable signal as ‘EN’. The transistor P 3 receives the inverted enable signal as ‘nEN’.

In an example embodiment, the feedback control circuit 304 a and a first inverter circuit may include PMOS transistors P 4 P 5 , P 6 , P 7 , P 8 and NMOS transistors N 8 . The PMOS transistors P 5 , P 6 , P 7 , and P 8 are connected in series between the power supply voltage VDDO and the output node. The PMOS transistor P 5 may receive input from the output node of the feedback control circuit 304 a , The PMOS transistor P 6 may receive inverted first signal as an input via a gate terminal. Further, the gate terminal of the PMOS transistor P 7 and P 8 are connected to source terminal of the respective PMOS transistor P 7 and P 8 . The source terminal of the PMOS transistor P 5 is connected to the output node of the current-mirror circuit 302 . The first inverter circuit 304 b is connected to the output node of the feedback control circuit 304 a and the output node of the current-mirror circuit 302 . When the preliminary input signal at input node has a low level voltage, the output signal may have a high level (i.e. VDDO).

Consider an example scenario, where the PMOS transistors P 7 and P 8 were not used or implemented, and the gate voltage of the PMOS transistor P 5 and P 6 would be maintained at the voltage resulting from subtracting a threshold voltage of the PMOS transistors from the power supply voltage VDDO. Accordingly, without the PMOS transistor P 8 , a leakage current corresponding to a sub-threshold voltage may flow through the PMOS transistors P 5 and P 6 . Accordingly, if the threshold voltage of the PMOS transistor P 6 is lower than the threshold voltage of the PMOS transistor P 5 , a leakage current proportional to the square of a difference between both of the threshold voltages may flow through P 5 .

According to an example embodiment, the PMOS transistors (P 1 to P 11 ) may be moved/altered to form series and parallel combination(s), and the NMOS transistors (N 1 to N 12 ) may be moved/altered to form series and parallel combination(s). Further, operations of the current-mirror based level shifter circuit 300 may be the same even though the PMOS (P 1 to P 11 ) and NMOS transistors (N 1 to N 12 ) are moved or altered or removed according to design requirements. Further, the width and length (w/l) of the PMOS and NMOS transistors may be varied according to the design requirements. One or more PMOS and NMOS transistors may be removed, if the width and length is more than other transistors.

In an example embodiment, the current-mirror based level shifter circuit 300 , comprising the current-mirror circuit 302 , is configured to generate a first output signal based on a received first input signal and a feedback signal. In an example embodiment, the current-mirror circuit 302 receives an enable signal, an inverted enable signal, and a plurality of inverted first input signal.

In an example embodiment, the current-mirror based level shifter circuit 300 comprises the feedback control circuit 304 a . In an embodiment, the feedback control circuit 304 a comprises the first inverter circuit 304 b and a diode connected PMOS (p-channel Metal Oxide Semiconductor) transistor P 7 and P 8 , coupled to the current-mirror circuit 302 , In an embodiment, the feedback control circuit 304 a is configured to generate a level shifted output signal based on receiving the inverted first input signal and the feedback signal. In an embodiment, the first inverter circuit 304 b receives the first output signal as an input to the first inverter circuit 304 b.

In an example embodiment, the current-mirror based level shifter circuit 300 comprising the power down circuit 306 is coupled to an output node of the current-mirror circuit 302 . In an example embodiment, the power down circuit 306 is configured to power down the current-mirror based level shifter circuit 300 , to maintain stable ground voltage (VSS) level at the output, when the current-mirror based level shifter circuit 300 is in power down mode. In an example embodiment, the input of the first inverter circuit 304 b is brought to ground voltage (VSS) level, when an inverted enable (nEN) signal is high. In an example embodiment, the current-mirror based level shifter circuit 300 comprising the second inverter circuit 308 , coupled to the feedback control circuit 304 a , is configured to generate a final level shifted output signal.

In an example embodiment, the current-mirror based level shifter circuit 300 comprising the feedback control circuit 304 a is configured to mitigate at least one of a contention current and a switching current in PMOS transistors P 5 and P 6 , by the diode connected PMOS transistors P 7 and P 8 , based on suppressing a gate-source voltage below a threshold voltage of the PMOS transistor P 6 , to turn-off the feedback control circuit 304 a during an active low input condition of the current-mirror based level shifter circuit 300 . In an example embodiment, the current-mirror based level shifter circuit 300 comprising the third inverter circuit 310 a coupled to an input node of n-channel Metal Oxide Semiconductor (NMOS) transistors N 3 and N 4 and the PMOS transistor P 6 , is configured to generate the inverted first input signal. In an embodiment, the generated inverted first input signal is provided as an input to NMOS transistors N 3 , N 4 and the PMOS transistor P 6 ; wherein the enable signal (EN) is inputted to the third inverter circuit 310 a via a pull-down NMOS transistor N 11 . In an embodiment, the enable signal can be inputted to the third inverter circuit 310 a via a pull-down NMOS transistor N 11 . In an embodiment, the current-mirror based level shifter circuit 300 comprising the fourth inverter circuit 310 b is configured to receive the enable signal via the input node. In an embodiment, the fourth inverter circuit 310 b coupled to input node of an NMOS transistor(s) N 6 , N 7 and a PMOS transistor P 3 , is configured to generate the inverted enable signal (nEN), to provide the inverted enable signal (nEN) as an input to NMOS transistors N 6 N 7 and a PMOS transistor P 3 . In an example embodiment, the NMOS transistor N 5 receiving the enable signal (EN) as input and the PMOS transistor P 3 receiving the inverted enable signal (nEN) as an input, is configured to cut-off the current mirror circuit ( 302 ) when the enable signal (EN) is active low.

In an example embodiment, the current-mirror circuit 302 comprising PMOS transistors P 1 and P 2 is configured to receive high voltage level input power supply via a source terminal of the PMOS transistors P 1 and P 2 . In an example embodiment, the diode connected PMOS transistor P 1 is coupled to a gate terminal of the PMOS transistor P 2 , In an example embodiment, the current-mirror circuit 302 comprises a NMOS transistor N 5 and the PMOS transistor P 3 , connected to the PMOS transistors P 1 and P 2 respectively, is configured to receive the enable signal and the inverted enable signal respectively. In an example embodiment, the current-mirror circuit 302 comprising the NMOS transistors N 1 and N 2 connected in series is configured to receive the first input signal and the feedback signal respectively, and the NMOS transistor (N 5 ), the PMOS transistor (P 3 ) connected in parallel is configured to receive enable signal (EN) and an inverted enable signal (nEN) respectively. In an embodiment, the current-mirror circuit 302 comprising the NMOS transistors N 3 , N 4 in series is connected to the PMOS transistor P 3 is configured to receive the inverted first input signal. In an embodiment, the NMOS transistors N 3 , N 4 is connected between an output node and a ground node of the current-mirror circuit 302 . In an example embodiment, the current-mirror based level shifter circuit 300 comprising the power down circuit 306 is configured to receive the inverted enable signal via an input node. In an embodiment, the power down circuit 306 comprises the NMOS transistor N 6 and N 7 in series is coupled to an output node of the current-mirror circuit 302 . In an example embodiment, the current-mirror based level shifter circuit 300 comprising the feedback circuit 304 a includes the PMOS transistors P 5 , P 6 , P 7 , and P 8 in series. In an example embodiment, the drain terminal of the PMOS transistor P 5 is connected to an output node of the current-mirror circuit 302 . In an example embodiment, the feedback circuit 304 a is configured to receive the feedback signal from the first inverter circuit 304 b via the PMOS transistor P 5 and the inverted first input signal is received via the PMOS transistor P 6 . In an example embodiment, the PMOS transistor P 8 is connected to the diode connected PMOS transistor P 7 , and the diode connected PMOS transistors P 7 is connected to a source terminal of the PMOS transistor P 6 .

In an example embodiment, the current-mirror based level shifter circuit 300 comprises a high voltage domain power supply and a low voltage domain power supply, and the output of the current-mirror based level shifter circuit 300 is a level shifted high voltage domain output signal from the low voltage domain signal. In an embodiment, the third inverter circuit 310 a receives the low voltage domain power supply, and the current-mirror circuit 302 , the feedback control circuit 304 a , the first inverter circuit 304 b , the second inverter circuit 308 the fourth inverter circuit 310 b receives the high voltage domain power.

Although the example embodiments herein have been described in terms of specific embodiments, various modifications can be made without departing from the scope of the present disclosure. For example, by interchanging the feedback signal Z with its complement Z and vice versa while retaining the inputs A and EN. In an embodiment, the current-mirror based level shifter circuit 300 may also include a plurality of current-mirror circuit 302 connected together in series as initial stages, and the feedback control circuit 304 a connected in series as the final stage. Also, the output of the feedback control circuit 304 a may be connected to an output driver without the second inverter circuit 308 . Further, the PMOS transistors and NMOS transistors may be stack or cascaded according to the design requirement and desired output.

FIG. 3 b illustrates a circuit diagram of the current-mirror based level shifter circuit 300 comprising variable width/length (w/l) transistors, according to an example embodiment.

In an example embodiment, the NMOS transistors N 3 and N 4 in the FIG. 3 a are replaced by NMOS transistor N 3 in FIG. 3 b . The width of the NMOS transistor N 3 in FIG. 3 b is varied so as to match the strength of the NMOS transistors N 3 and N 4 in FIG. 3 a . Further, the NMOS transistors N 3 in the current-mirror circuit 302 is scalable based on required operating voltage for robustness of the current-mirror based level shifter circuit 300 . Further, the PMOS transistors P 7 and P 8 in FIG. 3 a are replaced by the PMOS transistors P 8 in FIG. 3 b The width of the PMOS transistor P 8 in FIG. 3 b is varied so as to match the strength of the PMOS transistors P 7 and P 8 in FIG. 3 a . Further, the PMOS transistors P 7 and P 8 in the feedback control circuit 304 a are scalable for the required VGS suppression of the PMOS transistor P 6 , based on required operating voltage for robustness of the current-mirror based level shifter circuit 300 .

In an example embodiment, the first inventor circuit 304 b is configured to receive output from the current-mirror circuit 302 and generate an inverted current-mirror output signal. In an embodiment, the feedback control circuit 304 a and the second inventor circuit 308 is configured to receive the invented current-mirror output signal to generate a final level shifted output signal. In an embodiment, the power down circuit 306 is configured to power down the current-mirror based level shifter circuit 300 , when the current-mirror based level shifter circuit 300 is in power down mode. In an embodiment, the input of the first inverter circuit 304 b is brought to ground voltage (VSS) level, when an inverted enable (nEN) signal is high.

In an example embodiment, the current-mirror circuit 302 is configured to generate a first output signal from a first input signal, an inverted first input signal, a feedback signal, an enable signal (EN) and an inverted enable signal (nEN). In an example embodiment, the first inverter circuit 304 b is configured to receive the first output signal as a first inverter input signal and generate an inverted first output signal. In an embodiment, the feedback control circuit 304 a configured to receive the inverted first output signal and the inverted first input signal and generate the feedback signal to drive the first output signal, when the first input signal is high. In an embodiment, the second inverter circuit 308 is coupled to the output of the first inverter circuit ( 304 b ) via an input node, is configured to generate the level shifted final output signal.

Although the example embodiments herein may have been described in terms of specific embodiments, various modifications can be made without departing from the scope of the present disclosure. For example, the width and size of the transistors may be varied with respect to each transistor to mitigate or suppress the leakage current or contention current.

FIG. 4 a is a flow chart depicting a method 400 a for implementing a current-mirror based level shifter circuit 300 , according to an example embodiment.

The method 400 a includes, at operation 402 , generating, by the current-mirror circuit 302 , the first output signal based on the received first input signal and the feedback signal. At operation 404 , the feedback control circuit 304 a generates the level shifted output signal based on receiving the inverted first input signal and the feedback signal. At operation 406 , the power down circuit 306 powers down the current-mirror based level shifter circuit 300 , to maintain stable ground voltage (VSS) level at the output, when the current-mirror based level shifter circuit 300 is in power down mode. At operation 408 , the second inverter circuit 308 , coupled to the feedback control circuit 304 a , generates a final level shifted output signal.

The various operations in method 400 a may be performed in the order presented, in a different order or simultaneously. Further, in some embodiments, some operations listed in FIG. 4 a may be omitted.

FIG. 4 b is flow chart depicting a method 400 b for mitigating a contention current and a switching current in PMOS transistors, according to an example embodiment.

The method 400 b includes, at operation 412 , mitigating, by the feedback control circuit 304 a , at least one of a contention current and a switching current in a PMOS transistors P 5 , P 6 , by the diode connected PMOS transistors P 7 , P 8 based on suppressing a gate-source voltage below a threshold voltage of the PMOS transistor P 6 , to turn-off the feedback control circuit 304 a during an active low input condition of the current-mirror based level shifter circuit 300 .

The various operations in method 400 b may be performed in the order presented, in a different order or simultaneously. Further, in some embodiments, some operations listed in FIG. 4 b may be omitted.

FIG. 4 c is flow chart depicting a method 400 c for generating the inverted enable signal (nEN), according to an example embodiment.

The method 400 c includes, at operation 422 , generating, by the third inverter circuit 310 a , the inverted first input signal, by receiving the first input signal and the enable signal (EN). At operation 424 , a fourth inverter circuit 310 b generates the inverted enable signal (nEN), to provide the inverted enable signal (nEN) as an input to the NMOS transistors N 6 , N 7 and a PMOS transistor P 3 , by receiving the enable signal via the input node.

The various operations in method 400 c may be performed in the order presented, in a different order or simultaneously. Further, in some embodiments, some operations listed in FIG. 4 c may be omitted.

FIG. 4 d is flow chart depicting a method 400 d for receiving the feedback signal from the first inverter circuit 304 b and the inverted first input signal, according to an example embodiment.

The method 400 d includes, at operation 432 , receiving, by the current-mirror circuit 302 , high voltage level input power supply via a source terminal of the PMOS transistors P 1 , P 2 . At operation 434 , the current-mirror circuit 302 receives the enable signal and the inverted enable signal respectively. At operation 436 , the current-mirror circuit 302 receives the first input signal and the feedback signal respectively, and the NMOS transistor N 5 and the PMOS transistor P 3 of the current-mirror circuit 302 , connected in parallel, receive the enable signal (EN) and an inverted enable signal (nEN), respectively. At operation 438 , the current-mirror circuit 302 receives the inverted first input signal. At operation 440 , the power down circuit 306 receives the inverted enable signal via an input node. At operation 442 , the feedback circuit 304 a receives the feedback signal from the first inverter circuit 304 b via the PMOS transistor P 5 and the inverted first input signal via the PMOS transistor P 6 .

The various operations in method 400 d may be performed in the order presented, in a different order or simultaneously. Further, in some embodiments, some operations listed in FIG. 4 d may be omitted.

FIG. 4 e is flow chart depicting a method 400 e for powering down the current-mirror based level shifter circuit 300 , according to an example embodiment.

The method 400 e includes, at operation 452 , receiving, by the first inverter circuit 304 b , an output from the current-mirror circuit 302 and generating the inverted current-mirror output signal. At operation 454 , the feedback control circuit 304 a and the second inverter circuit 308 receive the inverted current-mirror output signal to generate the final level shifted output signal. At operation 456 , the power down circuit 306 powers down the current-mirror based level shifter circuit 300 , when the current-mirror based level shifter circuit 300 is in power down mode.

The various operations in method 400 e may be performed in the order presented, in a different order or simultaneously. Further, in some embodiments, some operations listed in FIG. 4 e may be omitted.

FIG. 4 f is flow chart depicting a method 400 f for generating the level shifted final output signal, according to an example embodiment.

The method 400 f includes, at operation 462 , generating, by the current-mirror circuit 302 , the first output signal from a first input signal, the inverted first input signal, a feedback signal, the enable signal (EN) and the inverted enable signal (nEN). At operation 464 , the first inverter circuit 304 b receives the first output signal as the first inverter input signal and generates an inverted first output signal. At operation 466 , the feedback control circuit 304 a receives the inverted first output signal and the inverted first input signal and generates the feedback signal to drive the first output signal, when the first input signal is high. At operation 468 , the second inverter circuit 308 generates the level shifted final output signal.

The various operations in method 400 f may be performed in the order presented, in a different order or simultaneously. Further, in some embodiments, some operations listed in FIG. 4 f may be omitted.

The current-mirror based level shifter circuit according to the example embodiments herein may reduce leakage currents or contention currents. The example embodiments herein may provide a robust solution for wide voltage shifting range with lesser layout area or same layout area. Embodiments herein may provide improved delay performance and may solve floating node issue, which actually drives the output current mirror based circuits, based on feedback loop method.

While example embodiments have been particularly illustrated and described above, it will be apparent to those skilled in the art that various changes and modifications in form and details could be made without departing from the spirit and scope of the present disclosure.