Active clamping with bootstrap circuit

This application is a continuation of U.S. patent application Ser. No. 16/401,980, filed May 2, 2019, and is related to U.S. patent application Ser. No. 16/145,819, filed on Sep. 28, 2018, and entitled “Integrated Self-Driven Active Clamp”, and is additionally related to U.S. Pat. No. 10,461,626, issued Oct. 29, 2019, and entitled “Active Clamp Circuit”, all of which are hereby incorporated by reference for all purposes.

Switch-mode power supplies (“power converters”) are power management components in modern electronic devices. They provide, among other things, efficient and galvanically isolated power to multiple loads. To achieve high power processing efficiency and/or galvanic isolation, conventionally one or more magnetically coupled elements, semiconductor switches and associated gate driver circuits are required.

The magnetically coupled elements often suffer from non-trivial leakage inductance phenomena, which necessitate the need for affordable voltage snubber circuits to control the semiconductor switch peak drain-to-source voltages. Recycling of energy using an active clamping configuration within the power converter provides an opportunity for power converter form-factor reduction and power efficiency improvement.

Active clamping configurations typically include one or more semiconductor switches and associated gate drivers. When n-channel MOSFET semiconductor devices are used to implement the one or more semiconductor switches, the associated gate drivers may require a voltage that is higher than that of a DC input voltage supplied to the power converter. In such configurations, a “bootstrap” circuit is often used to generate the required higher voltage.

In some embodiments, an active clamp circuit for a power converter having a transformer includes an active clamp switch having a drain node, a gate node, and a source node, the drain node being configured to be electrically connected to a first terminal of a primary winding of the transformer. The active clamp circuit further includes an active clamp capacitor having a first terminal electrically connected to the source node of the active clamp switch, and a second terminal configured to be electrically connected to a second terminal of the primary winding. The active clamp still further includes a gate driver circuit coupled to the gate node to control the active clamp switch, the gate driver circuit having a high-side input voltage node and a low-side input voltage node, the low-side input voltage node being coupled to the first terminal of the active clamp capacitor. The active clamp circuit still yet further includes a voltage regulator circuit configured to: i) receive an input voltage from the second terminal of the active clamp capacitor, and ii) provide a regulated voltage to the high-side input voltage node of the gate driver circuit using the input voltage, the regulated voltage being of a sufficient voltage level to control the active clamp switch.

In some embodiments, a power converter includes a transformer having a primary winding and a secondary winding, a first terminal of the primary winding being configured to be coupled to a DC voltage input node, the secondary winding being configured to be coupled to a load, a main switch coupled to a second terminal of the primary winding to control a current through the primary winding, and an active clamp circuit. The active clamp circuit includes an active clamp switch having a drain node, a gate node, and a source node, the drain node being configured to be electrically connected to the first terminal of the primary winding of the transformer. The active clamp circuit further includes an active clamp capacitor having a first terminal electrically connected to the source node of the active clamp switch, and a second terminal configured to be electrically connected to the second terminal of the primary winding. The active clamp circuit still further includes a gate driver circuit coupled to the gate node to control the active clamp switch, the gate driver circuit having a high-side input voltage node and a low-side input voltage node, the low-side input voltage node being coupled to the first terminal of the active clamp capacitor. The active clamp circuit still yet further includes a voltage regulator circuit configured to: i) receive an input voltage from the second terminal of the active clamp capacitor, and ii) provide a regulated voltage to the high-side input voltage node of the gate driver circuit using the input voltage, the regulated voltage being of a sufficient voltage level to control the active clamp switch.

FIG. 1 is a simplified schematic of a power converter having an active clamp circuit, in accordance with some embodiments.

FIG. 2 is a simplified schematic of an example active clamp circuit with a bootstrap circuit that could be used in the power converter shown in FIG. 1 .

FIG. 3 is a simplified schematic of an example improved active clamp circuit with an improved bootstrap circuit for use in the power converter shown in FIG. 1 , in accordance with some embodiments.

Some embodiments described herein provide an improved active clamp circuit with an improved bootstrap circuit for use in a power converter that converts an input voltage to an output voltage using a transformer. In some embodiments, the improved bootstrap circuit is advantageously implemented without requiring an additional high-breakdown voltage diode. Additionally, in some embodiments, the improved bootstrap circuit is advantageously implemented without requiring a separate input voltage (i.e., V CC ), thus simplifying the overall power converter design and/or active clamp integration.

In power converters sensitive to power losses and heat generation, energy dissipation in lossy components in the form of heat is undesirable. Thus, recycling of energy using an active clamping configuration within the power converters provides an opportunity for power converter form-factor reduction and power efficiency improvement. Active clamp circuits, as compared to resistor-capacitor-diode (RCD) snubber circuits, advantageously increase power processing efficiency of the power converter by recycling energy stored in a leakage inductance of the transformer. Additionally, such active clamp circuits clamp a primary side peak voltage of a main switch of the power converter, which enables the power converter to utilize primary side switches having a lower voltage rating, leading to reduced power losses during switch conduction and/or switching.

In some embodiments disclosed herein, an n-channel MOSFET (NMOS) switch is used to implement an active clamp switch of an active clamp circuit of a power converter. NMOS switches advantageously have a lower on-resistance as compared to p-channel MOSFET (PMOS) devices. However, to fully turn an NMOS switch on (i.e., an ON-state whereby a channel region of the NMOS switch is conducting), a sufficient gate-source voltage of the NMOS switch is required.

As disclosed herein, an improved bootstrap circuit is used to generate the gate-source voltage required to control, by a gate driver circuit, the on/off state of an active clamp switch of an active clamp circuit. As disclosed herein, the improved bootstrap circuit does not require a high-breakdown voltage diode which is often required for conventional bootstrap circuit architectures. Additionally, as disclosed herein, the improved bootstrap circuit does not require a second voltage supply (e.g., V CC ) which is often required by conventional bootstrap circuit architectures.

FIG. 1 is a simplified circuit schematic of a power converter 100 , in accordance with some embodiments. Some elements of the power converter 100 have been omitted from FIG. 1 to simplify the description of power converter 100 but are understood to be present. A voltage source V in ′ is received at the power converter 100 . V in ′ can be provided either as an alternating current (AC) or direct current (DC). An input side of the power converter 100 generally includes an input voltage filter block 122 , a rectifier block 116 (in the case of AC input), an input voltage buffer capacitor C 1 , an active clamp circuit 114 (which includes an NMOS active clamp switch M 3 ), a main switch M 1 driven by a pulse-width-modulation (PWM) signal PWM M1 , and a primary side controller circuit 118 . The input voltage filter block 122 , the rectifier block 116 and the input buffer capacitor C 1 provide a filtered, buffered, rectified, or otherwise conditioned input voltage V in (i.e., a DC input voltage at a DC voltage input node) to a transformer 102 .

The transformer 102 transfers power from the input side of the power converter 100 to an output side of the power converter 100 and generally includes a primary winding 104 with a first terminal 108 and a second terminal 110 . The output side of the power converter 100 generally includes a secondary winding 106 of the transformer 102 , an output buffer circuit 112 , a synchronous rectifier switch M 2 , a synchronous rectifier switch controller circuit 120 , and is configurable to be connected to a load R L .

The first terminal 108 of the primary winding 104 receives the DC input voltage V in . The second terminal 110 of the primary winding 104 is coupled to a drain node of the main switch M 1 and to an input of the active clamp circuit 114 . The main switch M 1 controls a current through the primary winding 104 to charge a magnetizing inductance L M 105 of the transformer 102 during a first portion of a switching cycle of the power converter 100 . The synchronous rectifier switch M 2 controls a current flow through the secondary winding 106 to discharge the transformer 102 into the output buffer circuit 112 and the load R L during a subsequent portion of the switching cycle.

When the main switch M 1 is enabled by the primary side controller circuit 118 during the first portion of a switching cycle, current flows through the primary winding 104 to a voltage bias node such as ground, illustrated in FIG. 1 as a triangle coupled to a source node of the main switch M 1 . The current flow through the primary winding 104 causes energy to be stored in the magnetizing inductance L M 105 and a leakage inductance L L (not shown) of the transformer 102 . When the main switch M 1 is disabled in a subsequent portion of the switching cycle, an output voltage V out is generated at the output buffer circuit 112 and is provided to the load R L . When the main switch M 1 is turned off, a reflected voltage (nV out ) is developed at the primary winding 104 . The contribution of the reflected voltage nV out to a drain-source voltage V dsM1 of the main switch M 1 at the second terminal 110 is expressed as:

V dsM1 =V in +nV out   (Equation 1)

where n is a turns ratio of the transformer 102 . Energy stored in the leakage inductance L L of the transformer 102 also contributes to the voltage V dsM1 developed at the second terminal 110 . The active clamp circuit 114 prevents the voltage V dsM1 from increasing to a level that damages the main switch M 1 .

FIG. 2 is a simplified circuit schematic of an active clamp circuit 214 that could be used to implement the active clamp circuit 114 of FIG. 1 , but which has some disadvantages that the present invention mitigates or eliminates. The active clamp circuit 214 generally includes the active clamp switch M 3 , an active clamp capacitor C 3 , a gate driver circuit 230 having a high-side input voltage node (+) and a low-side input voltage node (−), and a simplified implementation of a conventional bootstrap circuit 232 . The active clamp switch M 3 has a gate node (G), a drain node (D) and a source node (S). Some circuit elements have been omitted from the schematic for simplicity.

The conventional bootstrap circuit 232 generally includes a resistor R Boot , a high-breakdown voltage diode D Boot , and a bootstrap capacitor C Boot . Also shown are the terminals 108 , 110 of the primary winding 104 of the transformer 102 introduced with reference to FIG. 1 , and a node 236 .

In order to fully turn the active clamp switch M 3 on (i.e., control the active clamp switch M 3 ), the gate driver circuit 230 must drive the gate node G of the active clamp switch M 3 with a gate-source voltage that is higher than a turn-on threshold of the active clamp switch M 3 (e.g., generally a voltage higher than a voltage at the source node S of the active clamp switch M 3 ). Because the source node S of the active clamp switch M 3 is coupled to the second terminal 110 of the primary winding 104 , the voltage at the source node S of the active clamp switch M 3 will equal to V dsM1 . Thus, to fully turn on the active clamp switch M 3 , a voltage higher than V dsM1 is required. However, as previously described with reference to equation 1, the voltage V dsM1 may be higher than the input voltage V in during portions of the switching cycle.

Thus, the conventional bootstrap circuit 232 is utilized to provide a voltage V DDA to the gate driver circuit 230 to control the active clamp switch M 3 . The voltage V DDA is as high or higher than the turn-on threshold of the active clamp switch M 3 so that the gate driver circuit 230 can fully turn on the active clamp switch M 3 in response to an active clamp control signal PWM M3 which is provided by a module or circuit (not shown) of the power converter 100 or the active clamp circuit 214 . The voltage V DDA is referenced to the terminal 110 (i.e., V DDA has a floating ground). A supply voltage V CC is conventionally generated using another voltage regulator circuit (not shown) of the power converter 100 , for example, using a voltage regulator that generates the voltage V CC based on a current received from an auxiliary winding (not shown) of the transformer 102 .

The resistor R Boot generally protects the conventional bootstrap circuit 232 and the gate driver circuit 230 from high in-rush currents. In operation, when the main switch M 1 of the power converter 100 is on (and the active clamp switch M 3 is off), the terminal 110 is pulled to ground (i.e., a bias voltage coupled to the source node of the main switch M 1 ). During this time, the voltage V CC charges the capacitor C Boot through the resistor R Boot and the diode D Boot . Thus, node A of the bootstrap capacitor C Boot is charged to approximately V CC . At a subsequent time in the switching cycle, when the main switch M 1 is turned off, the voltage developed at the bootstrap capacitor C Boot is pulled up by voltage V dsM1 developed at the node 236 (as discussed with reference to equation 1). Thus, the voltage at node A, and correspondingly the voltage V DDA , reaches a voltage level (approximately V CC +V dsM1 ) which is sufficient to fully turn the active clamp switch M 3 on.

Unfortunately, high-breakdown voltage diodes such as the diode D Boot can be both large as well as costly and may preclude integrating the active clamp circuit 214 into a single integrated circuit (IC). Additionally, especially in the systems where the active clamp circuit 114 is implemented as a self-driven clamp module, providing the voltage V CC to the active clamp circuit 214 may introduce design complexity to the power converter 100 .

FIG. 3 is a simplified circuit schematic of an improved active clamp circuit 314 that implements the active clamp circuit 114 of FIG. 1 , in accordance with some embodiments. The improved active clamp circuit 314 generally includes the NMOS active clamp switch M 3 , the active clamp capacitor C 3 , a gate driver circuit 330 having a high-side input voltage node (+) and a low-side input voltage node (−), and an improved bootstrap circuit 334 . The improved bootstrap circuit 334 generally includes a voltage regulator circuit 338 (e.g., an LDO or other linear power regulator that is configured to lower/reduce and/or limit a received input voltage) and an optional capacitor 340 that is configurable to be coupled across the high-side input voltage node (+) and the low-side input voltage node (−) of the gate driver circuit 330 . Also shown are the terminals 108 , 110 of the primary winding 104 of the transformer 102 described with reference to FIG. 1 , and terminals 336 , 342 of the active clamp capacitor C 3 . Some circuit elements have been omitted from the circuit schematic for simplicity.

The improved bootstrap circuit 334 advantageously does not require an additional power source (i.e., to provide the voltage V CC ) as compared to the conventional bootstrap circuit 232 . Additionally, the improved bootstrap circuit 334 advantageously does not require a high-breakdown voltage diode (i.e., the diode D Boot ) as compared to the conventional bootstrap circuit 232 . Thus, the improved bootstrap circuit 334 can advantageously be integrated into a single IC. In some embodiments, the improved bootstrap circuit 334 is integrated into a single IC along with the remaining circuit components of the active clamp circuit 314 (i.e., the active clamp switch M 3 , the voltage regulator circuit 338 , and the gate driver circuit 330 ).

As shown, a connection arrangement of the active clamp capacitor C 3 disclosed in FIG. 3 differs as compared to a connection arrangement of the active clamp capacitor C 3 shown in FIG. 2 . As shown in FIG. 3 , the active clamp capacitor C 3 is connected between the source node S of the active clamp switch M 3 and the second terminal 110 of the primary winding 104 of the transformer 102 and is thereby connected to the drain node of the main switch M 1 . In contrast, the active clamp capacitor C 3 shown in FIG. 2 is connected between the drain node D of the active clamp switch M 3 and the first terminal 108 of the primary winding 104 of the transformer 102 .

The active clamp switch M 3 is controlled based on an active clamp control signal PWM M3 via the gate driver circuit 330 . The active clamp control signal PWM M3 is provided by a module or circuit (not shown) of the power converter 100 or of the improved active clamp circuit 314 . The active clamp circuit 314 clamps the voltage V dsM1 at the drain node of the main switch M 1 to a maximum voltage (e.g., within a safe operating range of the main switch M 1 ). In order to fully turn the active clamp switch M 3 on in response to the control signal PWM M3 , the gate driver circuit 330 must drive the gate node G of the active clamp switch M 3 with a gate-source voltage that is higher than a turn-on threshold of the active clamp switch M 3 (e.g., generally higher than a voltage V S at the source node S of the active clamp switch M 3 ).

The improved bootstrap circuit 334 advantageously provides a high-side rail voltage V DDA to the high-side input voltage node (+) of the gate driver circuit 330 , the voltage V DDA being as high or higher than the turn-on threshold (i.e., higher than a voltage at the source node S) of the active clamp switch M 3 , such that the gate driver circuit 330 can fully turn the active clamp switch M 3 on without requiring a high-breakdown voltage diode and without requiring an external voltage source (e.g., V CC ). The high-side rail voltage V DDA is referenced to a bias voltage V SSA (i.e., a low-side rail voltage) at the low-side input voltage node (−) of the gate driver circuit 330 which is connected to the terminal 342 of the active clamp capacitor C 3 . Thus, the voltage V DDA is referenced to a floating ground which is different than a ground of the power converter 100 (e.g., at a source node of the main switch M 1 ). The voltage regulator circuit 338 is configured to lower, buffer, condition, or limit the input voltage received by the voltage regulator circuit 338 such that the voltage V DDA output by the voltage regulator circuit 338 is lowered and/or limited as compared to the voltage received by the voltage regulator circuit 338 from the terminal 336 of the active clamp capacitor C 3 .

During a portion of a switching cycle of the power converter 100 in which the main switch M 1 is in an OFF state (i.e., not conducting), the terminal 110 , and thereby the terminal 336 , develops a voltage V dsM1 =V in +nV out as discussed with reference to equation 1. During this portion of the switching cycle, the active clamp capacitor C 3 is charged by a reverse current flow i sd from the terminal 110 to the terminal 108 via a body diode of the active clamp switch M 3 . As the active clamp capacitor C 3 is charged, a voltage V C3 develops across the active clamp capacitor C 3 (i.e., across the terminals 336 , 342 ), the voltage V C3 when measured across the active clamp capacitor C 3 being approximately equal to nV out .

The voltage regulator circuit 338 receives the voltage difference V C3 from across the terminals 336 , 342 of the active clamp capacitor C 3 . The voltage regulator circuit 338 uses the voltage V C3 developed across the active clamp capacitor C 3 to generate the high-side rail voltage V DDA , which is received at the high-side input voltage node (+) of the gate driver circuit 330 , by lowering, buffering, limiting, or otherwise conditioning the voltage V C3 . The bias voltage V SSA is received by the gate driver circuit 330 at the low-side input voltage node (−) from the terminal 342 of the active clamp capacitor C 3 . The source node S of the active clamp switch M 3 and the low-side input voltage node (−) of the gate driver circuit 330 are both coupled to the terminal 342 of the active clamp capacitor C 3 , and are thus both at a lower voltage relative to V DDA and further are of a different voltage level than a voltage at a ground node of the power converter 100 (e.g., at the source node of the main switch M 1 ). Thus, the gate driver circuit 330 can provide a sufficient gate voltage to the gate node G to fully turn on the active clamp switch M 3 . The optional capacitor 340 is used in some embodiments to buffer the voltage V DDA received at the gate driver circuit 330 .

At a subsequent time in the switching cycle, the active clamp switch M 3 is turned off and the main switch M 1 is turned on. There is a duration of time before this transition during which both the active clamp switch M 3 and the main switch M 1 are both turned off. The duration of time during which the active clamp switch M 3 and the main switch M 1 are both turned off depends on a desired system operation of the power converter 100 . At the subsequent time in the switching cycle when the main switch M 1 is turned on and the active clamp switch M 3 is turned off, the terminal 110 , and thereby the terminal 336 , is pulled to ground. The switching cycle is repeated when the main switch M 1 is turned off again, and the active clamp capacitor M 3 is charged once again by the current i sd .

Reference has been made in detail to embodiments of the disclosed invention, one or more examples of which have been illustrated in the accompanying figures. Each example has been provided by way of explanation of the present technology, not as a limitation of the present technology. In fact, while the specification has been described in detail with respect to specific embodiments of the invention, it will be appreciated that those skilled in the art, upon attaining an understanding of the foregoing, may readily conceive of alterations to, variations of, and equivalents to these embodiments. For instance, features illustrated or described as part of one embodiment may be used with another embodiment to yield a still further embodiment. Thus, it is intended that the present subject matter covers all such modifications and variations within the scope of the appended claims and their equivalents. These and other modifications and variations to the present invention may be practiced by those of ordinary skill in the art, without departing from the scope of the present invention, which is more particularly set forth in the appended claims. Furthermore, those of ordinary skill in the art will appreciate that the foregoing description is by way of example only, and is not intended to limit the invention.