Printed circuit board

This application claims the priority benefit of Taiwan application serial no. 109108680, filed on Mar. 17, 2020. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.

The disclosure relates to a power transmission element, and particularly, to a printed circuit board configured to provide a power rail.

A printed circuit board is generally formed by a plurality of power layers arranged in parallel and spaced from each other, and may include, for example, a plurality of vias arranged in an array. The vias may be electrically connected to a power supply unit or a load unit to receive or transmit a current. It should be noted that an amount of current that each of the plurality of vias arranged in an array is subject to varies along with a distance of electrical connection to the power supply unit or the load unit. In general, a part of the plurality of vias arranged in an array which are close to the power supply unit or the load unit often may be subject to a great amount of current, which leads to over-temperature of the part of vias. Therefore, several embodiments of solutions will be proposed below with respect to how to design a special printed circuit board architecture to improve the over-heating problem of the vias of the printed circuit board.

Some terms may be used in the entire specification of the invention and the appended claims to refer to particular elements. It should be understood by a person skilled in the art that a device manufacturer may use different names to refer to the same element. This article is not intended to distinguish a person elements with the same function but different names. In the following specification and claims, the words such as “include” and “comprise” are open words, and thus should be interpreted as “include, but not limited to . . . ”.

The invention is directed to a printed circuit board, which may effectively improve over-heating problem of vias of the printed circuit board to provide a better power transmission effect.

The printed circuit board of the invention includes N power layers and a first via group.

The N power layers are arranged in parallel and spaced from each other. The first via group includes M rows of vias which are disposed through the N power layers, where N and M are positive integers greater than 0. Each row of the M rows of vias is electrically connected to a first layer of the N power layers. A P th row of the M rows of vias is further electrically connected to Q power layers of the N power layers respectively, where Q is a smallest positive integer greater than or equal to P((N−1)/M), and P is a positive integer less than or equal to M.

In an embodiment of the invention, the Q power layers are an N th layer to an (N−Q+1) th layer of the N power layers.

In an embodiment of the invention, N is 3, and M is 2.

In an embodiment of the invention, N is 4, and M is 3.

In an embodiment of the invention, the first via group is disposed on a first side of the printed circuit board. The N power layers transmit a current towards a first direction away from the first side of the printed circuit board.

In an embodiment of the invention, the first layer of the N power layers of the printed circuit board is electrically connected to a first power source from the first side of the printed circuit board to cause the current provided by the first power source to be transmitted towards the first direction.

In an embodiment of the invention, a first row to an M th row of the M rows of vias are sequentially arranged along the first direction.

In an embodiment of the invention, the first via group is electrically connected to a power connector in a second direction perpendicular to the printed circuit board to cause the current provided by the power connector to be transmitted towards the first direction.

In an embodiment of the invention, a first row to an M th row of the M rows of vias are sequentially arranged along a direction opposite to the first direction.

In an embodiment of the invention, the printed circuit board further includes a second via group. The second via group includes K rows of vias. The K rows of vias are disposed through the N power layers, where K is a positive integer greater than 0. Each row of the K rows of vias is electrically connected to the first layer of the N power layers. An R th row of the K rows of vias is further electrically connected to S power layers of the N power layers respectively, where S is a smallest positive integer greater than or equal to R((N−1)/K), and R is a positive integer less than or equal to K.

In an embodiment of the invention, the S power layers are an N th layer to an (N−S+1) th layer of the N power layers.

In an embodiment of the invention, the second via group is disposed on a second side of the printed circuit board. The N power layers transmit the current towards the second side from the first side of the printed circuit board.

In an embodiment of the invention, the first layer of the N power layers of the printed circuit board is electrically connected to a load from the second side of the printed circuit board.

The load is configured to receive the current.

In an embodiment of the invention, a first row to a K th row of the K rows of vias are sequentially arranged along a third direction away from the second side of the printed circuit board.

In an embodiment of the invention, each via in the first via group and the second via group is a hollow metal cylinder.

Based on the above, the printed circuit board of the invention can improve the overheating problem of the vias of the printed circuit board by means of the design of special electrical connections between the power layers and the vias.

To enable the above features and advantages of the invention to be more comprehensible, the invention is described in detail below through embodiments with reference to the accompanying drawings.

FIG. 1 is a schematic top view of a printed circuit board according to an embodiment of the invention.

FIG. 2 is a side cross-sectional view of a first embodiment of a via group according to the invention.

FIG. 3 is a side cross-sectional view of a second embodiment of a via group according to the invention.

FIG. 4 is a schematic top view of a printed circuit board according to another embodiment of the invention.

FIG. 5 is a side cross-sectional view of a third embodiment of a via group according to the invention.

To make the contents of the invention more easily understood, the invention is described below with embodiments; however, the invention is not limited to the embodiments illustrated. An appropriate combination between the embodiments is also allowed.

The wording “electrically connect (or couple)” used in the full text (including the claims) of the specification of the disclosure may refer to any direct or indirect connection means. For example, if it is described herein that a first apparatus is electrically connected (or coupled) to a second apparatus, it should be interpreted as that the first apparatus may be directly connected to the second apparatus or the first apparatus may be indirectly connected to the second apparatus through another apparatus or a connection means. The terms such as “first” and “second” mentioned in the full text (including the claims) of the specification of the disclosure may be used to name elements or to distinguish different embodiments or scopes and are not used to limit an upper or lower limit of the number of elements or to limit the order of the elements. In addition, where possible, elements/members/steps with the same reference numerals in the figures and detailed description represent the same or similar parts. The elements/members/steps with the same reference numerals or the same expressions in different embodiments can be cross-referenced for related descriptions.

FIG. 1 is a schematic top view of a printed circuit board according to an embodiment of the invention. Referring to FIG. 1 , the printed circuit board 100 is composed of N power layers, and includes a first via group 110 and a second via group 120 , where N is a positive integer greater than 0. The N power layers are parallel to a plane formed by extension along a direction D 1 and a direction D 3 , and the N power layers are spaced from each other along a direction D 2 , where the directions D 1 , D 2 , and D 3 are perpendicular to each other. In the present embodiment, an insulting layer exists between each two of the N power layers of the printed circuit board 100 . In the present embodiment, the first via group 110 includes M rows of vias 110 _ 1 and 110 _ 2 - 110 _M arranged in an array, and the M rows of vias are disposed through the N power layers along the direction D 2 , where M is a positive integer greater than 0. The second via group 120 includes K rows of vias 120 _ 1 and 120 _ 2 - 120 _K arranged in an array, and the K rows of vias are disposed through the N power layers along the direction D 2 , where K is a positive integer greater than 0. Each row of vias in the first via group 110 and the second via group 120 may include one or more vias, which is not limited in the invention. In addition, each via in the first via group 110 and the second via group 120 may be, for example, a hollow metal cylinder.

In the present embodiment, the first via group 110 may be disposed on a first side S 1 of the printed circuit board 100 , and the first layer of the N power layers of the printed circuit board 100 is electrically connected to one end of a power source 100 S from the first side S 1 of the printed circuit board 100 . The other end of the power source 100 S is electrically connected to a reference potential Vf 1 . The second via group 120 may be disposed on a second side S 2 of the printed circuit board 100 , and the first layer of the N power layers of the printed circuit board 100 is electrically connected to one end of a load 100 L from the second side S 2 of the printed circuit board 100 . The other end of the load 100 L is electrically connected to a reference potential Vf 2 . The first via group 110 , the second via group 120 , and the N power layers form a power rail to cause the power source 100 S to transmit a current through the printed circuit board 100 and the load 100 L to receive the current through the printed circuit board 10 . In the present invention, the current provided by the power source 100 S is transmitted towards a direction D 1 away from the first side S 1 of the printed circuit board 100 through the N power layers of the printed circuit board 100 to the load 100 L on the second side S 2 of the printed circuit board 100 .

It should be noted that since the current is input from the first side S 1 of the printed circuit board 100 , vias close to the first side S 1 are easily subject to a large amount of current. Moreover, since the current is output from the second side S 2 of the printed circuit board 100 , vias close to the second side S 2 easily converge a large amount of current. Regarding this, in the present embodiment, the number of the N power layers electrically connected to each row of the M rows of vias 110 _ 1 and 110 _ 2 - 110 _M in the first via group 110 and the K rows of vias 120 _ 1 and 120 _ 2 - 120 _K in the second via group 120 is different. In the present embodiment, the first row to the M th row of the M rows of vias in the first via group 110 are sequentially arranged along the direction D 1 , and the first row to the K th row of the K rows of vias in the second via group 120 are sequentially arranged along a direction opposite to the direction D 1 .

Specifically, an electrical connection rule for the power rail architecture in the present embodiment is that each row of the M rows of vias 110 _ 1 and 110 _ 2 - 110 _M in the first via group 110 is electrically connected to the first layer of the N power layers and the P th row of vias in the first via group 110 are electrically connected to Q of the N power layers, where Q is a positive integer greater than or equal to P((N−1)/M), and P is a positive integer less than or equal to M. In other words, the number of the power layers electrically connected to the first row of vias 110 _ 1 in the first via group 110 in the present embodiment is minimum, and the number of the power layers electrically connected to the M th row of vias 110 _M in the first via group 110 is maximum. Moreover, the Q power layers are the N th layer to the (N−Q+1) th layer of the N power layers. Therefore, the first row of vias 110 _ 1 in the first via group 110 in the present embodiment may avoid being subject to an excessive amount of current, which effectively reduces the occurrence of overheating of the vias.

Likewise, each row of the K rows of vias 120 _ 1 and 120 _ 2 - 120 _K in the second via group 120 is electrically connected to the first layer of the N power layers, and the R th row of vias in the second via group 120 are electrically connected to S of the N power layers, where S is a positive integer greater than or equal to R((N−1)/K), and R is a positive integer less than or equal to K. In other words, the number of the power layers electrically connected to the first row of vias 120 _ 1 in the second via group 120 in the present embodiment is minimum, and the number of the power layers electrically connected to the K th row of vias 120 _K in the second via group 120 is maximum. Moreover, the S power layers are the N th layer to the (N−S+1) th layer of the N power layers. Therefore, the first row of vias 120 _ 1 in the second via group 120 in the present embodiment may avoid being subject to an excessive amount of current, which effectively reduces the occurrence of overheating of the vias.

In the present embodiment, the first side S 1 of the printed circuit board 100 is opposite the second side S 2 , and the first via group 110 and the second via group 120 may be symmetrically electrically connected to the N power layers respectively. However, in another embodiment of the present embodiment, the first side S 1 of the printed circuit board 100 may also be adjacent to or on the same side as the second side S 2 , but is not limited to the relative position relationship shown in FIG. 1 . Moreover, to enable a person skilled in the art to further understand the design spirit of the special electrical connection architecture of the power rail in the invention, two exemplary embodiments of FIG. 2 and FIG. 3 will be proposed below to provide further illustration.

FIG. 2 is a side cross-sectional view of a first embodiment of a via group according to the invention. Referring to FIG. 2 , a printed circuit board 200 may be, for example, a side cross-sectional view of an embodiment of the printed circuit board 100 in the embodiment of FIG. 1 , and the power rail architecture of the present embodiment satisfies the electrical connection rule in FIG. 1 . The printed circuit board 200 is composed of three power layers 230 _ 1 - 230 _ 3 (i.e., N=3 in the embodiment of FIG. 1 is satisfied). A first side S 1 of the printed circuit board 200 includes a via group 210 , and the via group 210 includes two rows of vias 210 _ 1 and 210 _ 2 (i.e., M=2 in the embodiment of FIG. 1 is satisfied), where the first row of vias 210 _ 1 and the second row of vias 210 _ 2 are disposed through the three power layers 230 _ 1 - 230 _ 3 along the direction D 2 . The first row of vias 210 _ 1 and the second row of vias 210 _ 2 may include one or more vias sequentially arranged along the direction D 3 respectively.

In the present embodiment, the first row of vias 210 _ 1 and the second row of vias 210 _ 2 in the via group 210 are electrically connected to the first power layer 230 _ 1 . The first row of vias 210 _ 1 is further electrically connected to the third power layer 230 _ 3 (i.e., P=1 and Q=1 in the embodiment of FIG. 1 are satisfied, where Q is a smallest positive integer “1” greater than or equal to 1*((3−1)/2)). The second row of vias 210 _ 2 are further electrically connected to the second power layer 230 _ 2 and the third power layer 230 _ 3 (i.e., P=2 and Q=2 in the embodiment of FIG. 1 are satisfied, where Q is a smallest positive integer “2” greater than or equal to 2*((3−1)/2)).

In the present embodiment, the first power layer 230 _ 1 on the first side S 1 of the printed circuit board 200 receives a current I 2 provided from the power source, and the current I 2 flows towards the direction D 1 . It should be noted that from the perspective of equivalent resistances, it is assumed that respective equivalent resistances of the power layers 230 _ 1 - 230 _ 3 are much greater than respective equivalent resistances of the first row of vias 210 _ 1 and the second row of vias 210 _ 2 ; therefore, for a shunt current I 21 , a shunt path of the shunt current I 21 corresponds to an equivalent resistance formed by parallel connection of the first power layer 230 _ 1 , the second power layer 230 _ 2 , and the third power layer 230 _ 3 (a parallel resistance will be less than each resistance connected in parallel). Moreover, for a shunt current I 22 , a shunt path of the shunt current I 22 corresponds to only an equivalent resistance provided by the third power layer 230 _ 3 . In other words, the equivalent resistance corresponding to the shunt path of the shunt current I 21 will be less than that corresponding to the shunt path of the shunt current I 22 . Therefore, when the current I 2 flows through the first row of vias 210 _ 1 , the shunt current I 21 shunted to the first power layer 230 _ 1 will be greater than the shunt current I 22 shunted to the first row of vias 210 _ 1 . The shunt current I 22 for the first row of vias 210 _ 1 will flow from the third power layer 230 _ 3 to a load side of the printed circuit board 200 . Therefore, in the present embodiment, if the current I 2 is large, the first row of vias 210 _ 1 will not be subject to an excessive amount of current to lead to over-temperature.

Likewise, when the shunt current I 21 flows through the second row of vias 210 _ 2 , the first power layer 230 _ 1 is subject to another part of a shunt current I 23 of the shunt current I 21 , and the second row of vias 210 _ 2 are subject to a part of a shunt current I 24 of the shunt current I 21 . Next, most of the shunt current I 24 is shunted to the second power layer 230 _ 2 , and a small part of the shunt current I 24 is shunted to the third power layer 230 _ 3 (the shunt current I 24 mainly flows to the second power layer 230 _ 2 ). Therefore, in an ideal situation, the amount of current of the shunt current I 21 may be approximately two-thirds that of the current I 2 . The amount of current of the shunt current I 22 may be approximately one-third that of the current I 2 . The amount of current of the shunt currents I 23 , I 24 , I 25 , and I 26 may be approximately one-third that of the current I 2 respectively, but the shunting results of the amount of current of the shunt currents are not limited in the invention.

In addition, electrical connections between another via group of the printed circuit board 200 coupled to the other side of the load and the three power layers 230 _ 1 - 230 _ 3 may be symmetric with the electrical connections of the via group 210 shown in FIG. 2 . Therefore, the another via group of the printed circuit board 200 coupled to the other side of the load may be analogized from the architectural design of the via group 210 , and is not described in detail here.

FIG. 3 is a side cross-sectional view of a second embodiment of a via group according to the invention. Referring to FIG. 3 , a printed circuit board 300 may be, for example, a side cross-sectional view of an embodiment of the printed circuit board 100 in the embodiment of FIG. 1 , and the power rail architecture of the present embodiment satisfies the electrical connection rule in FIG. 1 . The printed circuit board 300 is composed of four power layers 330 _ 1 - 330 _ 4 (i.e., N=4 in the embodiment of FIG. 1 is satisfied). A first side S 1 of the printed circuit board 300 includes a via group 310 , and the via group 310 includes three rows of vias 310 _ 1 , 310 _ 2 , and 310 _ 3 (i.e., M=3 in the embodiment of FIG. 1 is satisfied), where the first row of vias 310 _ 1 , the second row of vias 310 _ 2 , and the third row of vias 310 _ 3 are disposed through the four power layers 330 _ 1 - 330 _ 4 along the direction D 2 . The first row of vias 310 _ 1 , the second row of vias 310 _ 2 , and the third row of vias 310 _ 3 may include one or more vias sequentially arranged along the direction D 3 respectively.

In the present embodiment, the first row of vias 310 _ 1 , the second row of vias 310 _ 2 , and the third row of vias 310 _ 3 in the via group 310 are electrically connected to the first power layer 330 _ 1 . The first row of vias 310 _ 1 is further electrically connected to the fourth power layer 330 _ 4 (i.e., P=1 and Q=1 in the embodiment of FIG. 1 are satisfied, where Q is a smallest positive integer “1” greater than or equal to 1*((4−1)/3)). The second row of vias 310 _ 2 are further electrically connected to the third power layer 330 _ 3 and the fourth power layer 330 _ 4 (i.e., P=2 and Q=2 in the embodiment of FIG. 1 are satisfied, where Q is a smallest positive integer “2” greater than or equal to 2*((4−1)/3)). The third row of vias 310 _ 3 are further electrically connected to the second power layer 330 _ 2 , the third power layer 330 _ 3 , and the fourth power layer 330 _ 4 (i.e., P=3 and Q=3 in the embodiment of FIG. 1 are satisfied, where Q is a smallest positive integer “3” greater than or equal to 3*((4−1)/3)).

In the present embodiment, the first power layer 330 _ 1 on the first side S 1 of the printed circuit board 300 receives a current I 3 provided from the power source, and the current I 3 flows towards the direction D 1 . It should be noted that from the perspective of equivalent resistances, it is assumed that respective equivalent resistances of the power layers 330 _ 1 - 330 _ 4 are much greater than respective equivalent resistances of the first row of vias 310 _ 1 , the second row of vias 310 _ 2 , and the third row of vias 310 _ 3 ; therefore, for a shunt current I 31 , a shunt path of the shunt current I 31 corresponds to an equivalent resistance formed by parallel connection of the first power layer 330 _ 1 , the second power layer 330 _ 2 , the third power layer 330 _ 3 , and the fourth power layer 330 _ 4 (a parallel resistance will be less than each resistance connected in parallel). Moreover, for a shunt current I 32 , a shunt path of the shunt current I 32 corresponds to only an equivalent resistance provided by the fourth power layer 330 _ 4 . In other words, the equivalent resistance corresponding to the shunt path of the shunt current I 31 will be less than that corresponding to the shunt path of the shunt current I 32 . Therefore, when the current I 3 flows through the first row of vias 310 _ 1 , the shunt current I 31 shunted to the first power layer 330 _ 1 will be greater than the shunt current I 32 shunted to the first row of vias 310 _ 1 . The shunt current I 32 for the first row of vias 310 _ 1 will flow from the fourth power layer 330 _ 4 to a load side of the printed circuit board 300 . Therefore, in the present embodiment, if the current I 3 is large, the first row of vias 310 _ 1 will not be subject to an excessive amount of current to lead to over-temperature.

Likewise, when the shunt current I 31 flows through the second row of vias 310 _ 2 , the second row of vias 310 _ 2 are subject to a part of a shunt current I 34 of the shunt current I 31 , and another part of a shunt current I 33 of the shunt current I 31 flows to the third row of vias 310 _ 3 . Next, most of the shunt current I 34 is shunted to the third power layer 330 _ 3 , and a small part of the shunt current I 34 is shunted to the fourth power layer 330 _ 4 (the shunt current I 34 mainly flows to the third power layer 330 _ 3 ).

Moreover, when the shunt current I 33 flows through the third row of vias 310 _ 3 , the third row of vias 310 _ 3 are subject to a part of a shunt current I 36 of the shunt current I 33 , and another part of a shunt current I 35 of the shut current I 36 flows to the load side of the printed circuit board 300 through the first power layer 330 _ 1 . Next, most of a shunt current I 37 of the shunt current I 36 is shunted to the second power layer 330 _ 2 . A small part of the shunt current I 36 plus a shunt current I 38 of the shunt current I 34 flow to the load side of the printed circuit board 300 through the third power layer 330 _ 3 , and a further small part of the shunt current I 36 plus a shunt current I 39 of the shunt current I 32 flow to the load side of the printed circuit board 300 through the fourth power layer 330 _ 4 (the shunt current I 36 mainly flows to the second power layer 330 _ 2 ). Therefore, in an ideal situation, the amount of current of the shunt current I 31 may be approximately three-fourths that of the current I 3 . The amount of current of the shunt current I 32 may be approximately one-fourth that of the current I 3 . The amount of current of the shunt current I 33 may be approximately two-fourths that of the current I 3 . The amount of current of the shunt currents I 34 , I 35 , I 36 , I 37 , I 38 , and I 39 may be approximately one-fourth that of the current I 3 respectively, but the shunting results of the amount of current of the shunt currents are not limited in the invention.

In addition, electrical connections between another via group of the printed circuit board 300 coupled to the other side of the load and the four power layers 330 _ 1 - 330 _ 4 may be symmetric with the electrical connections of the via group 310 shown in FIG. 3 . Therefore, the another via group of the printed circuit board 300 coupled to the other side of the load may be analogized from the architectural design of the via group 310 , and is not described in detail here.

FIG. 4 is a schematic top view of a printed circuit board according to another embodiment of the invention. Referring to FIG. 4 , the printed circuit board 400 is composed of N power layers, and includes a via group 410 , where N is a positive integer greater than 0. The N power layers are parallel to a plane formed by extension along a direction D 1 and a direction D 3 , and the N power layers are spaced from each other along a direction D 2 . In the present embodiment, an insulting layer exists between each two of the N power layers of the printed circuit board 100 . In the present embodiment, the via group 410 includes M rows of vias 410 _ 1 and 410 _ 2 - 410 _M arranged in an array, and the M rows of vias are disposed through the N power layers along the direction D 2 , where M is a positive integer greater than 0. Each row of vias in the via group 410 may include one or more vias, which is not limited in the invention. In addition, each via in the via group 410 may be, for example, a hollow metal cylinder.

In the present invention, the via group 410 may be disposed on a first side S 1 of the printed circuit board 400 , and the first layer of the N power layers of the printed circuit board 400 is vertically electrically connected to a power connector from the direction D 2 of the printed circuit board 400 to receive a current provided by the power connector from the direction D 2 . The via group 410 , the N power layers, and a via group on the other side (load side) of the other side form a power rail. It should be noted that since the current is vertically input to the printed circuit board 100 , a via on the innermost side of the printed circuit board 100 (the via farthest from the first side of the printed circuit board 100 ) is easily subject to a large amount of current. Therefore, compared with the embodiment of FIG. 1 , the via group 410 in FIG. 4 and the via group 110 in FIG. 1 are different in a row order of the vias. In the present embodiment, the first row to the M th row of the M rows of vias in the first via group 410 are sequentially arranged along a direction opposite to the direction D 1 .

Specifically, each row of the M rows of vias 410 _ 1 and 410 _ 2 - 410 _M in the via group 410 is electrically connected to the first layer of the N power layers, and the P th row of vias in the first via group 410 are electrically connected to Q of the N power layers, where Q is a positive integer greater than or equal to P((N−1)/M), and P is a positive integer less than or equal to K. In other words, the number of the power layers electrically connected to the first row of vias 410 _ 1 in the first via group 410 in the present embodiment is minimum, and the number of the power layers electrically connected to the M th row of vias 410 _M in the first via group 410 is maximum. Moreover, the Q power layers are the N th layer to the (N−Q+1) th layer of the N power layers. Therefore, the first row of vias 410 _ 1 in the first via group 410 in the present embodiment may avoid being subject to an excessive amount of current, which effectively reduces the occurrence of overheating of the vias. Moreover, to enable a person skilled in the art to further understand the design spirit of the special electrical connection architecture of the power rail in the invention, an exemplary embodiment of FIG. 5 will be proposed below to provide further illustration.

FIG. 5 is a side cross-sectional view of a third embodiment of a via group according to the invention. Referring to FIG. 5 , a printed circuit board 500 may be, for example, a side cross-sectional view of an embodiment of the printed circuit board 400 in the embodiment of FIG. 4 , and the power rail architecture of the present embodiment satisfies the electrical connection rule in FIG. 4 . The printed circuit board 500 is composed of four power layers 530 _ 1 - 530 _ 4 (i.e., N=4 in the embodiment of FIG. 4 is satisfied). A first side S 1 of the printed circuit board 500 includes a via group 510 , and the via group 510 includes three rows of vias 510 _ 1 , 510 _ 2 , and 510 _ 3 (i.e., M=3 in the embodiment of FIG. 4 is satisfied), where the first row of vias 510 _ 1 , the second row of vias 510 _ 2 , and the third row of vias 510 _ 3 is disposed through the four power layers 530 _ 1 - 530 _ 4 along the direction D 2 . The first row of vias 510 _ 1 , the second row of vias 510 _ 2 , and the third row of vias 510 _ 3 may include one or more vias sequentially arranged along the direction D 3 respectively.

In the present embodiment, the first row of vias 510 _ 1 , the second row of vias 510 _ 2 , and the third row of vias 510 _ 3 in the via group 510 are electrically connected to the first power layer 530 _ 1 . The first row of vias 510 _ 1 is further electrically connected to the fourth power layer 530 _ 4 (i.e., P=4 and Q=1 in the embodiment of FIG. 1 are satisfied, where Q is a smallest positive integer “1” greater than or equal to 1*((4−1)/3)). The second row of vias 510 _ 2 is further electrically connected to the third power layer 530 _ 3 and the fourth power layer 530 _ 4 (i.e., P=2 and Q=2 in the embodiment of FIG. 4 are satisfied, where Q is a smallest positive integer “2” greater than or equal to 2*((4−1)/3)). The third row of vias 510 _ 3 is further electrically connected to the second power layer 530 _ 2 , the third power layer 530 _ 3 , and the fourth power layer 530 _ 4 (i.e., P=3 and Q=3 in the embodiment of FIG. 4 are satisfied, where Q is a smallest positive integer “3” greater than or equal to 3*((4−1)/3)).

In the present embodiment, the first power layer 530 _ 1 on the first side S 1 of the printed circuit board 500 is coupled to a power connector 500 C in the direction D 2 to receive a current I 5 provided from the power source, and the current I 5 is shunted through the first row of vias 510 _ 1 , the second row of vias 510 _ 2 , and the third row of vias 510 _ 3 . It should be noted that from the perspective of equivalent resistances, it is assumed that respective equivalent resistances of the power layers 530 _ 1 - 530 _ 4 are much greater than respective equivalent resistances of the first row of vias 510 _ 1 , the second row of vias 510 _ 2 , and the third row of vias 510 _ 3 ; therefore, for a shunt current I 51 , a shunt path of the shunt current I 51 corresponds to only an equivalent resistance provided by the fourth power layer 530 _ 4 , but the shunt path of the shunt current I 51 is closer to the vias on the receiving side. In other words, since the first row of vias 510 _ 1 is closest to the vias on the receiving side, the equivalent resistance provided by the fourth power layer 530 _ 4 will be reduced. For a shunt current I 52 , a shunt path of the shunt current I 52 corresponds to an equivalent resistance formed by parallel connection of the third power layer 530 _ 3 and the fourth power layer 530 _ 4 (a parallel resistance will be less than each resistance connected in parallel), but the shunt path of the shunt current I 52 is less close to the vias on the receiving side. In other words, since the second row of vias 510 _ 2 is less close to the vias on the receiving side, the equivalent resistances provided by the third power layer 530 _ 3 and the fourth power layer 530 _ 4 respectively will be reduced slightly. Moreover, for a shunt current I 53 , a shunt path of the shunt current I 53 corresponds to an equivalent resistance formed by parallel connection of the second power layer 530 _ 2 , the third power layer 530 _ 3 , and the fourth power layer 530 _ 4 , but the shunt path of the shunt current I 53 is farthest from the vias on the receiving side. In other words, since the third row of vias 510 _ 3 is farthest from the vias on the receiving side, the equivalent resistances of the second power layer 530 _ 2 , the third power layer 530 _ 3 , and the fourth power layer 530 _ 4 are almost unaffected by the distance from the vias on the receiving side.

Accordingly, by integrating the influences of distances from the power layers to the vias on the receiving side on the equivalent resistances, the equivalent resistance corresponding to the shunt path of the shunt current I 51 will be slightly greater than that corresponding to the shunt path of the shunt current I 52 , and the equivalent resistance corresponding to the shunt path of the shunt current I 52 will be slightly greater than that corresponding to the shunt path of the shunt current I 53 . Therefore, although the shunt current I 51 shunted to the first row of vias 510 _ 1 will be greater than the shunt currents I 52 and I 53 shunted to the second row of vias 510 _ 2 and the third row of vias 510 _ 3 and the shunt current I 52 shunted to the second row of vias 510 _ 2 will be greater than the shunt current I 53 shunted to the third row of vias 510 _ 3 , the shunt current I 51 will be smaller than the sum of the shunt current I 52 and the shunt current I 53 . That is, if the current I 5 is large, the first row of vias 510 _ 1 will not be subject to an excessive amount of current to lead to over-temperature, although the amount of current of the shunt current I 51 that the first row of vias 510 _ 1 is subject to is still large.

Likewise, a part of the shunt current I 51 is shunted to the first power layer 530 _ 1 , and the other part is shunted along the first row of vias 510 _ 1 to the fourth power layer 530 _ 4 . A main part of the shunt current I 52 is shunted along the second row of vias 510 _ 2 to the third power layer 530 _ 3 , and the other small part is shunted to the first power layer 530 _ 1 and shunted along the second row of vias 510 _ 2 to the fourth power layer 530 _ 4 . A main part of the shunt current I 53 is shunted along the third row of vias 510 _ 3 to the second power layer 530 _ 2 , and the other small part is shunted to the first power layer 530 _ 1 and shunted along the third row of vias 510 _ 3 to the third power layer 530 _ 3 and the fourth power layer 530 _ 4 . Therefore, in an ideal situation, the amount of current of the shunt currents I 54 , I 55 , I 56 , and I 57 may be approximately one-fourth that of the current I 5 respectively, but the shunting results of the amount of current of the shunt currents are not limited in the invention.

Based on the above, the printed circuit board of the invention includes a power rail formed by a plurality of power layers and a plurality of rows of vias arranged in an array, and the number of power layers electrically connected to the plurality of rows of vias of the printed circuit board of the invention respectively is different. Therefore, the printed circuit board of the invention can effectively improve the overheating problem of the vias of the printed circuit board based on the design of special electrical connections between the power layers and the vias disclosed in the invention.

The invention has been disclosed above with embodiments; however, the embodiments are not intended to limit the invention. Any person of ordinary skill in the art can make some changes and modifications without departing from the spirit and scope of the invention. Thus, the protection scope of the invention should be subject to that defined by the appended claims.