Circuit arrangement for controlling backlight source and operation method thereof

This application is a continuation application of and claims the priority benefit of a prior application Ser. No. 16/163,593, filed on Oct. 18, 2018, which is a continuation-in-part application of and claims the priority benefit of a prior application Ser. No. 15/828,396, filed on Nov. 30, 2017, now pending. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.

The invention relates to a display device and more particularly, to a circuit arrangement for controlling a backlight source and an operation method thereof.

FIG. 1 is schematic waveform diagram of a backlight control signal BL 1 when a backlight device of the related art controls/drives a backlight source in an asynchronous manner. In FIG. 1 , the vertical axis represents the voltage, and the horizontal axis represents the time. In FIG. 1 , Vsync represents a vertical sync signal, and DE represents a data enablement signal. A video processing circuit (not shown) may transmit the vertical sync signal Vsync and the data enablement signal DE to a panel driving circuit (not shown), so as to control the panel driving circuit to drive a liquid crystal display (LCD) panel (not shown). The vertical sync signal Vsync defines a plurality of video frame periods, for example, video frame periods F 1 , F 2 , F 3 and F 4 illustrated in FIG. 1 . As illustrated in FIG. 1 , the backlight control signal BL 1 of the backlight device of the related art is unrelated to phases (or timings) of the video frame periods F 1 , F 2 , F 3 and F 4 , i.e., the backlight device of the related art controls a backlight source (not shown) in an asynchronous manner. An issue of motion blur may occurs to the LCD panel using the asynchronous backlight.

FIG. 2A is schematic waveform diagram of a backlight control signal BL 2 when the backlight device of the related art controls/drives the backlight source in a synchronous manner. In FIG. 2A , the vertical axis represents voltages, the horizontal axis represents the time. In FIG. 2A , Vsync represents a vertical sync signal, and DE represents a data enablement signal. The vertical sync signal Vsync defines a plurality of video frame periods, for example, video frame periods F 1 , F 2 and F 3 as illustrated in FIG. 2A . As illustrated in FIG. 2A , a phase (or a timing) of the backlight control signal BL 2 of the backlight device of the related art may be synchronous with the video frame periods F 1 , F 2 , F 3 and F 4 in accordance with the vertical sync signal Vsync, i.e., the backlight device of the related art controls/drives a backlight source (not shown) in a synchronous manner. When the backlight control signal BL 2 is at a high level, the backlight source provides backlight. When the backlight control signal BL 2 is at a low level, the backlight source does not provide backlight. Pulse widths PW 2 of the backlight control signal BL 2 in the video frame periods F 1 , F 2 , F 3 and F 4 are equal to one another, and the pulse widths PW 2 may be modulated according to use requirements.

FIG. 2B is a schematic waveform diagram of a backlight control signal BL 2 when the backlight device of another related art controls/drives the backlight source in a synchronous manner. In FIG. 2B , the vertical axis represents the voltage, and the horizontal axis represents the time. The vertical sync signal Vsync and the data enablement signal DE illustrated in FIG. 2B may be derived with reference to the description related to FIG. 2A and thus, will not be repeated. As illustrated in FIG. 2B , a phase (or a timing) of the backlight control signal BL 2 of the backlight device of the related art may be synchronous with the video frame periods F 1 , F 2 , F 3 and F 4 in accordance with the data enablement signal DE, i.e., the backlight device of the related art controls/drives a backlight source (not shown) in a synchronous manner. Pulse widths PW 2 of the backlight control signal BL 2 in the video frame periods F 1 , F 2 , F 3 and F 4 are equal to one another, and the pulse widths PW 2 may be modulated according to use requirements. In any case, in an actual application environment, a period length of the vertical sync signal Vsync (a period length of the data enablement signal DE) may not be fixed, and lengths of the video frame periods F 1 , F 2 F 4 and F 4 are different from one another (as illustrated in FIG. 2A and FIG. 2B ). For the LCD panel using the synchronous backlight, an issue of backlight flicker may arise to the backlight device of the related art because the period length of the vertical sync signal Vsync is not fixed.

The invention provides a circuit arrangement for controlling a backlight source and an operation method thereof to improve the issue of backlight flicker.

According to an embodiment of the invention, a circuit arrangement for controlling a backlight source is provided. The circuit arrangement includes a generator. The generator is configured to receive a sync signal and generate a pulse width modulation (PWM) signal synchronous with the sync signal to control the backlight source. The sync signal indicates a frequency of a video including a series of image frames. The sync signal includes a sync period corresponding to a frame of the video. The PWM signal includes a first waveform pattern in a first sub-period of the sync period and a second waveform pattern in a second sub-period of the sync period. Each of the first waveform pattern and the second waveform pattern respectively includes at least one active pulse. The first waveform pattern is substantially identical to the second waveform pattern.

According to an embodiment of the invention, an operation method of a circuit arrangement for controlling a backlight source is provided. The operation method includes: receiving, by a generator, a sync signal indicating a frequency of a video including a series of image frames; and generating, by the generator, a PWM signal synchronous with the sync signal to control the backlight source. The sync signal includes a sync period corresponding to a frame of the video, the PWM signal includes a first waveform pattern in a first sub-period of the sync period and a second waveform pattern in a second sub-period of the sync period, each of the first waveform pattern and the second waveform pattern includes at least one active pulse, and the first waveform pattern is substantially identical to the second waveform pattern.

According to an embodiment of the invention, a circuit arrangement for controlling a backlight source is provided. The circuit arrangement includes a generator. The generator is configured to receive a sync signal and generate a PWM signal synchronous with the sync signal to control the backlight source. The sync signal indicates a frequency of a video including a series of image frames. The sync signal includes a sync period corresponding to a frame of the video. The PWM signal includes a plurality of repeated waveform patterns in a first sub-period and a second sub-period of the sync period. Each of the repeated waveform patterns includes at least one active pulse.

According to an embodiment of the invention, a circuit arrangement for controlling a backlight source is provided. The circuit arrangement includes a generator. The generator is configured to receive a sync signal and generate a PWM signal synchronous with the sync signal to control the backlight source. The sync signal indicates a frequency of a video including a series of image frames. The sync signal includes a sync period corresponding to a frame of the video. The generator at least divides the sync period into a first sub-period and a second sub-period. The PWM signal includes a first waveform pattern in the first sub-period of the sync period and a second waveform pattern in the second sub-period of the sync period. Each of the first waveform pattern and the second waveform pattern includes at least one active pulse.

According to an embodiment of the invention, a circuit arrangement for controlling a backlight source is provided. The circuit arrangement includes a generator. The generator is configured to receive a sync signal and generate a PWM signal synchronous with the sync signal to control the backlight source. The sync signal indicates a frequency of a video including a series of image frames. The sync signal includes a first sync period corresponding to a first frame of the video and a second sync period corresponding to a second frame of the video. The first sync period is longer in time than the second sync period. The PWM signal includes a first waveform pattern in a first sub-period of the first sync period, a second waveform pattern in a second sub-period of the first sync period, and a third waveform pattern in the second sync period. Each of the first waveform pattern, the second waveform pattern and the third waveform pattern includes at least one active pulse. The first waveform pattern is substantially identical to the second waveform pattern.

To sum up, in the circuit arrangement for controlling the backlight source and the operation method thereof provided by the embodiments of the invention, a sync period is at least divided into a first sub-period and a second sub-period. Each of the first waveform pattern in the first sub-period and the second waveform pattern in the second sub-period respectively includes at least one active pulse. The first waveform pattern is substantially identical to the second waveform pattern. If a length of the sync period is too long, the first waveform pattern and the second waveform pattern may achieve an effect of frequency multiplication to prevent human eyes from perceiving the flicker. Thus, the circuit arrangement and the operation method thereof can achieve improving the issue of backlight flicker.

To make the above features and advantages of the invention more comprehensible, embodiments accompanied with drawings are described in detail below.

The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

FIG. 1 is schematic waveform diagram of a backlight control signal when a backlight device of the related art controls/drives a backlight source in an asynchronous manner.

FIG. 2A is schematic waveform diagram of a backlight control signal when the backlight device of the related art controls/drives the backlight source in a synchronous manner.

FIG. 2B is a schematic waveform diagram of a backlight control signal when the backlight device of another related art controls/drives the backlight source in a synchronous manner.

FIG. 3 is a schematic circuit block diagram illustrating a display device according to an embodiment of the invention.

FIG. 4 is a flowchart illustrating an operation method of a circuit arrangement for controlling a backlight source according to an embodiment of the invention.

FIG. 5 is a schematic waveform diagram of the pulse width modulation (PWM) signal depicted in FIG. 3 according to an embodiment of the invention.

FIG. 6 is a schematic circuit block diagram illustrating the PWM control circuit depicted in FIG. 3 according to an embodiment of the invention.

FIG. 7 is a schematic waveform diagram of the signals depicted in FIG. 6 according to an embodiment of the invention.

FIG. 8 is a schematic circuit block diagram illustrating the PWM control circuit depicted in FIG. 3 according to another embodiment of the invention.

FIG. 9 is a schematic waveform diagram illustrating the vertical sync signal and the smoothed signal depicted in FIG. 8 according to an embodiment of the invention.

FIG. 10 is a flowchart illustrating an operation method of a circuit arrangement for controlling a backlight source according to another embodiment of the invention.

FIG. 11 is a schematic waveform diagram of the PWM signal in FIG. 3 according to yet another embodiment of the invention.

FIG. 12 is a schematic circuit block diagram illustrating the PWM control circuit depicted in FIG. 3 according to yet another embodiment of the invention.

FIG. 13 is a schematic waveform diagram of the PWM signal in FIG. 3 according to still another embodiment of the invention.

FIG. 14 is a schematic circuit block diagram illustrating the PWM control circuit depicted in FIG. 3 according to still another embodiment of the invention.

FIG. 15 is a schematic waveform diagram of the PWM signal in FIG. 3 according to further another embodiment of the invention.

The term “couple (or connect)” herein (including the claims) are used broadly and encompass direct and indirect connection or coupling means. For example, if the disclosure describes a first apparatus being coupled (or connected) to a second apparatus, then it should be interpreted that the first apparatus can be directly connected to the second apparatus, or the first apparatus can be indirectly connected to the second apparatus through other devices or by a certain coupling means. Moreover, elements/components/steps with same reference numerals represent same or similar parts in the drawings and embodiments. Elements/components/notations with the same reference numerals in different embodiments may be referenced to the related description.

FIG. 3 is a schematic circuit block diagram illustrating a display device 300 according to an embodiment of the invention. The display device 300 includes a display panel 330 , a panel driving circuit 320 and a video processing circuit. Based on a design requirement, the video processing circuit is, for example, a scaler circuit 310 and/or other video signal processing circuits. The scaler circuit 310 (the video processing circuit) may transmit a clock signal, a sync signal and video data to the panel driving circuit 320 , so as to control the panel driving circuit to drive the display panel 330 . Based on a design requirement, the sync signal may include a vertical sync signal, a horizontal sync signal, a data enablement signal and/other sync signals. A plurality of video frame periods may be defined by the video sync signal. In other words, the sync signal may indicate a frequency (or a period) of a video. The video includes a series of image frames. Based on a design requirement, the display panel 330 may be a liquid crystal display (LCD) panel or other types of display panels. The scaler circuit 310 , the panel driving circuit 320 and the display panel 330 are conventional components and thus, will not be repeatedly described.

In the embodiment illustrated in FIG. 3 , the display device 300 further includes a backlight source 350 and a circuit arrangement for controlling the backlight source 350 . In the embodiment illustrated in FIG. 3 , the circuit arrangement includes, for example, a generator 340 . The generator 340 may receive the sync signal from the video processing circuit (e.g., the scaler circuit 310 ). According to the sync signal, the generator 340 may control/drive the backlight source 350 in a synchronous manner. The generator 340 may perform global backlight control or local backlight control on the backlight source 350 . The backlight source 350 may provide backlight 351 to the display panel 330 . Based on a design requirement, the backlight source 350 may be a direct type backlight module or an edge-lighting type backlight module. As the generator 340 controls/drives the backlight source in the synchronous manner, the issue of motion blur may be effectively improved.

In the embodiment illustrated in FIG. 3 , the generator 340 includes a pulse width modulation (PWM) control circuit 341 and a backlight driving circuit 342 . The PWM control circuit 341 is coupled to the video processing circuit (e.g., the scaler circuit 310 ) to receive the sync signal (e.g., the vertical sync signal, the data enablement signal and/or any other sync signal). The PWM control circuit 341 may generate a PWM signal BL 3 . The backlight driving circuit 342 is coupled to the PWM control circuit 341 to receive the PWM signal BL 3 . According to the PWM signal BL 3 , the backlight driving circuit 342 may drive the backlight source 350 of the display panel 330 . The PWM control circuit 341 may perform the global backlight control or the local backlight control on the backlight source 350 .

FIG. 4 is a flowchart illustrating an operation method of a circuit arrangement for controlling a backlight source according to an embodiment of the invention. Referring to FIG. 3 and FIG. 4 , in step S 410 , the PWM control circuit 341 receives the sync signal (e.g., the vertical sync signal, the data enablement signal and/or any other sync signal) from the video processing circuit (e.g., the scaler circuit 310 ). A plurality of video frame periods are defined by the sync signal. In step S 420 , the PWM control circuit 341 may at least divide each of the video frame periods into a first period and a second period, wherein lengths of the first periods of different video frame periods are equal to one another.

FIG. 5 is a schematic waveform diagram of the PWM signal BL 3 depicted in FIG. 3 according to an embodiment of the invention. In FIG. 5 , the vertical axis represents the voltage, and the horizontal axis represents the time. In the implementation example illustrated in FIG. 5 , it is assumed that the PWM control circuit 341 receives a vertical sync signal Vsync (i.e., video sync information) from the video processing circuit (e.g., the scaler circuit 310 ). Referring to FIG. 3 , FIG. 4 and FIG. 5 , a plurality of video frame periods are defined by the vertical sync signal Vsync (i.e., the video sync information), for example, video frame periods F 5 , F 6 , F 7 and F 8 as illustrated in FIG. 5 . In another embodiment, the PWM control circuit 341 may receive the data enablement signal DE (i.e., the sync signal) from the video processing circuit (e.g., the scaler circuit 310 ), and a plurality of video frame periods may also be defined by the data enablement signal DE, for example, the video frame periods F 5 , F 6 , F 7 and F 8 as illustrated in FIG. 5 .

In step S 420 , the PWM control circuit 341 may at least divide each of the video frame periods into a first period and a second period. Based on a design requirement, a first period includes a part or all of a data period of each of the video frame periods, and a second period includes a part or all of a blanking period of each of the video frame periods.

For instance, according to the data enablement signal DE in the sync signal, the video frame period F 5 is at least divided into a first period P 51 and a second period P 52 , the video frame period F 6 is at least divided into a first period P 61 and a second period P 62 , the video frame period F 7 is at least divided into a first period P 71 and a second period P 72 , and the video frame period F 8 is at least divided into a first period P 81 and a second period P 82 . Lengths of the first periods P 51 , P 61 , P 71 and P 81 of the video frame periods F 5 to F 8 are equal to one another. The first period P 51 includes a data period of the video frame period F 5 , and the second period P 52 includes a blank period of the video frame period F 5 . The first period P 61 includes a data period of the video frame period F 6 , and the second period P 62 includes a blank period of the video frame period F 6 . The first period P 71 includes a data period of the video frame period F 7 , and the second period P 72 includes a blank period of the video frame period F 7 . The first period P 81 includes a data period of the video frame period F 8 , and the second period P 82 includes a blank period of the video frame period F 8 .

In step S 430 , the PWM control circuit 341 may generate the PWM signal BL 3 . A frequency of the PWM signal BL 3 in the first periods is different from a frequency of the PWM signal BL 3 in the second periods, but a duty ratio of the PWM signal BL 3 in the first periods is equal to a duty ratio of the PWM signal BL 3 in the second periods. For instance, the frequency of the PWM signal BL 3 in the first period P 51 is different from the frequency of the PWM signal BL 3 in the second period P 52 , but the duty ratio of the PWM signal BL 3 in each duty cycle of the first period P 51 is equal to the duty ratio of the PWM signal BL 3 in each duty cycle of the second period P 52 .

In the embodiment illustrated in FIG. 5 , the frequency of the PWM signal BL 3 in the first periods is less than the frequency of the PWM signal BL 3 in the second periods. For instance, the frequency of the PWM signal BL 3 in the first period P 51 is less than the frequency of the PWM signal BL 3 in the second period P 52 .

The backlight driving circuit 342 is coupled to the PWM control circuit 341 to receive the PWM signal BL 3 . In step S 440 , the backlight driving circuit 342 drives the backlight source 350 of the display panel 330 according to the PWM signal BL 3 , thereby driving the backlight source 350 to provide the backlight 351 to the display panel 330 .

Based on the above, by the generator 340 and the operation method thereof provided by the present embodiment, each video frame period is at least divided into the first period and the second period. The lengths of the first periods of different video frame periods are equal to one another. If the length of each video frame period is changed, the lengths of the second periods are changed along therewith, but the lengths of the first periods are not. The frequency of the PWM signal BL 3 in the first periods is different from the frequency of the PWM signal BL 3 in the second periods, but the duty ratio of the PWM signal BL 3 in each first period is equal to the duty ratio of the PWM signal BL 3 in each second period. Thus, with the backlight source 350 being driven/controlled to provide compensation light (i.e., the backlight 351 ) in the second periods, the average backlight brightness in different video frame periods F 5 to F 8 may tend to be approximately equal to one another. In other words, the generator 340 and the operation method thereof may achieve improving the issue of backlight flicker.

FIG. 6 is a schematic circuit block diagram illustrating the PWM control circuit 341 depicted in FIG. 3 according to an embodiment of the invention. In the embodiment illustrated in FIG. 6 , the PWM control circuit 341 includes a period defining circuit 610 , a first PWM signal generating circuit 620 , a second PWM signal generating circuit 630 and a superimposing circuit 640 . The period defining circuit 610 is coupled to the video processing circuit (e.g., the scaler circuit 310 ) to receive the sync signal (e.g., the vertical sync signal Vsync) from the video processing circuit. According to a timing of the vertical sync signal Vsync, the period defining circuit 610 may generate a first enablement signal 611 and a second enablement signal 612 . The first periods may be defined by the first enablement signal 611 , and the second periods may be defined by the second enablement signal 612 .

For instance, FIG. 7 is a schematic waveform diagram of the signals depicted in FIG. 6 according to an embodiment of the invention. In FIG. 7 , the vertical axis represents the voltage, and the horizontal axis represents the time. A plurality of video frame periods are defined by the vertical sync signal Vsyn, for example, video frame periods F 9 and F 10 as illustrated in FIG. 7 . The video frame period F 9 is at least divided into a first period P 91 and a second period P 92 , and the video frame period F 10 is at least divided into a first period P 101 and a second period P 102 . The first periods P 91 and P 101 may be defined by the first enablement signal 611 , and the second periods P 92 and P 102 may be defined by the second enablement signal 612 . Lengths of the first periods P 91 and P 101 are equal to each other. If the length of each video frame period is changed, the lengths of the second periods P 92 and P 102 are changed along therewith, but the lengths of the first periods P 91 and P 101 are not.

Referring to FIG. 6 and FIG. 7 , the first PWM signal generating circuit 620 is coupled to the period defining circuit 610 to receive the first enablement signal 611 . The first PWM signal generating circuit 620 may generate the first PWM signal 621 in each first period according to the first enablement signal 611 . The first PWM signal generating circuit 620 may determine a duty ratio of the first PWM signal 621 in the first period according to a duty ratio parameter DR. It is assumed that the duty ratio is 50% in the embodiment illustrated in FIG. 7 , while the duty ratio may be adjusted based on use requirements in other embodiments. The first PWM signal generating circuit 620 may further determine a phase of the first PWM signal 621 in each first period according to a delay parameter DL. The first PWM signal generating circuit 620 may be any type of PWM signal generating circuit/element. For example, the first PWM signal generating circuit 620 may be a PWM signal generating circuit that is well known in this field or any other PWM signal generating circuit.

In the embodiment illustrated in FIG. 7 , when the first enablement signal 611 is at a low level, the first PWM signal generating circuit 620 is disabled. When the first enablement signal 611 is at a high level, the first PWM signal generating circuit 620 is enabled. Thus, the first PWM signal generating circuit 620 may generate the first PWM signal 621 in the first periods P 91 and P 101 . The first PWM signal generating circuit 620 may set the duty ratio of the first PWM signal 621 in the first periods P 91 and P 101 to 50% according to the duty ratio parameter DR. The first PWM signal generating circuit 620 may further determine a time of delay TD of a pulse of the first PWM signal 621 in the first periods P 91 and P 101 according to the delay parameter DL, i.e., determine a phase of the first PWM signal 621 in the first periods P 91 and P 101 .

The second PWM signal generating circuit 630 is coupled to the period defining circuit 610 to receive the second enablement signal 612 . The second PWM signal generating circuit 630 may generate the second PWM signal 631 according to the second enablement signal 612 in the second periods. The second PWM signal generating circuit 630 may determine a duty ratio of the second PWM signal 631 in the second periods according to the duty ratio parameter DR. In the embodiment illustrated in FIG. 7 , when the second enablement signal 612 is at a low level, the second PWM signal generating circuit 630 is disabled. When the second enablement signal 612 is at a high level, the second PWM signal generating circuit 630 is enabled. Thus, the second PWM signal generating circuit 630 may generate the second PWM signal 631 in the second periods P 92 and P 102 . The second PWM signal generating circuit 630 may set the duty ratio of the second PWM signal 631 in the second periods P 92 and P 102 to 50% according to the duty ratio parameter DR. A frequency of the second PWM signal 631 in the second periods P 92 and P 102 is different from a frequency of the first PWM signal 621 in the first periods P 91 and P 101 . The second PWM signal generating circuit 630 may be any type of PWM signal generating circuit/element. For example, the second PWM signal generating circuit 630 may be a PWM signal generating circuit that is well known in this field or any other PWM signal generating circuit.

The superimposing circuit 640 is coupled to the first PWM signal generating circuit 620 to receive the first PWM signal 621 . The superimposing circuit 640 is coupled to the second PWM signal generating circuit 630 to receive the second PWM signal 631 . The superimposing circuit 640 may superimpose the first PWM signal 621 and the second PWM signal 631 to obtain the PWM signal BL 3 , as illustrated in FIG. 7 .

FIG. 8 is a schematic circuit block diagram illustrating the PWM control circuit 341 depicted in FIG. 3 according to another embodiment of the invention. In the embodiment illustrated in FIG. 8 , the PWM control circuit 341 includes a low pass filter 710 , a period defining circuit 610 , a first PWM signal generating circuit 620 , a second PWM signal generating circuit 630 and a superimposing circuit 640 . The period defining circuit 610 , the first PWM signal generating circuit 620 , the second PWM signal generating circuit 630 and the superimposing circuit 640 illustrated in FIG. 8 may be inferred with reference to the descriptions related to the embodiments illustrated in FIG. 6 and FIG. 7 and thus, will not be repeated.

In the embodiment illustrated in FIG. 8 , the low pass filter 710 is coupled to the video processing circuit (e.g., the scaler circuit 310 ) to receive the sync signal (e.g., the vertical sync signal Vsync) from the video processing circuit. The low pass filter 710 may output a smoothed signal 711 to the period defining circuit 610 . FIG. 9 is a schematic waveform diagram of the vertical sync signal Vsync and the smoothed signal 711 depicted in FIG. 8 according to an embodiment of the invention. As illustrated in FIG. 9 , the low pass filter 710 may smooth the vertical sync signal Vsync to generate the smoothed signal 711 . The period defining circuit 610 is coupled to the low pass filter 710 to receive the smoothed signal 711 . The period defining circuit 610 may generate the first enablement signal 611 and the second enablement signal 612 according to a timing of the smoothed signal 711 .

In the embodiments described above, the backlight source 350 is controlled/driven by the generator 340 and the operation method thereof in a synchronous manner, and thus, the issue of motion blur may be effectively improved. The generator 340 and the operation method thereof may be applied to the backlight control of variable vertical sync signals or fixed vertical sync signals. By the generator 340 and the operation method thereof, each video frame period may be at least divided into the first period and the second period. The lengths of the first periods of different video frame periods are equal to one another. If the length of each video frame period is changed, the lengths of the second periods are changed along therewith, but the lengths of the first periods are not. The frequency of the PWM signal BL 3 in the first periods is different from the frequency of the PWM signal BL 3 in the second periods, but the duty ratio of the PWM signal BL 3 in each first period is equal to the duty ratio of the PWM signal BL 3 in each second period. Thus, with the backlight source 350 being driven/controlled to provide compensation light (i.e., the backlight 351 ) in the second periods, the average backlight brightness in different video frame periods may tend to be approximately equal to one another. In other words, the generator 340 and the operation method thereof may achieve improving the issue of backlight flicker.

FIG. 10 is a flowchart illustrating an operation method of a circuit arrangement for controlling a backlight source according to another embodiment of the invention. Referring to FIG. 3 and FIG. 10 , in step S 1010 , the generator 340 receives the sync signal (which includes the vertical sync signal Vsync, the data enablement signal DE and/or other sync signals). The sync signal indicates a frequency of a video including a series of image frames. The sync signal includes a sync period corresponding to a frame of the video.

In step S 1020 , the generator 340 may generate the PWM signal BL 3 synchronous with the sync signal to control the backlight source 350 . The generator 340 may at least divide the sync period into a first sub-period and a second sub-period. The PWM signal BL 3 includes a first waveform pattern in a first sub-period of the sync period and a second waveform pattern in a second sub-period of the sync period. Each of the first waveform pattern and the second waveform pattern includes at least one active pulse. The first waveform pattern is substantially identical to the second waveform pattern.

In another present embodiment, the PWM signal BL 3 includes a plurality of repeated waveform patterns in the first sub-period and the second sub-period of the sync period. Each of the repeated waveform patterns includes at least one active pulse.

In yet another embodiment, the sync signal includes a first sync period corresponding to a first frame of the video and a second sync period corresponding to a second frame of the video. The first sync period is longer in time than the second sync period. The PWM signal includes the first waveform pattern in the first sub-period of the first sync period, the second waveform pattern in the second sub-period of the first sync period, and a third waveform pattern in the second sync period. Each of the first waveform pattern, the second waveform pattern and the third waveform pattern includes at least one active pulse. The first waveform pattern is substantially identical to the second waveform pattern.

In step S 1030 , the generator 340 may drive the backlight source 350 of the display panel 330 according to the PWM signal BL 3 , thereby driving the backlight source 350 to provide the backlight 351 to the display panel 330 . Step S 1030 illustrated in FIG. 10 may refer to the description related to step S 440 illustrated in FIG. 4 and thus, will not be repeated.

In the present embodiment, the PWM control circuit 341 of the generator 340 may receive the sync signal from the scaler circuit 340 (i.e., the video processing circuit). The PWM control circuit 341 may check the frequency (or the period) of the sync signal. When the frequency of the sync signal is lower than a threshold frequency (or when the period of the sync signal is greater than a threshold period), the PWM control circuit 341 multiplies the frequency of the sync signal to generate a multiplied sync signal. The threshold frequency may be determined based on a design requirement. When the frequency of the sync signal is higher than the threshold frequency, the PWM control circuit 341 serves the sync signal as the multiplied sync signal. The PWM control circuit 341 may generate the PWM signal BL 3 according to the multiplied sync signal. The backlight driving circuit 342 is coupled to the PWM control circuit 341 to receive the PWM signal BL 3 . The backlight driving circuit 342 may drive the backlight source 350 of the display panel 330 according to the PWM signal BL 3 .

The PWM modulation control circuit 341 may check a time length of the sync period. When the time length of the sync period exceeds a rated time length, the PWM control circuit 341 may at least divide the sync period into the first sub-period and the second sub-period. The rated time length may be determined based on a design requirement. A duty ratio of the PWM signal BL 3 in the first sub-period is equal to a duty ratio of the PWM signal BL 3 in the second sub-period. The frequency of the PWM signal BL 3 in the first sub-period is equal to the frequency of the PWM signal BL 3 in the second sub-period.

FIG. 11 is a schematic waveform diagram of the PWM signal BL 3 depicted in FIG. 3 according to yet another embodiment of the invention. In FIG. 11 , the vertical axis represents the voltage, and the horizontal axis represents the time. Referring to FIG. 3 , FIG. 10 and FIG. 11 , in step S 1010 , the PWM control circuit 341 receives a sync signal (e.g., a vertical sync signal Vsync 1 , a data enablement signal DE and/or any other sync signal) from the video processing circuit (e.g., the scaler circuit 310 ). The vertical sync signal Vsync 1 may indicate a frequency (or a period) of a video including a series of image frames, for example, video frames F 11 , F 12 , F 13 , F 14 , F 15 and F 16 illustrated in FIG. 11 . The sync signal includes a sync period corresponding to a frame of the video. For example, the video frame F 16 corresponds to a sync period Psync 1 .

The PWM control circuit 341 may check a time length of the sync period (for example, the sync period Psync 1 illustrated in FIG. 11 ). In this case, the sync period Psync 1 corresponding to the video frame F 16 is employed as an example for description. Sync periods corresponding to the rest of the video frames (for example, the video frames F 11 , F 12 , F 13 , F 14 and F 15 ) may be inferred with reference to the description related to the sync period Psync 1 and thus, will not be repeated. If the sync period Psync 1 is too long (i.e., the frequency of the PWM signal BL 3 may be too low), human eyes may probably perceive the flicker of the backlight source 350 . Thus, when the time length of the sync period Psync 1 exceeds the rated time length, the PWM control circuit 341 may at least divide the sync period into a first sub-period SP 11 and a second sub-period SP 12 .

In step S 1020 , the PWM control circuit 341 may generate the PWM signal BL 3 synchronous with the sync signal (for example, the vertical sync signal Vsync 1 or the data enablement signal DE) to control the backlight source 350 . A duty ratio of the PWM signal BL 3 in the first period SP 11 is equal to a duty ratio of the PWM signal BL 3 in the second period SP 12 , and a frequency of the PWM signal BL 3 in the first period SP 11 is equal to a frequency of the PWM signal BL 3 in the second period SP 12 . In step S 1030 , the backlight driving circuit 342 drives the backlight source 350 of the display panel 330 according to the PWM signal BL 3 , thereby driving the backlight source 350 to provide the backlight 351 to the display panel 330 .

When the time length of the sync period Psync 1 exceeds the rated time length, the PWM control circuit 341 may apply the frequency multiplication operation on the PWM signal BL 3 in the sync period Psync 1 , thereby preventing the human eyes from perceiving the flicker of the backlight source 350 . Thus, the generator 340 and the operation method thereof may achieve improving the issue of backlight flicker.

FIG. 12 is a schematic circuit block diagram illustrating the PWM control circuit 341 depicted in FIG. 3 according to yet another embodiment of the invention. In the embodiment illustrated in FIG. 12 , the PWM control circuit 341 includes a frequency checking circuit 1210 and a PWM signal generating circuit 1220 . The frequency checking circuit 1210 is coupled to the video processing circuit (e.g., the scaler circuit 310 ) to receive the sync signal (for example, the vertical sync signal Vsync 1 ) from the vertical sync signal. The frequency checking circuit 1210 checks the frequency of the sync signal Vsync 1 .

Referring to FIG. 11 and FIG. 12 , when the frequency of the sync signal Vsync 1 is higher than the threshold frequency (or when the period of the sync signal Vsync 1 is smaller than the threshold period), the frequency checking circuit 1210 may serve the sync signal Vsync 1 as a multiplied sync signal Vsync 2 . For example, in the video frame F 11 , a frequency of the multiplied sync signal Vsync 2 is equal to the frequency of the vertical sync signal Vsync 1 . The threshold frequency may be determined based on a design requirement. When the frequency of the sync signal Vsync 1 is lower than the threshold frequency (or when the period of the sync signal Vsync 1 is greater than the threshold period), the frequency checking circuit 1210 may multiply the frequency of the vertical sync signal Vsync 1 to generate the multiplied sync signal Vsync 2 . Referring to the embodiment illustrated in FIG. 11 , in the sync period Psync 1 , the frequency of the multiplied sync signal Vsync 2 may be twice the frequency of the vertical sync signal Vsync 1 . In any case, the magnification of the frequency multiplication operation may be determined based on a design requirement.

The PWM signal generating circuit 1220 is coupled to the frequency checking circuit 1210 to receive the multiplied sync signal. The PWM signal generating circuit 1220 may generate the PWM signal BL 3 to the backlight driving circuit 342 according to the multiplied sync signal Vsync 2 . The PWM signal generating circuit 1220 may determine the duty ratio of the PWM signal according to the duty ratio parameter DR. The duty ratio parameter DR may be determined based on a design requirement. In addition, the PWM signal generating circuit 1220 may further determine the time of delay TD according to the delay parameter DL, i.e., determine the phase of the PWM signal BL 3 . The PWM signal generating circuit 1220 may be any type of PWM signal generating circuit/element. For example, the PWM signal generating circuit 1220 may be a PWM signal generating circuit that is well known in this field or any other PWM signal generating circuit.

FIG. 13 is a schematic waveform diagram of the PWM signal BL 3 depicted in FIG. 3 according to still another embodiment of the invention. In FIG. 13 , the vertical axis represents the voltage, and the horizontal axis represents the time. In the implementation example illustrated in FIG. 13 , it is assumed that the PWM control circuit 341 receives the vertical sync signal Vsync (i.e., video sync information) from the video processing circuit (e.g., the scaler circuit 310 ). The vertical sync signal Vsync 1 , the multiplied sync signal Vsync 2 , the time of delay TD, the video frame F 11 , the video frame F 12 , the video frame F 13 , the video frame F 14 , the video frame F 15 , the video frame F 16 , the sync period Psync 1 , the first sub-period SP 11 and the second sub-period SP 12 may refer to the description related to FIG. 11 and thus, will not be repeated.

The PWM control circuit 341 may at least divide the first sub-period SP 11 into a third sub-period SP 111 and a fourth sub-period SP 112 according to the multiplied sync signal Vsync 2 and in the same way, may at least divide the second sub-period SP 12 into sub-periods SP 121 and SP 122 . Each of the rest of the video frames F 11 , F 12 , F 13 , F 14 and F 15 illustrated in FIG. 11 may also be divided into a plurality of sub-periods. The sub-periods of the video frames F 11 , F 12 , F 13 , F 14 and F 15 illustrated in FIG. 11 may refer to the descriptions related to the video frame period F 5 , the first period P 51 , the second period P 52 , the video frame period F 6 , the first period P 61 , the second period P 62 , the video frame period F 7 , the first period P 71 , the second period P 72 , the video frame period F 8 , the first period P 81 and the second period 82 illustrated in FIG. 5 and thus, will not be repeated.

FIG. 14 is a schematic circuit block diagram illustrating the PWM control circuit 341 depicted in FIG. 3 according to still another embodiment of the invention. Referring to FIG. 13 and FIG. 14 , in the embodiment illustrated in FIG. 14 , the PWM control circuit 341 includes a frequency checking circuit 1210 , a period defining circuit 610 , a first PWM signal generating circuit 620 , a second PWM signal generating circuit 630 and a superimposing circuit 640 . The frequency checking circuit 1210 is coupled to the video processing circuit (e.g., the scaler circuit 310 ) to receive the sync signal (for example, the vertical sync signal Vsync 1 ) from the vertical sync signal. The frequency checking circuit 1210 checks the frequency of the vertical sync signal Vsync 1 and outputs the multiplied sync signal Vsync 2 . The frequency checking circuit 1210 and the multiplied sync signal Vsync 2 illustrated in FIG. 14 may be inferred with reference to the descriptions related to the frequency checking circuit 1210 and the multiplied sync signal Vsync 2 illustrated in FIG. 12 and thus, will not be repeated.

The period defining circuit 610 is coupled to the frequency checking circuit 1210 to receive the multiplied sync signal Vsync 2 . According to a timing of the vertical sync signal Vsync 2 , the period defining circuit 610 may generate a first enablement signal 611 and a second enablement signal 612 , wherein the third sub-period SP 111 and the sub-period SP 121 are defined by the first enablement signal 611 , and the fourth sub-period SP 112 and the sub-period SP 122 are defined by the second enablement signal 612 . The period defining circuit 610 , the first enablement signal 611 and the second enablement signal 612 illustrated in FIG. 14 may be inferred with reference to the descriptions related to the period defining circuit 610 , the first enablement signal 611 and the second enablement signal 612 illustrated in FIG. 6 and FIG. 7 and thus, will not be repeated.

The first PWM signal generating circuit 620 is coupled to the period defining circuit 610 to receive the first enablement signal 611 . The first PWM signal generating circuit 620 may generate the first PWM signal 621 in the third sub-period SP 111 and the sub-period SP 121 according to the first enablement signal 611 and determine a duty ratio of the first PWM signal 621 in the third sub-period SP 111 and the sub-period SP 121 according to the duty ratio parameter DR. The first PWM signal generating circuit 620 may further determine the time of delay TD of a pulse of the first PWM signal 621 in the third sub-period SP 111 according to the delay parameter DL, i.e., determine the phase of the first PWM signal 621 . The first PWM signal generating circuit 620 and the first PWM signal 621 illustrated in FIG. 14 may be inferred with reference to the descriptions related to the first PWM signal generating circuit 620 and the first PWM signal 621 illustrated in illustrated in FIG. 6 and FIG. 7 and thus, will not be repeated.

The second PWM signal generating circuit 630 is coupled to the period defining circuit 610 to receive the second enablement signal 612 . The second PWM signal generating circuit 630 may generate the second PWM signal 631 in the fourth sub-period SP 112 and the sub-period SP 122 according to the second enablement signal 612 and determine the duty ratio of the second PWM signal 631 in the fourth sub-period SP 112 and the sub-period SP 122 according to the duty ratio parameter DR. The frequency of the second PWM signal 631 is different from the frequency of the first PWM signal 621 . The second PWM signal generating circuit 630 and the second PWM signal 631 illustrated in FIG. 14 may be inferred with reference to the descriptions related to the second PWM signal generating circuit 630 and the second PWM signal 631 illustrated in illustrated in FIG. 6 and FIG. 7 and thus, will not be repeated.

The superimposing circuit 640 is coupled to the first PWM signal generating circuit 620 to receive the first PWM signal 621 . The superimposing circuit 640 is coupled to the second PWM signal generating circuit 630 to receive the second PWM signal 631 . The superimposing circuit 640 may superimpose the first PWM signal 621 and the second PWM signal 631 to obtain the PWM signal BL 3 . The superimposing circuit 640 and the PWM signal BL 3 illustrated in FIG. 14 may be inferred with reference to the descriptions related to the superimposing circuit 640 and the PWM signal BL 3 illustrated in illustrated in FIG. 6 and FIG. 7 and thus, will not be repeated.

FIG. 15 is a schematic waveform diagram of the PWM signal PL 3 depicted in FIG. 3 according to further another embodiment of the invention. In FIG. 15 , the vertical axis represents the voltage, and the horizontal axis represents the time. In the implementation example illustrated in FIG. 15 , it is assumed that the PWM control circuit 341 receives the vertical sync signal Vsync 1 (i.e., video sync information) from the video processing circuit (e.g., the scaler circuit 310 ). The vertical sync signal Vsync 1 , the multiplied sync signal Vsync 2 , the video frame F 11 , the video frame F 12 , the video frame F 13 , the video frame F 14 , the video frame F 15 , the video frame F 16 , the sync period Psync 1 , the first sub-period SP 11 and the second sub-period SP 12 may refer to the description related to FIG. 11 and/or FIG. 13 and thus, will not be repeated.

In the embodiment illustrated in FIG. 15 , the PWM signal BL 3 has pulses respectively in an initiate period and an end period in each sub-period, and has no pulse in a middle period in each sub-period. For example, the PWM signal BL 3 has pulses respectively in the initiate period and the end period in the third sub-period SP 111 without any pulse in a middle period in the third sub-period SP 111 , as illustrated in FIG. 15 . The rest of the sub-periods (for example, the sub-period SP 121 ) may be inferred with reference to the description related to the third sub-period SP 111 and thus, will not be repeated.

Based on different design demands, the blocks of the generator 340 , the PWM control circuit 341 , the backlight driving circuit 342 , the frequency checking circuit 1210 , the PWM signal generating circuit 1220 , the period defining circuit 610 , the first PWM signal generating circuit 620 , the second PWM signal generating circuit 630 and/or the superimposing circuit 640 may be implemented in a form of hardware, firmware, software (i.e., programs) or in a combination of many of the aforementioned three forms.

In terms of the hardware form, the blocks of the generator 340 , the PWM control circuit 341 , the backlight driving circuit 342 , the frequency checking circuit 1210 , the PWM signal generating circuit 1220 , the period defining circuit 610 , the first PWM signal generating circuit 620 , the second PWM signal generating circuit 630 and/or the superimposing circuit 640 may be implemented in logical circuits on an integrated circuit. Related functions of the generator 340 , the PWM control circuit 341 , the backlight driving circuit 342 , the frequency checking circuit 1210 , the PWM signal generating circuit 1220 , the period defining circuit 610 , the first PWM signal generating circuit 620 , the second PWM signal generating circuit 630 and/or the superimposing circuit 640 may be implemented in the hardware form by using hardware description languages (e.g., Verilog HDL or VHDL) or other suitable programming languages. For example, the related functions of the generator 340 , the PWM control circuit 341 , the backlight driving circuit 342 , the frequency checking circuit 1210 , the PWM signal generating circuit 1220 , the period defining circuit 610 , the first PWM signal generating circuit 620 , the second PWM signal generating circuit 630 and/or the superimposing circuit 640 may be implemented in one or more controllers, micro-controllers, microprocessors, application-specific integrated circuits (ASICs), digital signal processors (DSPs), field programmable gate arrays (FPGAs) and/or various logic blocks, modules and circuits in other processing units.

In terms of the software form and/or the firmware form, the related functions of the generator 340 , the PWM control circuit 341 , the backlight driving circuit 342 , the frequency checking circuit 1210 , the PWM signal generating circuit 1220 , the period defining circuit 610 , the first PWM signal generating circuit 620 , the second PWM signal generating circuit 630 and/or the superimposing circuit 640 may be implemented as programming codes. For example, the generator 340 , the PWM control circuit 341 , the backlight driving circuit 342 , the frequency checking circuit 1210 , the PWM signal generating circuit 1220 , the period defining circuit 610 , the first PWM signal generating circuit 620 , the second PWM signal generating circuit 630 and/or the superimposing circuit 640 may be implemented by using general purpose programming languages (e.g., C, C++or Assembly) or other suitable programming languages. The programming codes may be recorded/stored in recording media. The aforementioned recording media include a read only memory (ROM), a storage device and/or a random access memory (RAM). The programming codes may be accessed from the recording medium and executed by a computer, a central processing unit (CPU), a controller, a micro-controller or a microprocessor to accomplish the related functions. As for the recording medium, a non-transitory computer readable medium, such as a tape, a disk, a card, a semiconductor memory or a programming logic circuit, may be used. In addition, the programs may be provided to the computer (or the CPU) through any transmission medium (e.g., a communication network or radio waves). The communication network is, for example, the Internet, wired communication, wireless communication or other communication media.

Based on the above, in the circuit arrangement and the operation method thereof provided by the embodiments of the invention, a sync period can be at least divided into a first sub-period and a second sub-period. Each of the first waveform pattern in the first sub-period and the second waveform pattern in the second sub-period respectively includes at least one active pulse. The first waveform pattern in the first sub-period is substantially identical to the second waveform pattern in the second sub-period. If the length of the sync period is too long, the first waveform pattern and the second waveform pattern can achieve an effect of frequency multiplication to prevent the human eyes from perceiving the flicker of the backlight source. Thus, the circuit arrangement and the operation method thereof can achieve improving the issue of backlight flicker.

It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the disclosed embodiments without departing from the scope or spirit of the disclosure. In view of the foregoing, it is intended that the disclosure cover modifications and variations of this disclosure provided they fall within the scope of the following claims and their equivalents.