Semiconductor device and method of operating the same

This application is a continuation of U.S. patent application Ser. No. 15/802,591, filed in the U.S. Patent and Trademark Office on Nov. 3, 2017, which claims the benefit of Korean Patent Application No. 10-2017-0007143, filed on Jan. 16, 2017, in the Korean Intellectual Property Office, the disclosures of which are incorporated herein by reference in its their entireties.

1. Field

The present disclosure relates to a semiconductor device and a method of operating the same, and more particularly, to a semiconductor device which performs rectification for converting an alternating current (AC) voltage into a direct current (DC) voltage and a method of operating the semiconductor device.

2. Discussion of the Related Art

A rectifier is used to convert an AC voltage into a DC voltage. In particular, with recently developed wireless power transmission techniques for consumer electronics, in an environment using an AC signal having relatively high frequency of, e.g., 6.78 MHz (a standard wireless charging frequency today), the operation of a rectifier affects the efficiency and stability of a wireless power apparatus using the rectifier.

Accordingly, it is desirable to efficiently and stably convert an AC voltage into a DC voltage in a high-speed operating environment, particularly in devices that receive wireless power. It is also desirable to prevent the generation of a reverse current between a rectified voltage and the AC voltage.

Aspects of the disclosure provide a semiconductor device capable of efficiently and stably performing voltage conversion in a high-speed operating environment.

Aspects of the disclosure also provide a method of operating a semiconductor device capable of efficiently and stably performing voltage conversion in a high-speed operating environment.

However, aspects of the disclosure are not restricted to the one set forth herein. The above and other aspects of the disclosure will become more apparent to one of ordinary skill in the art to which the disclosure pertains by referencing the detailed description of the disclosure given below.

According to an aspect of the disclosure, there is provided a semiconductor device including a comparator which compares a first voltage with a rectified voltage and provides a second voltage in accordance with the comparison. A timer circuit may operate a timer according to the second voltage and output a third voltage in correspondence with an operation time of the timer. A driver may drive a transistor with a fourth voltage generated by the driver according to the third voltage. A calibration circuit may generate a timer calibration signal based on the second voltage and the fourth voltage. The timer calibration signal may be provided to the timer circuit and used to calibrate the operation time of the timer.

According to another aspect of the disclosure, there is provided a semiconductor device including a first comparator which compares a voltage level of a first node with a voltage level of a rectified voltage to control a voltage level of a second node; a timer circuit which operates a timer according to the voltage level of the second node and controls a voltage level of a third node; a driver which drives a transistor by controlling a voltage level of a fourth node according to the voltage level of the third node; and a protection circuit which monitors a current flowing between the rectified voltage and the first node and, when a reverse current is generated, generates a timer stop signal for stopping the operation of the timer and provides the timer stop signal to the timer circuit.

According to still another aspect of the disclosure, there is provided a method of operating a semiconductor device including comparing a voltage level of a first node with a voltage level of a rectified voltage; operating a timer of a timer circuit which uses a second node as an input by controlling a voltage level of the second node according to the comparison result; driving a transistor by controlling a voltage level of a fourth node, which corresponds to an output of a driver, using the driver which operates using a third node corresponding to an output of the timer circuit as an input; and providing a timer calibration signal for calibrating an operation time of the timer to the timer circuit by monitoring the voltage level of the second node and the voltage level of the fourth node.

These and/or other aspects will become apparent and more readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings in which:

FIG. 1 is a block diagram of an example rectifier to which semiconductor devices according to embodiments can be applied;

FIG. 2 is a circuit diagram of a semiconductor device according to an embodiment;

FIGS. 3, 4 and 5 are each a timing diagram illustrating a respective operation example of the semiconductor device according to the embodiment of FIG. 2 ;

FIG. 6 is a circuit diagram of a semiconductor device according to an embodiment;

FIG. 7 is a timing diagram illustrating an operation example of the semiconductor device according to the embodiment of FIG. 6 ;

FIG. 8 is a circuit diagram of a semiconductor device according to an embodiment;

FIG. 9 is a circuit diagram of a semiconductor device according to an embodiment;

FIG. 10 is a circuit diagram of a semiconductor device according to an embodiment;

FIG. 11 is a circuit diagram of a semiconductor device according to an embodiment;

FIG. 12 is a circuit diagram of a semiconductor device according to an embodiment; and

FIG. 13 is a circuit diagram of a semiconductor device according to an embodiment.

FIG. 1 is a block diagram of an example rectifier 1 to which semiconductor devices according to embodiments can be applied. Rectifier 1 may be implemented as a hybrid active rectifier using a metal oxide semiconductor field effect transistor (MOSFET) as a switching element. Other rectifier types and configurations are also contemplated.

The example rectifier 1 may include four transistors N 1 through N 4 . Transistors N 1 and N 2 are connected in parallel to each other and are turned on and off at different times. Transistors N 3 and N 4 are connected in parallel to each other and are connected in series with transistors N 1 and N 2 , respectively. The transistors N 3 and N 4 are likewise turned on and off at different times.

In the current example, the transistors N 1 through N 4 are implemented as n-channel metal oxide semiconductor (NMOS) transistors. An alternating current (AC) voltage supplied from an AC power supply 10 is applied across nodes AC_P and AC_N. The resulting voltage at node AC_P, referenced to ground (GND), is referred to hereafter as V AC_P while the voltage at node AC_N, referenced to GND, will be denoted V AC_N . A source of the transistor N 1 and a drain of the transistor N 3 may each be connected to the node AC_P, and a source of the transistor N 2 and a drain of the transistor N 4 may be connected to the node AC_N.

The AC voltage is converted into a rectified voltage Vrect, which is a direct current (DC) voltage, by the turn-on and turn-off operations of the transistors N 1 through N 4 .

Specifically, in a period during which V AC_P minus V AC_N is positive, the transistors N 1 and N 4 are turned on, and the transistors N 2 and N 3 are turned off. To this end, a semiconductor device 100 turns on the transistor N 1 in a period approximately coinciding with V AC_P minus V AC_N being positive. This period also substantially coincides with V AC_P (referenced to GND) being positive, since transistor N 4 is ON and the drain to source voltage V DS across transistor N 4 is close to zero, whereby nodes GND and AC_N are at nearly the same potential during this time period. (Current flow is from source to drain in this example.) This period may be referred to as a first half cycle of the AC voltage cycle. In addition, since the transistor N 4 is implemented to be gated (self-driving connection) by the voltage V AC_P , it is turned on in the period during which V AC_P is positive. The semiconductor device 100 precisely controls the operation of the transistor N 1 particularly in a high-speed operating environment to enable the rectifier 1 to efficiently and stably convert AC voltage. This will be described in detail later with reference to FIGS. 2 through 13 .

Transistors N 2 and N 3 are switched on and off in a complementary manner to transistors N 1 and N 4 , respectively. Thus, in a period during which V AC_N minus V AC_P is positive, the transistors N 1 and N 4 are turned off, and the transistors N 2 and N 3 are turned on (and V AC_N referenced to GND is thereby positive). To this end, a semiconductor device 200 turns on the transistor N 2 during a period approximately coinciding with V AC_N being positive. In addition, since the transistor N 3 is implemented to be gated (self-driving connection) by V AC_N , it is turned on in the period during which V AC_N (referenced to GND) is positive. As described below, semiconductor device 200 precisely controls the operation of the transistor N 2 particularly in the high-speed operating environment to enable the rectifier 1 to efficiently and stably convert AC voltage.

In the current example, Schottky barrier diodes Dl through D 4 having a small voltage drop and a high switching speed may be connected in parallel (across the drain to source path) with transistors N 1 through N 4 , respectively. Note, however, that the detailed configuration of the rectifier 1 may vary depending on the purpose of implementation.

It should be noted that the scope of the disclosure is not limited to a particular form of rectifier. Thus, rectifier 1 can also be implemented in various other ways.

Various implementations of the semiconductor devices 100 and 200 will hereinafter be described with reference to FIGS. 2 through 13 . In implementing the rectifier 1 , semiconductor devices 100 and 200 may have the same configurations and operate the same way but with complementary timing to achieve the desired on-off switching of the transistors N 1 and N 2 .

Alternatively, they may have different configurations, so long as the transistor switching objectives are realized.

In FIGS. 2 through 13 , only the semiconductor device 100 which controls the operation of the transistor N 1 is described in order to avoid redundancy. However, the same description is applicable to the semiconductor device 200 which controls the operation of the transistor N 2 .

FIG. 2 is a circuit diagram of a semiconductor device 100 a according to an embodiment. Semiconductor device 100 a includes a first comparator 110 , a timer circuit 120 , a driver 130 , and a calibration circuit 140 . Device 100 a is electrically connected to transistor N 1 by a node NC corresponding to a gate of the transistor N 1 and node AC_P corresponding to a source of the transistor N 1 .

The comparator 110 controls the voltage level V NA of a node NA by comparing V AC_P with a rectified voltage Vrect.

For example, the comparator 110 may compare V AC_P with Vrect and output logic low to the node NA in a period during which V AC_P is lower than Vrect. In a period during which V AC_P is equal to or higher than Vrect, the comparator 110 may output V NA as logic high. However, due to a delay required for circuit operation, V NA may transition later than when V AC_P becomes equal to Vrect. (See e.g. delay d 1 of FIG. 3 .)

In some embodiments, the comparator 110 may comprise a full active rectifier (FAR) comparator. The comparator 110 may be controlled by an enable signal EN for determining whether to operate the comparator 110 .

The timer circuit 120 operates a timer according to V NA and controls the voltage level V NB of a node NB.

For example, the timer circuit 120 operates the timer included therein when V NA becomes logic high. When the operation of the timer starts, V NB transitions to logic high. When the operation of the timer ends, V NB transitions to logic low. (See e.g. the period A of FIG. 3 , which is an example period of the timer operation.)

The timer circuit 120 controls the time during which V NB is maintained at logic high by using the timer. The timer circuit 120 is configured to dynamically set a time duration for the timer's operation. Accordingly, the timer circuit 120 can increase or decrease the time during which the V NB is maintained at logic high by adjusting the operation of the timer to meet the requirements for implementation purposes or operating environment.

The timer circuit 120 may receive a timer calibration signal for calibrating the operation time of the timer from the calibration circuit 140 , which will be described later, and may change the maximum time value of the timer according to the time calibration signal.

The driver 130 drives the transistor N 1 by controlling the voltage level V NC of the node NC according to V NB .

For example, when V NB becomes logic high, the driver 130 may turn the voltage level V NC of the node NC corresponding to the gate of the transistor N 1 to logic high, thereby turning on transistor N 1 . In addition, when V NB becomes logic low, the driver 130 may turn V NC to logic low, thereby turning off transistor N 1 . However, due to a delay required for circuit operation, V NC may transition later than when V NB transitions. (See e.g. delay d 2 of FIG. 3 .)

In some embodiments, the driver 130 may include a high-performance driver for a FAR. In this case, the driver 130 may be enabled under the control of a node BST to which a boost voltage Vbst is applied via a diode D 5 .

The calibration circuit 140 receives V NA and V NC and based on these voltages, generates the timer calibration signal for calibrating the operation time of the timer, and provides the timer calibration signal to the timer circuit 120 .

The calibration circuit 140 “generates a judge time window” of a duration J when V NC transitions from logic high to logic low. (See e.g. judge time window W of FIG. 3 , of a duration J.) That is, calibration circuit 140 starts an internal timer that counts for the period J, and a voltage is monitored during this period. Specifically, calibration circuit 140 monitors V NA during a time corresponding to the judge time window and generates a timer calibration signal based on the monitoring result.

For example, when V NA transitions from logic high to logic low during the judge time window, the calibration circuit 140 may determine that the operation time of the transistor N 1 is within a normal range. Accordingly, the calibration circuit 140 may not thereafter provide a timer calibration signal to the timer circuit 120 .

In another example, when V NA is maintained at the logic high or logic low throughout the judge time window, the calibration circuit 140 may determine that the operation time of the transistor N 1 is outside the normal range.

When V NA is maintained at logic high throughout the judge time window, the calibration circuit 140 may thereafter provide a timer calibration signal to timer circuit 120 for extending the operation time of its timer. Accordingly, the operation time of the transistor N 1 may be extended in a next cycle.

On the other hand, when V NA is maintained at logic low throughout the judge time window, the calibration circuit 140 may thereafter provide a timer calibration signal to timer circuit 120 for shortening the operation time of its timer. Accordingly, the operation time of the transistor N 1 may be shortened in the next cycle.

The timer circuit 120 may receive the timer calibration signal for extending or shortening the operation time of the timer from the calibration circuit 140 and change the maximum time value of the timer according to the timer calibration signal.

FIGS. 3 through 5 are timing diagrams illustrating operation examples of the semiconductor device 100 a according to the embodiment of FIG. 2 .

Specifically, FIG. 3 illustrates a case where the operation time of the transistor N 1 is within the normal range, FIG. 4 illustrates a case where the operation time of the transistor N 1 is not within the normal range and needs to be extended, and FIG. 5 illustrates a case where the operation time of the transistor N 1 is not within the normal range and needs to be shortened.

Referring to FIG. 3 , when AC is applied from the AC power supply 10 of FIG. 1 , V AC_P starts to rise at a time t 0 .

The comparator 110 , which compares V AC_P with Vrect, outputs logic low to the node NA (V NA is logic low) at time t 0 . Then, when V AC_P reaches Vrect at a time t 1 , the comparator 110 transitions V NA to logic high.

V NA transitions to logic high at a time t 2 after a delay d 1 . At the time t 2 , the timer circuit 120 operates the timer according to V NA and transitions V NB to logic high. The timer started at the time t 2 continues to operate for a time period A until a time t 5 . Meanwhile, at time t 2 , V AC_P has risen to a level slightly above Vrect.

At a time t 3 after a delay d 2 , the voltage level V NC of the node NC transitions to logic high. Accordingly, the transistor N 1 is turned on at time t 4 after a short delay, and V AC_P drops to become approximately equal to Vrect by virtue of the near zero voltage differential across the source to drain terminals of transistor N 1 . Thus, returning momentarily to FIG. 1 , during approximately a one half AC cycle (“first half of AC cycle”) following time t 4 in which transistor N 1 is turned on, current flow is as follows, assuming a start point at node AC_P: from node AC_P through the source-drain of transistor N 1 to the node at which Vrect is present (Vrect node); from the Vrect node through a load (not shown) connected between the Vrect node and GND; from GND through the source-drain of transistor N 4 (which is also turned on in this period) to node AC_N; and from node AC_N back to AC_P. Following this approximate one half AC cycle, a “second half of AC cycle” begins in which transistors N 2 and N 3 are shortly turned on in a similar manner through similar control by control circuit 200 , while transistors N 1 and N 4 are turned off. Here, current likewise flows from the Vrect node through the load to GND, i.e., in the same direction as in the first half of the cycle. Accordingly, current flows in the same direction throughout both halves of the AC cycle, whereby the AC voltage applied by AC power supply 10 is rectified and converted to a DC voltage. If, however, an undesirable reverse current flows, when the transistor on-off timing is uncalibrated (and misaligned with the AC cycle), such a reverse current flows in the opposite direction, e.g. from the Vrect node through the drain to source path of transistor N 1 to node AC_P.

Referring still to FIG. 3 , the timer preset by the timer circuit 120 ends at a time t 5 .

Thus, V NC transitions to logic low at a time t 6 after a delay d 3 . Accordingly, the transistor N 1 is turned off, so that current flow is shortly thereafter switched to the path of the second half AC cycle (through transistors N 2 and N 3 ) as described above.

After V NC transitions to logic low at the time t 6 , the calibration circuit 140 generates a judge time window W (by means of a signal JT). Specifically, the calibration circuit 140 generates the judge time window W of a specific time duration J from a time t 7 after a delay d 4 from the time t 6 . Then, the calibration circuit 140 monitors V NA during the time of the judge time window W.

In the current example, V NA transitions from logic high to logic low at a time t 9 included in the judge time window W. Specifically, when V AC_P falls to reach Vrect at a time t 8 , V NA transitions to logic low at the time t 9 after a delay d 5 .

In this case, the calibration circuit 140 may determine that the operation time of the transistor N 1 is within the normal range. Accordingly, the calibration circuit 140 does not provide the timer calibration signal to the timer circuit 120 , and the operation time A of the timer of the timer circuit 120 is maintained unchanged even in the next cycle for converting the first AC voltage into the rectified voltage Vrect.

Referring to FIG. 4 , when the first AC voltage is applied from the AC power supply 10 of FIG. 1 , V AC_P starts to rise at a time t 0 .

The comparator 110 which compares V AC_P with Vrect outputs V NA at logic low. Then, when V AC_P reaches Vrect at a time t 1 , the comparator 110 transitions V NA to logic high.

V NA transitions to logic high a time t 2 after a delay d 1 . At the time t 2 , the timer circuit 120 operates the timer according to V NA and transitions V NB to logic high. The timer started at the time t 2 continues to operate for a time period B until a time t 5 .

At a time t 3 after a delay d 2 , the voltage level of the node NC transitions to logic high. Accordingly, the transistor N 1 is turned on, and current flow during the first half of the AC cycle is as described above from a time t 4 .

The timer preset by the timer circuit 120 ends at the time t 5 .

Thus, V NC transitions to logic low at a time t 6 after a delay d 3 . Accordingly, the transistor N 1 is turned off, and the current flow is no longer through transistor N 1 .

After V NC transitions to logic low at the time t 0 , the calibration circuit 140 generates a judge time signal JT with window W. Specifically, the calibration circuit 140 generates the judge time window W of a specific time duration J from a time t 7 after a delay d 4 from the time t 6 . Then, the calibration circuit 140 monitors V NA during the period J of the judge time window W.

In the current example of FIG. 4 , V NA transitions from logic high to logic low at a time t 9 outside the judge time window W. Specifically, when V AC_P falls to reach Vrect at a time t 8 , V NA transitions to logic low at the time t 9 after a delay d 5 .

Therefore, V NA is maintained at logic high throughout the period J of the judge time window W. In this case, the calibration circuit 140 may determine that the operation time of the transistor N 1 is not within the normal range. In particular, in this case, although average overall current flow is still in the direction from the Vrect node through the output load to GND over the entire AC cycle, overall efficiency of the rectifier circuit 1 is reduced due to the short operation time of the timer. That is, there is a reverse current during a small portion of the overall AC cycle, which reduces efficiency.

To prevent such inefficiency, the calibration circuit 140 provides the timer calibration signal for extending the operation time of the timer to the timer circuit 120 . The timer circuit 120 which receives the timer calibration signal extends the operation time of the timer in the next cycle for converting the AC voltage into the rectified voltage Vrect. This can reduce the inefficiency of not fully converting the AC voltage over both halves of the AC cycle due to the short operation time of the timer in the previous cycle.

Referring to FIG. 5 , when V AC_P is generated from the application of AC power supply 10 of FIG. 1 , V AC_P starts to rise at a time t 0 .

The comparator 110 which compares V AC_P with Vrect outputs V NA as logic low. Then, when V AC_P reaches Vrect at a time t 1 , the comparator 110 transitions V NA to logic high.

V NA transitions to logic high at a time t 2 after a delay d 1 . At the time t 2 , the timer circuit 120 operates the timer according to V NA and transitions V NB to logic high. The timer started at the time t 2 continues to operate for a time period C until a time t 5 .

At a time t 3 after a delay d 2 , V NC transitions to logic high. Accordingly, the transistor N 1 is turned on, and current flows in the direction from the node of Vrect through an output load to GND from a time t 4 .

V NA transitions from logic high to logic low at a time t 6 outside a judge time window W. Specifically, when V AC_P falls to reach Vrect at the time t 5 , V NA transitions to logic low at the time t 6 after a delay d 5 .

The timer preset by the timer circuit 120 ends at the time t 6 .

Thus, V NC transitions to logic low at a time t 7 after a delay d 3 . Accordingly, the transistor N 1 is turned off, and the process of conversion during the first half of the AC cycle ends.

After V NC transitions to logic low at the time t 7 , the calibration circuit 140 generates the judge time window W. Specifically, the calibration circuit 140 generates the judge time window W of a specific time duration J from a time t 8 after a delay d 4 from the time t 7 . Then, the calibration circuit 140 monitors V NA during the period J of the judge time window W.

In the current example, V NA is maintained at logic low in a period corresponding to the judge time window W. In this case, the calibration circuit 140 may determine that the operation time of the transistor N 1 is not within the normal range. In particular, in this case, although a period during which the first AC voltage can stably be converted into the rectified voltage Vrect has passed, the conversion of the first AC voltage continues until the time t 7 due to the long operation time of the timer. This can generate a reverse current and reduce efficiency.

To reduce such instability and inefficiency, the calibration circuit 140 provides the timer calibration signal for shortening the operation time of the timer to the timer circuit 120 . The timer circuit 120 which receives the timer calibration signal shortens the operation time of the timer in the next cycle for converting the first AC voltage into the rectified voltage Vrect. This can reduce the inability to convert the voltage V AC_P stably and efficiently due to the long operation time of the timer in the previous cycle.

According to the various embodiments described above, the length of a period during which V AC_P is converted into the rectified voltage Vrect is set precisely using the timer, and the operation time of the timer is adjusted by evaluating the stability and efficiency of voltage conversion in the previous cycle. Therefore, voltage conversion can be performed in an improved manner in the next cycle. Through operation of the timer, the percentage of time that the output current flows in the same direction, i.e., as direct current, is increased. Accordingly, voltage conversion can be performed efficiently and stably in the high-speed environment.

FIG. 6 is a circuit diagram of a semiconductor device 100 b according to an embodiment.

Referring to FIG. 6 , like the semiconductor device 100 a according to the embodiment of FIG. 2 , the semiconductor device 100 b includes a first comparator 110 , a timer circuit 120 , a driver 130 , and a calibration circuit 140 . However, the semiconductor device 100 b differs from the semiconductor device 100 a of FIG. 2 in that it further includes a protection circuit ( 150 and 160 ).

The protection circuit ( 150 and 160 ) is designed to prevent a rectifier 1 from being damaged due to the continuation of voltage conversion even if a reverse current is generated from a node of rectified voltage Vrect through transistor N 1 to the node AC_P.

Specifically, when the reverse current is generated from the rectified voltage Vrect to the node AC_P, the protection circuit ( 150 and 160 ) generates a timer stop signal for stopping the operation of a timer of the timer circuit 120 and provides the timer stop signal to the timer circuit 120 . The timer circuit 120 stops the operation of the timer according to the timer stop signal, and the driver 130 turns off transistor N 1 to stop the voltage conversion.

In the current embodiment, the protection circuit ( 150 and 160 ) includes a second comparator 150 and a logic gate 160 .

The second comparator 150 determines whether the difference between Vrect and V AC_P exceeds an offset voltage Voff and provides the determination result (voltage V ND ) at node ND. For example, when the offset voltage Voff is set to 200 mV, it is determined whether the difference between Vrect and the falling voltage level of the node AC_P exceeds 200 mV.

The logic gate 160 generates the timer stop signal by performing a logical operation on V NC and V ND . It can be determined from V NC whether the transistor N 1 is being operated, that is, whether the voltage conversion at that time is being performed. In addition, it can be determined from V ND whether the difference between Vrect and V AC_P exceeds the offset voltage Voff. Therefore, the logic gate 160 may determine whether to generate the timer stop signal in consideration of V NC and V ND

In the current embodiment, the logic gate 160 is implemented as an AND logic gate, but can alternatively be implemented as any other logic gate depending on the specific configuration of the circuit.

FIG. 7 is a timing diagram illustrating an operation example of the semiconductor device 100 b according to the embodiment of FIG. 6 .

Referring to FIG. 7 , when the first AC voltage is applied from the AC power supply 10 of FIG. 1 , V AC_P starts to rise at a time t 0 . On the other hand, the voltage level of a node AC_N to which the second AC voltage is applied falls as indicated by a dotted line.

The comparator 110 which compares V AC_P with Vrect outputs logic low to a node NA. Then, when V AC_P reaches Vrect at a time t 1 , V NA transitions to logic high.

V NA transitions to logic high at a time t 2 after a delay d 1 . At the time t 2 , the timer circuit 120 operates the timer according to V NA and transitions V NB to logic high. The timer started at the time t 2 continues to operate for a time period D until a time t 5 .

At a time t 3 after a delay d 2 , the voltage level of the node NC transitions to logic high. Accordingly, the transistor N 1 is turned on, and the first AC voltage is converted into the rectified voltage Vrect from a time t 4 .

VNA transitions from logic high to logic low at a time t 6 outside a judge time window. Specifically, when V AC_P falls to reach Vrect at the time t 5 , V NA transitions to logic low at the time t 6 after a delay d 5 .

Even though V AC_P is falling, the timer preset by the timer circuit 120 ends at a time t 9 . Accordingly, there is a risk that a reverse current will be generated in a period from the time t 7 to the time t 9 .

To prevent the generation of the reverse current, the protection circuit ( 150 and 160 ) generates a timer stop signal for stopping the operation of the timer of the timer circuit 120 at a node NE. Specifically, the protection circuit ( 150 and 160 ) generates the timer stop signal at the time t 7 when the transistor N 1 is operating and when the difference between Vrect and V AC_P exceeds the offset voltage Voff.

The timer circuit 120 stops the operation of the timer in response to the timer stop signal received via the node NE, and the driver 130 interrupts the voltage conversion by turning off the transistor N 1 after a delay d 6 from the time t 7 .

Accordingly, the semiconductor device 100 b can perform voltage conversion efficiently and stably in a high-speed environment and prevent the rectifier 1 from being damaged due to the continuation of the voltage conversion even if a reverse current is generated from the rectified voltage Vrect to the node AC_P.

FIG. 8 is a circuit diagram of a semiconductor device 100 c according to an embodiment.

Referring to FIG. 8 , like the semiconductor device 100 a according to the embodiment of FIG. 2 , the semiconductor device 100 c according to the current embodiment includes a first comparator 110 , a timer circuit 120 , a driver 130 , and a calibration circuit 140 . Semiconductor device 100 c differs from the semiconductor device 100 a in that it further includes a delay control circuit 170 .

The delay control circuit 170 receives externally calculated delay time information, generates a delay signal for controlling the start time of the timer operation of the timer circuit 120 based on the delay time information, and provides the delay signal to the timer circuit 120 .

In some embodiments, the delay control circuit 170 may receive the delay time information from a microcontroller.

The timer circuit 120 receives the delay signal from the delay control circuit 170 via a node NF and sets the start time of the timer operation based on the delay signal.

Accordingly, the semiconductor device 100 c can be more precisely controlled to maximize the voltage conversion efficiency in cooperation with an external device (e.g., a microcontroller) while performing voltage conversion efficiently and stably in a high-speed environment.

FIG. 9 is a circuit diagram of a semiconductor device 100 d according to an embodiment. Similar to semiconductor device 100 c of FIG. 8 , the semiconductor device 100 d according to the current embodiment includes a first comparator 110 , a timer circuit 120 , a driver 130 , a calibration circuit 140 and a delay control circuit 170 . Semiconductor device 100 d differs from device 100 c by further including a protection circuit ( 150 and 160 ) described above with reference to FIG. 6 .

Accordingly, the semiconductor device 100 d can perform voltage conversion efficiently and stably in a high-speed environment and prevent a rectifier 1 from being damaged due to the continuation of the voltage conversion even if a reverse current is generated from a rectified voltage Vrect to a node AC_P. In addition, the semiconductor device 100 d can be more precisely controlled to maximize the voltage conversion efficiency in cooperation with an external device (e.g., a microcontroller).

FIG. 10 is a circuit diagram of a semiconductor device 100 e according to an embodiment. Semiconductor device 100 e includes a first comparator 110 , a timer circuit 120 , and a calibration circuit 140 , but differs from device 100 a of FIG. 2 by including a plurality of drivers 131 , 133 , and 135 instead of the driver 130 ; and further includes a segment control circuit 180 .

In this embodiment, a rectifier 1 includes additional transistors N 1 ′ and N 1 ″ connected in parallel to transistor N 1 . The transistors N 1 , N 1 ′ and N 1 ″ may be used to change the total size of a transistor according to the specific load state of the rectifier 1 . The drivers 131 , 133 , and 135 drive the transistors N 1 , N 1 ′, and N 1 ″, respectively.

The segment control circuit 180 receives a transistor segment control signal from the exterior and controls the operation of the transistors N 1 and N 1 ″ connected in parallel with the transistor N 1 . That is, the segment control circuit 180 adjusts the total size of a transistor by turning on or off the transistors N 1 and N 1 ″ according to the operating state or environment of the rectifier 1 .

In some embodiments, the segment control circuit 180 may receive the transistor segment control signal from a microcontroller.

The drivers 133 and 135 may receive signals for controlling the transistors N 1 and N 1 ″ from the segment control circuit 180 via nodes NG and NH and turn on or off the transistors N 1 ′ and N 1 ″ in response to the received signals.

Accordingly, the semiconductor device 100 e can be more precisely controlled to maximize the voltage conversion efficiency by changing the size of a transistor according to the specific load state of the rectifier 1 in operation with an external device (e.g., a microcontroller) while performing voltage conversion efficiently and stably in a high-speed environment.

FIG. 11 is a circuit diagram of a semiconductor device 100 f according to an embodiment. Semiconductor device 100 f includes a first comparator 110 , a timer circuit 120 , a plurality of drivers 131 , 133 and 135 , a calibration circuit 140 , and a segment control circuit 180 . Semiconductor device 100 f differs from device 100 e of FIG. 10 in that it further includes a protection circuit ( 150 and 160 ) described above with reference to FIG. 6 .

Accordingly, the semiconductor device 100 f can perform voltage conversion efficiently and stably in a high-speed environment and prevent a rectifier 1 from being damaged due to the continuation of the voltage conversion even if a reverse current is generated from a rectified voltage Vrect to a node AC_P. In addition, the semiconductor device 100 f can be more precisely controlled to maximize the voltage conversion efficiency by changing the size of a transistor according to the specific load state of the rectifier 1 in cooperation with an external device (e.g., a microcontroller).

FIG. 12 is a circuit diagram of a semiconductor device 100 g according to an embodiment. Semiconductor device 100 g includes a first comparator 110 , a timer circuit 120 , a plurality of drivers 131 , 133 and 135 , a calibration circuit 140 , a delay control circuit 170 , and a segment control circuit 180 .

Accordingly, semiconductor device 100 g differs from device 100 e of FIG. 10 by including delay control circuit 170 . As described earlier in connection with FIG. 8 , the inclusion of a delay control circuit 170 allows semiconductor device 100 g to be more precisely controlled to maximize the voltage conversion efficiency in cooperation with an external device (e.g., a microcontroller) while performing voltage conversion efficiently and stably in a high-speed environment.

FIG. 13 is a circuit diagram of a semiconductor device 100 h according to an embodiment.

Referring to FIG. 13 , the semiconductor device 100 h according to the embodiment includes a first comparator 110 , a timer circuit 120 , a plurality of drivers 131 , 133 and 135 , a calibration circuit 140 , a protection circuit ( 150 and 160 ), a delay control circuit 170 , and a segment control circuit 180 .

Accordingly, by including all of the delay control circuit, the protection circuit and the segment control circuit, the semiconductor device 100 g can perform voltage conversion efficiently and stably in a high-speed environment and prevent a rectifier 1 from being damaged due to the continuation of the voltage conversion even if a reverse current is generated from a rectified voltage Vrect to a node AC_P. In addition, the semiconductor device 100 g can be more precisely controlled to maximize the voltage conversion efficiency in cooperation with an external device (e.g., a microcontroller).

A method of operating a semiconductor device according to various embodiments includes comparing the voltage level of a node AC_P with the voltage level of a rectified voltage Vrect and operating a timer of a timer circuit 120 that uses a node NA as an input by controlling V NA according to the comparison result.

The method includes driving a transistor N 1 by controlling the voltage level of a node NC, which corresponds to an output of a driver 130 , using the driver 130 which operates using a node NB corresponding to an output of the timer circuit 120 as an input.

The method also includes providing a timer calibration signal for calibrating the operation time of the timer to the timer circuit 120 by monitoring the voltage level of the node NA and the voltage level of the node NC.

In some embodiments, the operating of the timer of the timer circuit 120 may include operating the timer of the timer circuit 120 by controlling the voltage level of the node NA when the voltage level of the node AC_P rises to the voltage level of the rectified voltage Vrect.

In some embodiments, the providing of the timer calibration signal to the timer circuit 120 may include generating a judge time window in response to a change in the voltage level of the node NC, monitoring the voltage level of the node NA corresponding to the judge time window, and generating the timer calibration signal based on the monitoring result.

The method may further include generating a timer stop signal for stopping the operation of the timer and providing the timer stop signal to the timer circuit 120 when a reverse current is generated from the rectified voltage Vrect to the node AC_P.

In addition, the method may further include receiving externally calculated delay time information, generating a delay signal for controlling the start time of the timer operation of the timer circuit 120 based on the delay time information, and providing the delay signal to the timer circuit 120 .

In addition, the method may further include receiving a transistor segment control signal from the outside and controlling the operation of the transistor N 1 and transistors N 1 ′ and N 1 ″ connected in parallel to the transistor N 1 .

It is noted here that the above-described comparators and drivers are each configured by circuitry. As such, any of the comparators may alternatively be called a comparator circuit, and any of the drivers can alternatively be called a driver circuit.

Although example embodiments of the present disclosure have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the disclosure as set forth in the accompanying claims.