Logic circuit

This application is based on and claims priority under 35 USC 119 from Japanese Patent Application No. 2019-059398 filed on Mar. 26, 2019, the disclosure of which is incorporated by reference herein.

The present disclosure relates to a logic circuit.

The following technology is known as technology relating to a logic circuit that includes a CMOS (Complementary Metal-Oxide Semiconductor) inverter.

A CMOS inverter circuit in which a first P-channel FET and an N-channel FET are connected together in series and are connected between a power supply and a ground, and a gate of the first P-channel FET and a gate of the N-channel FET are connected to an input terminal, and the connection point between the first P-channel FET and the N-channel FET is connected to an output terminal is described in, for example, Japanese Unexamined Patent Application Laid-Open (JP-A) No. H09-214313 (Patent Document 1). This CMOS inverter circuit has a switch control device that connects a switch element and a second P-channel that is connected in series to this switch element in parallel to the first P-channel FET, and connects a gate of the second P-channel FET to an input terminal, and when the voltage of the power supply, which is being monitored, exceeds a predetermined value, turns ON the switch element.

In a CMOS inverter that is formed so as to include an N-channel type of MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) and a P-channel type of MOSFET, during a transition period between a point when the power supply is turned on and a point when the power supply voltage rises to a prescribed level, in some cases a phenomenon occurs in which the input of the CMOS inverter is undefined and the output thereof is undefined, or alternatively, the output logic is inverted. As a consequence of this, the problem has sometimes arisen that a signal having an unintended logic level is output from the CMOS inverter, resulting in the system malfunctioning.

The present disclosure was conceived in consideration of the above-described problems and it is an object thereof to provide a logic circuit that makes it possible to inhibit a signal having an unintended logic level from being output when a power supply is turned on.

A logic circuit according to the present disclosure includes an inverter that outputs from an output terminal a signal created by inverting the logic of a signal input into an input terminal, a first transistor that is connected to the input terminal in such a way as to maintain an OFF state, and a second transistor that is connected to the output terminal in such a way as to maintain an OFF state.

According to the present disclosure there is provided a logic circuit that makes it possible to inhibit a signal having an unintended logic level from being output when a power supply is turned on.

Exemplary embodiments of the present disclosure will be described in detail based on the following figures, wherein:

FIG. 1 is a view showing an example of a structure of a logic circuit according to a comparative example;

FIG. 2 is a view showing a structure of a circuit block according to the comparative example;

FIG. 3A is a view showing an example of a voltage waveform of each node when a power supply of the circuit block according to the comparative example is turned on;

FIG. 3B is a view showing an example of a voltage waveform of each node when the power supply of the circuit block according to the comparative example is turned on;

FIG. 3C is a view showing an example of a voltage waveform of each node when the power supply of the circuit block according to the comparative example is turned on;

FIG. 4A is a view showing an example of the structure of the logic circuit according to the comparative example;

FIG. 4B is a view showing an example of the structure of the logic circuit according to the comparative example;

FIG. 4C is a view showing an example of the structure of the logic circuit according to the comparative example;

FIG. 5 is a view showing an example of a structure of a logic circuit according to an exemplary embodiment of the present disclosure;

FIG. 6 is a view showing a structure of a circuit block according to the exemplary embodiment of the present disclosure;

FIG. 7 is a view showing an example of a voltage waveform of each node when a power supply of the circuit block according to the exemplary embodiment of the present disclosure is turned on;

FIG. 8 is a view showing a structure of a circuit block according to another exemplary embodiment of the present disclosure;

FIG. 9 is a view showing a structure of a circuit block according to another exemplary embodiment of the present disclosure;

FIG. 10 is a view showing an example of a voltage waveform of each node when the power supply of the circuit block according to the exemplary embodiment of the present disclosure is turned on;

FIG. 11 is a view showing a structure of a circuit block according to another exemplary embodiment of the present disclosure;

FIG. 12 is a view showing an example of a voltage waveform of each node when the power supply of the circuit block according to the exemplary embodiment of the present disclosure is turned on;

FIG. 13 is a view showing a structure of a circuit block according to another exemplary embodiment of the present disclosure; and

FIG. 14 is a view showing an example of a voltage waveform of each node when the power supply of the circuit block according to the exemplary embodiment of the present disclosure is turned on.

Firstly, before a logic circuit according to exemplary embodiments of the present disclosure is described, a logic circuit according to a comparative example will be described.

FIG. 1 is a view showing an example of the structure of a logic circuit 1 X 1 according to a comparative example. The logic circuit 1 X 1 according to the comparative example forms part of a typical CMOS inverter, and is formed so as to include a P-channel type of MOSFET 10 P that is connected to a power supply line, and an N-channel type of MOSFET 10 N that is connected to a ground line. A gate of the MOSFET 10 P and a gate of the MOSFET 10 N are each connected to an input terminal 11 , while a drain of the MOSFET 10 P and a drain of the MOSFET 10 N are each connected to an output terminal 12 .

FIG. 2 is a view showing the structure of a circuit block 100 X that is formed so as to include the logic circuit 1 X 1 according to the comparative example. The circuit block 100 X is formed so as to include the logic circuit 1 X 1 , a logic circuit 1 X 0 that is provided at the stage immediately preceding the logic circuit 1 X 1 , and a logic circuit 1 X 2 that is provided at the stage immediately following the logic circuit 1 X 1 . In other words, the circuit block 100 X is formed by cascode-connecting the logic circuits 1 X 0 , 1 X 1 , and 1 X 2 . The logic circuits 1 X 0 and 1 X 2 have the same structure as the logic circuit 1 X 1 shown in FIG. 1 .

When the power supply is turned on, a power supply voltage VDD rises to a prescribed level, and until a system input is confirmed, a potential of an input node IX of the circuit block 100 X remains undefined (i.e., in a high impedance state). Here, a gate threshold value voltage Vth of the P-channel type MOSFET (hereinafter, this will be referred to as a PMOS) is taken as Vtp, and the leakage current thereof is taken as Ipk. Moreover, a gate threshold value voltage Vth of the N-channel type MOSFET (hereinafter, this will be referred to as an NMOS) is taken as Vtn, and the leakage current thereof is taken as Ink.

FIG. 3A shows an example of a voltage waveform of each node when the power supply of the circuit block 100 X according to the comparative example is turned on when first conditions (|Vtp|≈|Vtn| and Ipk≈Ink, e.g. |Vtp| is nearly equal to |Vtn| and Ipk is nearly equal to Ink) are satisfied. When the first conditions are satisfied, the potentials of an output node a 1 of the logic circuit 1 X 0 , of an output node a 2 of the logic circuit 1 X 1 , and of an output node OX of the logic circuit 1 X 2 are each undefined. In areas as well where the power supply voltage VDD is smaller than the MOSFET gate threshold value voltage Vth (i.e., where Vth≤VDD), the potentials of the nodes a 1 , a 2 , and OX are each undefined. Note that in the areas where Vth≤VDD, the effects of the MOSFET leakage currents are dominant. The state shown in FIG. 3A is a state in which Ipk and Ink are mutually balanced.

FIG. 3B shows an example of a voltage waveform of each node when the power supply of the circuit block 100 X according to the comparative example is turned on when second conditions (|Vtp|<|Vtn| and Ipk>Ink) are satisfied. When the second conditions are satisfied, operations are dependent on the PMOS. In this case, in the areas where Vth≤VDD, PMOS characteristics are evident while NMOS remains substantially inoperative. The potential of the output node OX of the logic circuit 1 X 2 is raised to a high level by the PMOS leakage current. Thereafter, if the level of the power supply voltage VDD increases, NMOS characteristics begin to appear (in other words, the NMOS begins to operate), and the potential of the output node OX is inverted to a low level. In other words, when the second conditions are satisfied, during the transition period after the power supply is turned on, the potential of the output node OX is inverted from a high level to a low level by the states of the logic circuits 1 X 0 and 1 X 1 .

FIG. 3C shows an example of a voltage waveform of each node when the power supply of the circuit block 100 X according to the comparative example is turned on when third conditions (|Vtp|>|Vtn| and Ipk<Ink) are satisfied. When the third conditions are satisfied, operations are dependent on the NMOS. In this case, in the areas where Vth≤VDD, NMOS characteristics are evident while PMOS remains substantially inoperative. The potential of the output node OX of the logic circuit 1 X 2 is dropped to a low level by the NMOS leakage current. Thereafter, if the level of the power supply voltage VDD increases, PMOS characteristics begin to appear (in other words, the PMOS begins to operate), and the potential of the output node OX is inverted to a high level. In other words, when the third conditions are satisfied, during the transition period after the power supply is turned on, the potential of the output node OX is inverted from a low level to a high level by the states of the logic circuits 1 X 0 and 1 X 1 .

In this way, according to the circuit block 100 X which includes the logic circuit 1 X 1 according to the comparative example, during the transition period after the power supply is turned on, the potential of the output node OX is either undefined or is inverted because of variations in the MOSFET characteristics. As a consequence, a signal having an unintended logic level is output, and there is a possibility of the system malfunctioning. A degree of improvement might be expected by adjusting the size ratio between the PMOS and the NMOS, however, because of the variations in the MOSFET characteristics, the above-described problems may not be completely solved.

FIG. 4A , FIG. 4B , and FIG. 4C show examples of structures of the logic circuit according to the comparative example that enable output node instabilities to be inhibited. The logic circuit 1 X 1 shown in FIG. 4A has a resistance element 13 provided between the input terminal 11 and the ground line. The logic circuit 1 X 1 shown in FIG. 4B has a resistance element 14 provided between the power supply line and the input terminal 11 . The logic circuit 1 X 1 shown in FIG. 4C has a DMOS (Double-Diffused MOSFET) 15 provided between the input terminal 11 and the ground line. According to the logic circuits 1 X 1 shown in FIG. 4A through FIG. 4C , while it is possible to inhibit instabilities in the potentials of the output nodes when the power supply is turned on, because current is being constantly supplied to the resistance elements 13 and 14 and to the DMOS 15 , the problem arises that power consumption increases.

Hereinafter, exemplary embodiments of the present disclosure will be described with reference to the drawings. Note that component elements or portions thereof that are essentially the same or equivalent in the respective drawings are given the same descriptive symbols.

First Exemplary Embodiment

FIG. 5 shows an example of the structure of a logic circuit 1 A 1 according to a first exemplary embodiment of the present disclosure. The logic circuit 1 A 1 can be formed on a single semiconductor chip. The logic circuit 1 A 1 is formed so as to include an inverter 10 that outputs from an output terminal 12 a signal created by inverting the logic of a signal input into the input terminal 11 . The inverter 10 has a P-channel type of MOSFET 10 P, and an N-channel type of MOSFET 10 N. A source of the MOSFET 10 P is connected to a power supply line, a gate thereof is connected to the input terminal 11 , and a drain thereof is connected to the output terminal 12 . A source of the MOSFET 10 N is connected to a ground line, a gate thereof is connected to the input terminal 11 , and a drain thereof is connected to the output terminal 12 .

Additionally, the logic circuit 1 A 1 has a P-channel type of MOSFET 20 P that is connected to the input terminal 11 in such a way as to maintain an OFF state, and an N-channel type of MOSFET 20 N that is connected to the output terminal 12 in such a way as to maintain an OFF state.

A source and a gate of the MOSFET 20 P are connected to the power supply line, while a drain thereof is connected to the input terminal 11 . The MOSFET 20 P maintains an OFF state as a result of the source and gate thereof being connected to the power supply line. A source and a gate of the MOSFET 20 N are connected to the ground line, while a drain thereof is connected to the output terminal 12 . The MOSFET 20 N maintains an OFF state as a result of the source and gate thereof being connected to the ground line.

FIG. 6 shows the structure of a circuit block 100 A that is formed so as to include the logic circuit 1 A 1 according to the present exemplary embodiment. The circuit block 100 A can be formed on a single semiconductor chip. The circuit block 100 A is formed so as to include the logic circuit 1 A 1 , a logic circuit 1 A 0 that is provided at the stage immediately preceding the logic circuit 1 A 1 , and a logic circuit 1 A 2 that is provided at the stage immediately following the logic circuit 1 A 1 . In other words, the circuit block 100 A is formed by cascode-connecting the logic circuits 1 A 0 , 1 A 1 , and 1 A 2 . The logic circuits 1 A 0 and 1 A 2 have the same structure as the logic circuit 1 X 1 according to the comparative example shown in FIG. 1 .

FIG. 7 shows an example of a voltage waveform of each node when the power supply of the circuit block 100 A is turned on. In areas where the power supply voltage VDD is smaller than the MOSFET gate threshold value voltage Vth (i.e., where Vth≤VDD), in other words, in areas where the circuit is not operating normally, the effects of the MOSFET leakage currents are dominant. In such areas, the potential of the input terminal 11 of the logic circuit 1 A 1 is fixed at a high level by the leakage current of the MOSFET 20 P which is connected to the input terminal 11 . Additionally, the potential of the output terminal 12 of the logic circuit 1 A 1 is fixed at a low level by the leakage current of the MOSFET 20 N which is connected to the output terminal 12 . As a result, the potential of the output node OX of the subsequent logic circuit 1 A 2 is fixed at a high level.

According to the circuit block 100 A which includes the logic circuit 1 A 1 according to the present exemplary embodiment, even if the above-described first conditions (|Vtp|≈|Vtn| and Ipk≈Ink, e.g. |Vtp| is nearly equal to |Vtn| and Ipk is nearly equal to Ink) are satisfied, the potential of the output node OX is not undefined, and even when the above-described second conditions (|Vtp|<|Vtn| and Ipk>Ink), or third conditions (|Vtp|>|Vtn| and Ipk<Ink) are satisfied, the potential of the output node OX is not inverted. In other words, it is possible to inhibit a signal having an unintended logic level from being output when the power supply is turned on. Accordingly, it is possible to suppress the risk of a system malfunction being generated when the power supply is turned on. Moreover, because the MOSFET 20 P and the MOSFET 20 N constantly maintain an OFF state, it is possible to inhibit an increase in the power consumption. Additionally, the MOSFET 20 P and 20 N do not affect circuit operations.

Second Exemplary Embodiment

FIG. 8 shows an example of the structure of the logic circuit 1 A 1 according to a second exemplary embodiment of the present disclosure. The logic circuit 1 A 1 is formed so as to include the inverter 10 that outputs from the output terminal 12 a signal created by inverting the logic of a signal input into the input terminal 11 . The inverter 10 has the P-channel type of MOSFET 10 P, and the N-channel type of MOSFET 10 N. The source of the MOSFET 10 P is connected to the power supply line, the gate thereof is connected to the input terminal 11 , and the drain thereof is connected to the output terminal 12 . The source of the MOSFET 10 N is connected to the ground line, the gate thereof is connected to the input terminal 11 , and the drain thereof is connected to the output terminal 12 .

Additionally, the logic circuit 1 A 1 has the P-channel type of MOSFET 20 P that is connected to the input terminal 11 in such a way as to maintain an OFF state, and a P-channel type of MOSFET 21 P that is connected to the output terminal 12 in such a way as to maintain an OFF state.

The source and the gate of the MOSFET 20 P are connected to the power supply line, while the drain thereof is connected to the input terminal 11 . The MOSFET 20 P maintains an OFF state as a result of the source and gate thereof being connected to the power supply line. The source of the MOSFET 21 P is connected to the output terminal 12 , the gate thereof is connected to the power supply line, and the drain thereof is connected to the ground line. The MOSFET 21 P maintains an OFF state as a result of the gate thereof being connected to the power supply line.

According to the circuit block 100 A which includes the logic circuit 1 A 1 according to the present exemplary embodiment (see FIG. 6 ), in the same way as in the circuit block 100 A according to the first exemplary embodiment, in the areas where Vth≤VDD, the potential of the input terminal 11 of the logic circuit 1 A 1 is fixed at a high level by the leakage current of the MOSFET 20 P which is connected to the input terminal 11 . Additionally, the potential of the output terminal 12 of the logic circuit 1 A 1 is fixed at a low level by the leakage current of the MOSFET 21 P which is connected to the output terminal 12 . As a result, the potential of the output node OX of the subsequent logic circuit 1 A 2 is fixed at a high level.

According to the circuit block 100 A which includes the logic circuit 1 A 1 according to the present exemplary embodiment, even if the above-described first conditions (|Vtp|≈|Vtn| and Ipk≈Ink, e.g. |Vtp| is nearly equal to |Vtn| and Ipk is nearly equal to Ink) are satisfied, the potential of the output node OX is not undefined, and even when the above-described second conditions (|Vtp|<|Vtn| and Ipk>Ink), or third conditions (|Vtp|>|Vtn| and Ipk<Ink) are satisfied, the potential of the output node OX is not inverted. In other words, it is possible to inhibit a signal having an unintended logic level from being output when the power supply is turned on. Accordingly, it is possible to suppress the risk of a system malfunction being generated when the power supply is turned on. Moreover, because the MOSFET 20 P and the MOSFET 21 P constantly maintain an OFF state, it is possible to inhibit an increase in the power consumption. Additionally, the MOSFET 20 P and 21 P do not affect circuit operations.

Third Exemplary Embodiment

FIG. 9 shows an example of the structure of the logic circuit 1 A 1 according to a third exemplary embodiment of the present disclosure. The logic circuit 1 A 1 is formed so as to include the inverter 10 that outputs from the output terminal 12 a signal created by inverting the logic of a signal input into the input terminal 11 . The inverter 10 has the P-channel type of MOSFET 10 P, and the N-channel type of MOSFET 10 N. The source of the MOSFET 10 P is connected to the power supply line, the gate thereof is connected to the input terminal 11 , and the drain thereof is connected to the output terminal 12 . The source of the MOSFET 10 N is connected to the ground line, the gate thereof is connected to the input terminal 11 , and the drain thereof is connected to the output terminal 12 .

Additionally, the logic circuit 1 A 1 has the P-channel type of MOSFET 20 P that is connected to the input terminal 11 in such a way as to maintain an OFF state, a P-channel type of MOSFET 22 P that is connected to the input terminal 11 and enables a latch operation of the inverter 10 to be achieved when the power supply is turned on, and the N-channel type of MOSFET 20 N that is connected to the output terminal 12 in such a way as to maintain an OFF state.

The source and the gate of the MOSFET 20 P are connected to the power supply line, while the drain thereof is connected to the input terminal 11 . The MOSFET 20 P maintains an OFF state as a result of the source and gate thereof being connected to the power supply line. The source of the MOSFET 22 P is connected to the power supply line, the gate thereof is connected to the output terminal 12 , and the drain thereof is connected to the input terminal 11 . The source and the gate of the MOSFET 20 N are connected to the ground line, while the drain thereof is connected to the output terminal 12 . The MOSFET 20 N maintains an OFF state as a result of the source and gate thereof being connected to the ground line.

FIG. 10 shows an example of a voltage waveform of each node when the power supply of the circuit block 100 A which includes the logic circuit 1 A 1 according to the present exemplary embodiment (see FIG. 6 ) is turned on. In areas where the power supply voltage VDD is smaller than the MOSFET gate threshold value voltage Vth (i.e., where Vth≤VDD), in other words, in areas where the circuit is not operating normally, the effects of the MOSFET leakage currents are dominant. In such areas, the potential of the input terminal 11 of the logic circuit 1 A 1 is fixed at a high level by the leakage current of the MOSFET 20 P which is connected to the input terminal 11 . Additionally, the potential of the output terminal 12 of the logic circuit 1 A 1 is fixed at a low level by the leakage current of the MOSFET 20 N which is connected to the output terminal 12 . Moreover, as a result of the potential of the output terminal 12 being fixed at a low level, the MOSFET 22 P which is connected to the input terminal 11 of the logic circuit 1 A 1 maintains an ON state. As a result, a latch operation to maintain a state in which the potential of the input terminal 11 is set at a high level, and the potential of the output terminal 12 is set at a low level is achieved. As a result, the potential of the output node OX of the subsequent logic circuit 1 A 2 is fixed at a high level.

According to the circuit block 100 A which includes the logic circuit 1 A 1 according to the present exemplary embodiment, even if the above-described first conditions (|Vtp|≈|Vtn| and Ipk≈Ink, e.g. |Vtp| is nearly equal to |Vtn| and Ipk is nearly equal to Ink) are satisfied, the potential of the output node OX is not undefined, and even when the above-described second conditions (|Vtp|<|Vtn| and Ipk>Ink), or third conditions (|Vtp|>|Vtn| and Ipk<Ink) are satisfied, the potential of the output node OX is not inverted. In other words, it is possible to inhibit a signal having an unintended logic level from being output when the power supply is turned on. Accordingly, it is possible to suppress the risk of a system malfunction being generated when the power supply is turned on. Moreover, the MOSFET 20 P and the MOSFET 20 N constantly maintain an OFF state, and the MOSFET 22 P is placed in an ON state transiently, however, there is no constant supply of current thereto. Accordingly, it is possible to inhibit an increase in the power consumption. Additionally, the MOSFET 20 P, 22 P, and 20 N do not affect circuit operations. Moreover, because a latch operation is achieved by the MOSFET 22 P, the stability of operations when the power supply is turned on can be further heightened.

Note that it is also possible for the MOSFET 22 P according to the present exemplary embodiment to be connected to the input terminal 11 of the logic circuit 1 A 1 according to the second exemplary embodiment (see FIG. 8 ).

Fourth Exemplary Embodiment

FIG. 11 shows an example of the structure of the logic circuit 1 A 1 according to a fourth exemplary embodiment of the present disclosure. The logic circuit 1 A 1 is formed so as to include the inverter 10 that outputs from the output terminal 12 a signal created by inverting the logic of a signal input into the input terminal 11 . The inverter 10 has the P-channel type of MOSFET 10 P, and the N-channel type of MOSFET 10 N. The source of the MOSFET 10 P is connected to the power supply line, the gate thereof is connected to the input terminal 11 , and the drain thereof is connected to the output terminal 12 . The source of the MOSFET 10 N is connected to the ground line, the gate thereof is connected to the input terminal 11 , and the drain thereof is connected to the output terminal 12 .

This logic circuit 1 A 1 additionally has an N-channel type of MOSFET 23 N that is connected to the input terminal 11 in such a way as to maintain an OFF state, and a P-channel type of MOSFET 23 P that is connected to the output terminal 12 in such a way as to maintain an OFF state.

A source and a gate of the MOSFET 23 N are connected to the ground line, while a drain thereof is connected to the input terminal 11 . The MOSFET 23 N maintains an OFF state as a result of the source and gate thereof being connected to the ground line. A source and a gate of the MOSFET 23 P are connected to the power supply line, while a drain thereof is connected to the output terminal 12 . The MOSFET 23 P maintains an OFF state as a result of the source and gate thereof being connected to the power supply line.

FIG. 12 shows an example of a voltage waveform of each node when the power supply of the circuit block 100 A which includes the logic circuit 1 A 1 according to the present exemplary embodiment (see FIG. 6 ) is turned on. In areas where the power supply voltage VDD is smaller than the MOSFET gate threshold value voltage Vth (i.e., where Vth≤VDD), in other words, in areas where the circuit is not operating normally, the effects of the MOSFET leakage currents are dominant. In such areas, the potential of the input terminal 11 of the logic circuit 1 A 1 is fixed at a low level by the leakage current of the MOSFET 23 N which is connected to the input terminal 11 . Additionally, the potential of the output terminal 12 of the logic circuit 1 A 1 is fixed at a high level by the leakage current of the MOSFET 23 P which is connected to the output terminal 12 . As a result, the potential of the output node OX of the subsequent logic circuit 1 A 2 is fixed at a low level.

According to the circuit block 100 A which includes the logic circuit 1 A 1 according to the present exemplary embodiment, even if the above-described first conditions (|Vtp|≈|Vtn| and Ipk≈Ink, e.g. |Vtp| is nearly equal to |Vtn| and Ipk is nearly equal to Ink) are satisfied, the potential of the output node OX is not undefined, and even when the above-described second conditions (|Vtp|<|Vtn| and Ipk>Ink), or third conditions (|Vtp|>|Vtn| and Ipk<Ink) are satisfied, the potential of the output node OX is not inverted. In other words, it is possible to inhibit a signal having an unintended logic level from being output when the power supply is turned on. Accordingly, it is possible to suppress the risk of a system malfunction being generated when the power supply is turned on. Moreover, because the MOSFET 23 P and the MOSFET 23 N constantly maintain an OFF state, it is possible to inhibit an increase in the power consumption. Additionally, the MOSFET 23 P and 23 N do not affect circuit operations.

Fifth Exemplary Embodiment

FIG. 13 shows an example of the structure of the logic circuit 1 A 1 according to a fifth exemplary embodiment of the present disclosure. The logic circuit 1 A 1 is formed so as to include the inverter 10 that outputs from the output terminal 12 a signal created by inverting the logic of a signal input into the input terminal 11 . The inverter 10 has the P-channel type of MOSFET 10 P, and the N-channel type of MOSFET 10 N. The source of the MOSFET 10 P is connected to the power supply line, the gate thereof is connected to the input terminal 11 , and the drain thereof is connected to the output terminal 12 . The source of the MOSFET 10 N is connected to the ground line, the gate thereof is connected to the input terminal 11 , and the drain thereof is connected to the output terminal 12 .

Additionally, the logic circuit 1 A 1 has the N-channel type of MOSFET 23 N that is connected to the input terminal 11 in such a way as to maintain an OFF state, an N-channel type of MOSFET 24 N that is connected to the input terminal 11 and enables a latch operation of the inverter 10 to be achieved when the power supply is turned on, and the P-channel type of MOSFET 23 P that is connected to the output terminal 12 in such a way as to maintain an OFF state.

FIG. 14 shows an example of a voltage waveform of each node when the power supply of the circuit block 100 A is turned on. In areas where the power supply voltage VDD is smaller than the MOSFET gate threshold value voltage Vth (i.e., where Vth≤VDD), in other words, in areas where the circuit is not operating normally, the effects of the MOSFET leakage currents are dominant. In such areas, the potential of the input terminal 11 of the logic circuit 1 A 1 is fixed at a low level by the leakage current of the MOSFET 23 N which is connected to the input terminal 11 . Additionally, the potential of the output terminal 12 of the logic circuit 1 A 1 is fixed at a high level by the leakage current of the MOSFET 23 P which is connected to the output terminal 12 . Moreover, as a result of the potential of the output terminal 12 being fixed at a high level, the MOSFET 24 N which is connected to the input terminal 11 of the logic circuit 1 A 1 maintains an ON state. As a result, a latch operation to maintain a state in which the potential of the input terminal 11 is set at a low level, and the potential of the output terminal 12 is set at a high level is achieved. As a result, the potential of the output node OX of the subsequent logic circuit 1 A 2 is fixed at a low level.

According to the circuit block 100 A which includes the logic circuit 1 A 1 according to the present exemplary embodiment, even if the above-described first conditions (|Vtp|≈|Vtn| and Ipk≈Ink, e.g. |Vtp| is nearly equal to |Vtn| and Ipk is nearly equal to Ink) are satisfied, the potential of the output node OX is not undefined, and even when the above-described second conditions (|Vtp|<|Vtn| and Ipk>Ink), or third conditions (|Vtp|>|Vtn| and Ipk<Ink) are satisfied, the potential of the output node OX is not inverted. In other words, it is possible to inhibit a signal having an unintended logic level from being output when the power supply is turned on. Accordingly, it is possible to suppress the risk of a system malfunction being generated when the power supply is turned on. Moreover, the MOSFET 23 P and the MOSFET 23 N constantly maintain an OFF state, and the MOSFET 24 N is placed in an ON state transiently, however, there is no constant supply of current thereto. Accordingly, it is possible to inhibit an increase in the power consumption. Additionally, the MOSFET 23 N, 24 N, and 23 P do not affect circuit operations. Moreover, because a latch operation is achieved by the MOSFET 24 N, the stability of operations when the power supply is turned on can be further heightened.

Exemplary embodiments of the present disclosure have been described above, however, the present disclosure is not limited to these. Various modifications and the like may be made to the present disclosure insofar as they do not depart from the spirit or scope of the present disclosure.