Display device and a method of driving a gate driver

This application is a continuation of U.S. patent application Ser. No. 16/043,739, filed on Jul. 24, 2018, which claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2017-0137691, filed on Oct. 23, 2017 and Korean Patent Application No. 10-2018-0078831, filed on Jul. 6, 2018, the disclosures of which are incorporated by reference herein in their entireties.

The present inventive concept relates to a method of driving a gate driver from an overcurrent and a display device having the gate driver.

A display device includes a display panel for displaying an image and a driving circuit for driving the display panel. The display panel includes gate lines, data lines, and pixels. The driving circuit generates various driving voltages to operate the display panel. To display an image via the pixels, the driving voltages at a high voltage level are applied to the gate lines and the data lines.

When there is a short circuit between wirings through which the driving voltages are provided, an overcurrent may flow to the wirings. In this case, the display panel can malfunction. In addition, the wirings are at risk of being burnt.

Exemplary embodiments of the inventive concept provide a display device including a display panel including a plurality of data lines, a plurality of gate lines, and a plurality of pixels, wherein the display panel is operated in an active period in which a data driving signal is applied to the pixels through the data lines or in a blank period in which the data driving signal is not applied to the pixels and a driving circuit for driving the display panel. The driving circuit includes a signal controller for outputting a plurality of clock control signals, a voltage generator for receiving the clock control signals, wherein the voltage generator outputs a plurality of active clock signals synchronized with the clock control signals during the active period and outputs a plurality of blank clock signals during the blank period, and an overcurrent detection circuit for receiving the clock control signals and the blank clock signals, wherein the overcurrent detection circuit detects an overcurrent of the blank clock signals. A phase difference between the clock control signals in the active period is different from a phase difference between the clock control signals in the blank period.

When a rising time point of a first clock control signal is a first rising time point and a rising time point of a second clock control signal that rises at a time point nearest to and after the first rising time point is a second rising time point, a first time difference between the first rising time point and the second rising time point in the active period is smaller than a second time difference between the first rising time point and the second rising time point in the blank period.

After the blank period is entered, the second clock control signal first rises after a first delay time and a third clock control signal subsequent to the second clock control signal first rises after a second delay time.

Each of the first and second clock control signals has a low level for a time equal to or greater than the first time difference of the blank period before the active period begins.

A duty ratio of a high level of each the first and second clock control signals in the active period is smaller than a duty ratio of a high level of each of the first and second clock control signals in the blank period.

The overcurrent detection circuit detects the overcurrent during a time between the first rising time point and a falling time point of the second clock control signal that falls at a time point nearest to and after the first rising time point.

The overcurrent detection circuit counts a signal at a detection time after a first time elapses from the first rising time point, wherein the counted signal indicates that a current level of a first clock signal is higher than an overcurrent reference current level.

The detection time is a detection period, and the detection period is a period between the first rising time point and the falling time point in the blank period.

The blank clock signals include a first blank clock signal and a second blank clock signal, and the first blank clock signal has a voltage level different from a voltage level of the second blank clock signal.

The blank period includes a masking period and an overcurrent detection period, the blank clock signals have a low level during the masking period, and the first blank clock signal has a high level and the second blank clock signal has a low level in the overcurrent detection period.

The first blank clock signal in a first frame and the second blank clock signal in a second frame have a same level as each other, and the second blank clock signal in the first frame and the first blank clock signal in the second frame have a same level as each other.

The overcurrent detection circuit counts a number of overcurrent detections and activates an overcurrent detection signal when the number of overcurrent detections is equal to or greater than a reference number, and the voltage generator stops generating the driving voltage in response to the overcurrent detection signal.

Exemplary embodiments of the inventive concept provide a display device including a display panel including a plurality of data lines, a plurality of gate lines, and a plurality of pixels, wherein the display panel is operated in an active period in which a data driving signal is applied to the pixels through the data lines or in a blank period in which the data driving signal is not applied to the pixels and a driving circuit for driving the display panel. The driving circuit includes a signal controller for outputting a plurality of clock control signals, a voltage generator for receiving the clock control signals, wherein the voltage generator outputs a plurality of active clock signals synchronized with the clock control signals during the active period and outputs a plurality of blank clock signals during the blank period, and an overcurrent detection circuit for receiving the clock control signals and the blank clock signals, wherein the overcurrent detection circuit detects an overcurrent of the blank clock signals. A time difference between a rising time point of a first clock control signal and a falling time point of a second clock control signal that falls at a time point nearest to and after the rising time point is greater in the blank period than in the active period.

A frequency of each of the first and second clock control signals in the blank period is lower than a frequency of each of the first and second clock control signals in the active period.

A phase difference between each of the first and second clock control signals in the active period is different from a phase difference between each of the first and second clock control signals in the blank period.

Exemplary embodiments of the inventive concept provide a method of driving a gate driver of a display panel, which includes a plurality of data lines, a plurality of gate lines, and a plurality of pixels, wherein the display panel is operated in an active period in which a data driving signal is applied to the pixels through the data lines or in a blank period in which the data driving signal is not applied to the pixels, the method including receiving a plurality of clock control signals having phase differences different from each other in the active period and the blank period, generating a plurality of active clock signals synchronized with the clock control signals in the active period, generating a plurality of blank clock signals in the blank period, detecting an overcurrent of the blank clock signals in response to the clock control signals and the blank clock signals, and activating an overcurrent detection signal when a number of overcurrent detections exceeds a reference number.

After the blank period is entered, each of first, second and third clock control signals has a first rise time, and the first rise time of each of the second and third clock control signals is delayed.

A first duty ratio of a high level of the clock control signals in the active period is smaller than a second duty ratio of a high level of the clock control signals in the blank period.

The blank clock signals are generated in synchronization with the clock control signals in the blank period.

The generating of the blank clock signals includes generating a first blank clock signal having a first voltage level and generating a second blank clock signal having a second voltage level different from the first voltage level.

Exemplary embodiments of the inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings in which:

FIG. 1 is a block diagram showing a display device according to an exemplary embodiment of the present inventive concept;

FIG. 2 is a block diagram showing a voltage generator according to an exemplary embodiment of the present inventive concept;

FIG. 3 is a block diagram showing an overcurrent detection circuit according to an exemplary embodiment of the present inventive concept;

FIG. 4 is a timing diagram showing some signals output from a signal controller according to an exemplary embodiment of the present inventive concept;

FIG. 5 is a timing diagram showing clock control signals, clock signals, and a current level of a clock signal according to an exemplary embodiment of the present inventive concept;

FIG. 6 is a timing diagram explaining a method of detecting an overcurrent according to an exemplary embodiment of the present inventive concept;

FIG. 7 is a timing diagram showing clock control signals and a current level of a clock signal according to an exemplary embodiment of the present inventive concept;

FIG. 8 is a timing diagram showing clock control signals and a current level of a clock signal according to an exemplary embodiment of the present inventive concept;

FIG. 9 is a timing diagram showing clock signals output during a blank period according to an exemplary embodiment of the present inventive concept; and

FIG. 10 is a timing diagram showing clock signals output during a blank period according to an exemplary embodiment of the present inventive concept.

Hereinafter, exemplary embodiments of the present inventive concept will be explained in detail with reference to the accompanying drawings. The inventive concept may, however, be embodied in different forms and should not be construed as being limited to the embodiments set forth herein. Like numerals may refer to like elements throughout the specification.

FIG. 1 is a block diagram showing a display device DD according to an exemplary embodiment of the present inventive concept.

Referring to FIG. 1 , the display device DD includes a display panel 100 and a driving circuit 200 . The driving circuit 200 includes a signal controller 210 , a voltage generation circuit 220 , a gate driver 230 , and a data driver 240 . The signal controller 210 , the voltage generation circuit 220 , the gate driver 230 , and the data driver 240 may be used to drive the display panel 100 .

The display panel 100 may be one of various display panels, such as an organic light emitting display panel, a liquid crystal display panel, a plasma display panel, an electrophoretic display panel, an electrowetting display panel, etc.

The display panel 100 includes a plurality of data lines DL 1 to DLm, a plurality of gate lines GL 1 to GLn, and a plurality of pixels PX.

The gate lines GL 1 to GLn extend in a first direction DR 1 and are arranged in a second direction DR 2 crossing the first direction DR 1 . For example, the gate lines GL 1 to GLn extend lengthwise in the first direction DR 1 . The data lines DL 1 to DLm extend in the second direction DR 2 and are arranged in the first direction DR 1 . For example, the data lines DL 1 to DLrm extend lengthwise in the second direction DR 2 . The data lines DL 1 to DLm and the gate lines GL 1 to GLn may define pixel areas, and the pixels PX are disposed in the pixel areas, respectively. FIG. 1 shows a pixel PX connected to a first data line DL 1 and a first gate line GL 1 as a representative example.

The pixel PX may display one of the primary colors or a mixture of the primary colors. The primary colors may include a red color, a green color, and a blue color, and the mixture of the primary colors may include various colors, e.g., a white color, a yellow color, a cyan color, a magenta color, etc. However, the colors displayed by the pixels PX are not limited thereto.

The signal controller 210 (or a timing controller) receives a control signal CS and image data RGB from an external source. The signal controller 210 applies a first control signal CONT 1 to the data driver 240 and applies a second control signal CONT 2 to the gate driver 230 . The first control signal CONT 1 is used to drive the data driver 240 , and the second control signal CONT 2 is used to drive the gate driver 230 .

The data driver 240 drives the data lines DL 1 to DLm in response to the first control signal CONT 1 provided from the signal controller 210 . The data driver 240 may be electrically connected to one side portion of the display panel 100 . The data driver 240 may be an independent integrated circuit or directly mounted on the display panel 100 . In addition, the data driver 240 may be a single chip or may include a plurality of chips.

The gate driver 230 drives the gate lines GL 1 to GLn in response to the second control signal CONT 2 provided from the signal controller 210 . The gate driver 230 may be integrated in a predetermined area of the display panel 100 . In this case, the gate driver 230 may be implemented in a circuit using an amorphous silicon gate of an amorphous silicon thin film transistor, an oxide semiconductor, a crystalline semiconductor, a polycrystalline semiconductor, and the like. In addition, the gate driver 230 may be electrically connected to one side portion of the display panel 100 . In this case, the gate driver 230 may be an independent integrated circuit. According to an exemplary embodiment of the inventive concept, the gate driver 230 may be implemented in a tape carrier package (TCP) or a chip-on-film (COF).

A switching transistor of each of the pixels PX arranged in one row and connected to one gate line among the gate lines GL 1 to GLn is turned on during a time period in which a gate-on voltage is applied to the one gate line. In this case, the data driver 240 applies data driving signals corresponding to image data signals included in the first control signal CONT 1 to the data lines DL 1 to DLm. The data driving signals applied to the data lines DL 1 to DLm are respectively applied to the pixels PX through the turned-on switching transistors.

The display panel 100 may be operated in an active period during which the display panel 100 receives the data driving signals or in a blank period during which the display panel 100 does not receive the data driving signals. For example, the active period may correspond to a period in which the data driving signals applied to the data lines DL 1 to DLm are applied to the pixels PX through the turned-on switching transistors. In addition, the blank period does not influence a display quality of the display panel 100 . This is so, because the data driving signals are not applied to the data lines DL 1 to DLm during the blank period.

The voltage generation circuit 220 receives a power voltage VIN from an external source and receives a clock control signal CPV, a vertical start signal STV, and a blank signal BLK from the signal controller 210 . The vertical start signal STV indicates a start of one frame, and the blank signal BLK is maintained in an active state (e.g., a low level) during the blank period in which the data driver 240 does not drive the data lines DL 1 to DLm within one frame.

The voltage generation circuit 220 may generate the driving voltages in response to the clock control signal CPV, the vertical start signal STV, and the blank signal BLK. As an example, the driving voltages may include an analog power voltage, a gamma voltage, the gate-on voltage, a gate-off voltage, a ground voltage, a common voltage, and the like. However, the driving voltages are not limited thereto. In addition, the voltage generation circuit 220 may further include terminals to output the driving voltages.

The voltage generation circuit 220 may generate clock signals CKV based on the generated driving voltages. An individual clock signal CKV may have a waveform with a gate-on voltage level and a gate-off voltage level.

FIG. 2 is a block diagram showing the voltage generation circuit 220 according to an exemplary embodiment of the present inventive concept, and FIG. 3 is a block diagram showing an overcurrent detection circuit according to an exemplary embodiment of the present inventive concept.

Referring to FIGS. 2 and 3 , the voltage generation circuit 220 includes a voltage generator 221 and an overcurrent detection circuit 222 .

The voltage generator 221 receives the power voltage VIN and the clock control signal CPV and converts the clock control signal CPV to the clock signal CKV to output the clock signal CKV. The overcurrent detection circuit 222 detects an output current of the clock signal CKV flowing through a voltage terminal OP and outputs an overcurrent detection signal OVER_C.

The overcurrent detection circuit 222 includes a current sensor 222 a , an overcurrent detector 222 b , an overcurrent counter 222 c , and an overcurrent determination circuit 222 d.

The current sensor 222 a senses an output current of the clock signal CKV output through the voltage terminal OP.

The overcurrent detector 222 b determines whether a current level of the clock signal CKV is higher than an overcurrent reference current level. The overcurrent detector 222 b may be operated in both of the active period and the blank period, or only in the blank period, for example.

The overcurrent counter 222 c counts a signal, which indicates that the current level of the clock signal CKV is higher than the overcurrent reference current level, output from the overcurrent detector 222 b . The overcurrent counter 222 c is initialized every predetermined period.

When the number of overcurrents counted by the overcurrent counter 222 c exceeds the number of reference counts, the overcurrent determination circuit 222 d determines that the output current of the clock signal CKV is in an overcurrent state and activates the overcurrent detection signal OVER_C.

The voltage generator 221 receives the overcurrent detection signal OVER_C from the overcurrent determination circuit 222 d . When the overcurrent detection signal OVER_C is activated (e.g., the overcurrent detection signal OVER_C is at the high level), the voltage generator 221 may stop generating inner driving voltages. In other words, the voltage generator 221 stops generating the driving voltages to be output to the voltage terminal OP, and thus, the display panel 100 shown in FIG. 1 may be prevented from malfunctioning. In addition, the display panel 100 may be prevented from becoming defective due to a high temperature and may also reduce a risk of fire.

FIG. 4 is a timing diagram showing some signals output from the signal controller 210 according to an exemplary embodiment of the present inventive concept. FIG. 4 shows the vertical start signal STV, the blank signal BLK, and the clock control signal CPV.

The clock control signal CPV may be provided in a plural number. For example, the clock control signal CPV may include first, second, third, and fourth clock control signals CPV 1 , CPV 2 , CPV 3 , and CPV 4 having different phases from each other. However, the inventive concept is not limited thereto. For instance, the clock control signal CPV may include three or sixth clock control signals having different phases from each other.

A difference in phase between the first, second, third, and fourth clock control signals CPV 1 , CPV 2 , CPV 3 , and CPV 4 in the active period AP may be different from a difference in phase between the first, second, third, and fourth clock control signals CPV 1 , CPV 2 , CPV 3 , and CPV 4 in the blank period BP.

According to the exemplary embodiment of the present inventive concept, a reliability of the overcurrent detection performed by the overcurrent detection circuit 222 may be increased by controlling the phase difference between the first, second, third, and fourth clock control signals CPV 1 , CPV 2 , CPV 3 , and CPV 4 in the blank period BP.

Among the first, second, third, and fourth clock control signals CPV 1 , CPV 2 , CPV 3 , and CPV 4 , a rising time point of a k-th clock signal may be referred to as a “first rising time point”, and a rising time point of a (k+1)th clock signal rising at a time point nearest the first time rising time point may be referred to as a “second rising time point”. “k” may be an integer equal to or greater than 1. In the present exemplary embodiment, when “k” is 4, the (k+1)th clock control signal may be the first clock control signal CPV 1 , and when “k” is 5, the (k+1)th clock control signal may be the second clock control signal CPV 2 .

Hereinafter, a case in which “k” is 1 will be described as a representative example. In FIG. 4 , a first rising time point RP 1 of the first clock control signal CPV 1 and a second rising time point RP 2 of the second clock control signal CPV 2 in the active period AP are shown. In addition, a first rising time point BRP 1 of the first clock control signal CPV 1 and a second rising time point BRP 2 of the second clock control signal CPV 2 in the blank period BP are shown in FIG. 4 .

A difference in time between the first rising time point RP 1 and the second rising time point RP 2 may be referred to as a “first time difference TL 1 ”, and a difference in time between the first rising time point BRP 1 and the second rising time point BRP 2 may be referred to as a “second time difference TL 2 ”. Here, the first time difference TL 1 is different from the second time difference TL 2 , and the second time difference TL 2 is greater than the first time difference TL 1 . As an example, the second time difference TL 2 may be two times greater than the first time difference TL 1 . In other words, the phase difference between the first, second, third, and fourth clock control signals CPV 1 , CPV 2 , CPV 3 , and CPV 4 in the blank period BP may be greater than the phase difference between the first, second, third, and fourth clock control signals CPV 1 , CPV 2 , CPV 3 , and CPV 4 in the active period AP.

After a time point at which the blank period BP is entered, a first rising time point of each of the clock control signals except for a clock control signal that first rises among the first, second, third, and fourth clock control signals CPV 1 , CPV 2 , CPV 3 , and CPV 4 may be delayed. The clock control signal that first rises in the blank period BP of FIG. 4 is the first clock control signal CPV 1 . Accordingly, the first rising time point of the second, third, and fourth clock control signals CPV 2 , CPV 3 , and CPV 4 may be delayed.

The first rising time point of the second clock control signal CPV 2 may be delayed by a first time TD 1 , the first rising time point of the third clock control signal CPV 3 may be delayed by a second time TD 2 , and the first rising time point of the fourth clock control signal CPV 4 may be delayed by a third time TD 3 .

When the second time difference TL 2 is two times greater than the first time difference TL 1 , the first time TD 1 may be the same as the first time difference TL 1 , the second time TD 2 may be two times greater than the first time difference TL 1 , and the third time TD 3 may be three times greater than the first time difference TL 1 . In other words, the delay times TD 1 , TD 2 and TD 3 may sequentially increase.

After the first rising time point of the second, third, and fourth clock control signals CPV 2 , CPV 3 , and CPV 4 is delayed, a waveform and a duty ratio of each of the first, second, third, and fourth clock control signals CPV 1 , CPV 2 , CPV 3 , and CPV 4 are constant in the active period AP and the blank period BP.

Although the first rising time point of each of the second, third, and fourth clock control signals CPV 2 , CPV 3 , and CPV 4 are delayed in the blank period BP, these delays do not impact image quality since the blank period BP is not a period in which signals for the image are received.

The clock control signal CPV may maintain a low level during a predetermined period LT of the blank period BP before the active period AP begins. Accordingly, the clock signals CKV (refer to FIG. 1 ) may be prevented from being repeatedly output at the beginning of the active period AP. The predetermined period LT may have a length equal to or greater than the first time difference TL 1 .

FIG. 5 is a timing diagram showing the clock control signals, the clock signals, and a current level of the clock signal according to an exemplary embodiment of the present inventive concept.

FIG. 5 shows the first clock control signal CPV 1 , the second clock control signal CPV 2 , and the clock signal CKV. The first clock control signal CPV 1 and the second clock control signal CPV 2 are the same as the first clock control signal CPV 1 and the second clock control signal CPV 2 shown in FIG. 4 . However, the first clock control signal CPV 1 and the second clock control signal CPV 2 shown in FIG. 5 have different duty ratios from those of the first clock control signal CPV 1 and the second clock control signal CPV 2 shown in FIG. 4 .

In FIG. 5 , only first and second clock signals CKV 1 and CKV 2 are shown, but the clock signal CKV may include more than two clock signals. In addition, the clock signal CKV may further include a first clock bar signal and a second clock bar signal having a phase opposite to that of the first clock signal CKV 1 and the second clock signal CKV 2 .

When the first clock control signal CPV 1 has a falling edge, the voltage level of the first clock signal CKV 1 rises, and when the first clock control signal CPV 1 has a rising edge, the voltage level of the first clock signal CKV 1 rises again. When the first clock control signal CPV 1 has the falling edge after being maintained at a certain voltage level, the voltage level of the first clock signal CKV 1 falls, and when the first clock control signal CPV 1 has the rising edge after having the falling edge after being maintained, the voltage level of the first clock signal CKV 1 falls again. When the first clock signal CKV 1 initially rises or falls, it may rise or fall to a charge share voltage having an intermediate level. This way, the voltage level of the first clock signal CKV 1 may be stepwise changed. The second clock signal CKV 2 operates in the same manner as the first clock signal CKV 1 , and thus, detailed descriptions of the second clock signal CKV 2 will be omitted.

The first clock signal CKV 1 is divided into a first active clock signal CKVA 1 output during the active period AP and a first blank clock signal CKVB 1 output during the blank period BP. The second clock signal CKV 2 is divided into a second active clock signal CKVA 2 output during the active period AP and a second blank clock signal CKVB 2 output during the blank period BP.

In the exemplary embodiment shown in FIG. 5 , the first active clock signal CKVA 1 and the first blank clock signal CKVB 1 are generated in synchronization with the first clock control signal CPV 1 , and the second active clock signal CKVA 2 and the second blank clock signal CKVB 2 are generated in synchronization with the second clock control signal CPV 2 .

FIG. 5 shows an output current of the first clock signal CKV 1 . The current represented by a solid line indicates a normal output current CKVN_C. and the current represented by a dotted line indicates an abnormal output current CKVE_C.

Regarding the normal output current CKVN_C, the current flows depending on the change of the voltage when the first clock signal CKV 1 first rises, second rises, first falls, and second falls. In addition, when the voltage level of the first clock signal CKV 1 starts to be maintained, the normal output current CKVN_C converges to zero (0).

However, when a short circuit occurs between the voltage terminal to which the first clock signal CKV 1 is applied and the voltage terminal to which the second clock signal CKV 2 is applied, the abnormal output current E_C may not converge to zero (0) even though the voltage level of the first clock signal CKV 1 is maintained. In the above description, the expression that “a short circuit occurs between the voltage terminals” may mean that the short circuit occurs between the voltage terminals, and also that the short circuit occurs between components, e.g., driving lines, connected to terminals.

The abnormal output current CKVE_C may be a current generated when a current flows between a terminal to which the first clock signal CKV 1 is applied and a terminal to which the second clock signal CKV 2 is applied. However, the abnormal output current CKVE_C is not limited thereto.

When the voltage level of the first clock signal CKV 1 starts to be maintained, the normal output current CKVN_C is supposed to converge to zero (0). However, since a difference in voltage level exists between the terminal to which the first clock signal CKV 1 is applied and the terminal to which the second clock signal CKV 2 is applied, the abnormal output current CKVE_C is maintained at a predetermined level without converging to zero (0).

When the second clock signal CKV 2 first rises, the difference in voltage level between the first clock signal CKV 1 and the second clock signal CKV 2 is reduced by half, and thus, a current value of the abnormal output current CKVE_C is reduced. When the second clock signal CKV 2 rises for the second time and the voltage level of the first clock signal CKV 1 becomes equal to the voltage level of the second clock signal CKV 2 , the abnormal output current CKVE_C becomes zero (0).

Since the current value of the abnormal output current CKVE_C is reduced when the second clock signal CKV 2 first rises, the detection of the overcurrent may be carried out during periods DT 1 and DT 2 . Period DT 1 occurs between the first rising time point RP 1 of the first clock control signal CPV 1 and the falling point FP of the second clock control signal CPV 2 . The falling point FP of the second clock control signal CPV 2 corresponds to the first level drop of the second clock control signal CPV 2 after the first rising time point RP 1 . For example, in FIG. 5 , the falling point FP occurs when CPV 2 goes low and DT 1 ends. Period DT 2 occurs between yet another first rising time point RP 1 of the first clock control signal CPV 1 and yet another falling point FP of the second clock control signal CPV 2 . The rising time point RP 1 and falling point FP of period DT 2 are shown to the right of FIG. 5 .

The overcurrent detection circuit 222 (refer to FIG. 2 ) determines whether the voltage level of the clock signal CKV is higher than the overcurrent reference current level OCP_L at a detection time point after a first time elapses from the rising time point of the clock control signal CPV (refer to FIG. 2 ) by a first time. The detection time point may have a predetermined distribution.

For instance, the first time may be about 4.5 μs and the distribution may be about 20%, but they are not limited thereto. Although the first time set as the detection time point is about 4.5 μs, the overcurrent detection circuit 222 (refer to FIG. 2 ) may determine whether the overcurrent occurs at a time point within a detection period DPN between about 3.6 μs to about 5.4 μs due, for example, to the distribution.

When a detectable period DT 1 in the active period AP is about 4.2 μs from the rising time point of the clock control signal CPV (refer to FIG. 2 ), the normal output current CKVN_C and the abnormal output current CKVE_C are lower than the overcurrent reference current level OCP_L within a range from about 4.2 μs to about 5.4 μs. Accordingly, it may not be determined whether the overcurrent occurs. In addition, when the overcurrent reference current level OCP_L is lowered to detect the overcurrent, the normal output current CKVN_C may be determined as the overcurrent. For example, when a voltage level of the gate-on voltage increases to compensate for degradation of driving ability of inner driving elements at a low temperature, the normal output current CKVN_C may be erroneously determined as an overcurrent.

According to an exemplary embodiment of the present inventive concept, the phase difference between the first and second clock control signals CPV 1 and CPV 2 in the blank period BP is greater than the phase difference between the first and second clock control signals CPV 1 and CPV 2 in the active period AP. Accordingly, a time point at which a difference in voltage level between the first blank clock signal CKVB 1 and the second blank clock signal CKVB 2 is reduced by half may be later than a time point at which a difference in voltage level between the first active clock signal CKVA 1 and the second active clock signal CKVA 2 is reduced by half. In other words, the detectable period DT 2 in the blank period BP may be longer than the detectable period DT 1 in the active period AP. For example, the detectable period DT 2 in the blank period BP may be two times longer than the detectable period DT 1 in the active period AP. In other words, the detectable period DT 2 may be equal to or greater than about 8.4 Its. Accordingly, the detection period DPN between about 3.6 μs and about 5.4 μs may completely overlap with the detectable period DT 2 . In other words, the detection period DPN may be included in the detectable period DT 2 . Accordingly, the reliability of the overcurrent detection may be increased.

FIG. 6 is a timing diagram explaining a method of detecting the overcurrent according to an exemplary embodiment of the present inventive concept.

FIG. 6 shows the first clock signal CKV 1 and the output current CKV_C with respect to the first clock signal CKV 1 .

Referring to FIGS. 3 and 6 , the current sensor 222 a senses the output current CKV_C. The overcurrent detector 222 b determines whether the voltage level of the output current CKV_C is higher than the overcurrent reference current level OCP_L.

The overcurrent counter 222 c counts the signal, which indicates that the level of the output current CKV_C is higher than the overcurrent reference current level OCP_L, output from the overcurrent detector 222 b . The overcurrent counter 222 c is initialized every predetermined period. As an example, the overcurrent counter 222 c counts the overcurrent during thirty two (32) rising edges of the first clock signal CKV 1 , initializes the counted number, and counts again the overcurrent during another thirty two (32) rising edges of the first clock signal CKV 1 . The counting of the overcurrent for thirty two (32) rising edges is merely an example, and thus, the period for such counting may be shorter or longer than thirty two (32) rising edges of the first clock signal CKV 1 . In addition, the overcurrent counter 222 c may be initialized each time a frame is finished. The initialization time point of the overcurrent counter 222 c may be variously changed.

The overcurrent determination circuit 222 d determines that the current of the clock signal is in the overcurrent state when the number of overcurrents counted by the overcurrent counter 222 c exceeds the number of reference counts. FIG. 6 shows the number of times OC 1 , OC 2 , OC 3 , and OCX, in which the overcurrent is detected in thirty two (32) rising edges of the first clock signal CKV 1 . As an example, when the number of reference counts is eight (8), the overcurrent determination circuit 222 d determines that the current of the clock signal is in the overcurrent state when “X” of “OCX” exceeds eight (8). In addition, the overcurrent determination circuit 222 d determines that the current of the clock signal is in the normal state when “X” of “OCX” is equal to or smaller than eighth (8). However, the number of reference counts is not limited to eight (8).

FIG. 7 is a timing diagram showing clock control signals and a current level of a clock signal according to an exemplary embodiment of the present inventive concept.

FIG. 7 shows a first clock control signal CPV 1 a , a second clock control signal CPV 2 a , and a current CKVC_a of a first clock signal. Hereinafter, different features of the first clock control signal CPV 1 a and the second clock control signal CPV 2 b from those of the first clock control signal CPV 1 (refer to FIG. 5 ) and the second clock control signal CPV 2 (refer to FIG. 5 ) will be mainly described.

A duty ratio of each of the first clock control signal CPV 1 a and the second clock control signal CPV 2 a in the active period AP is different from a duty ratio of each of the first clock control signal CPV 1 a and the second clock control signal CPV 2 a in the blank period BP. The first clock control signal CPV 1 a will be described as a representative example.

In the active period AP, a period of the first clock control signal CPV 1 a is “x1”, and a length of a period in which the first clock control signal CPV a has a high level is “y1”. Accordingly, a first duty ratio of the high level of the first clock control signal CPV 1 a in the active period AP is “y1/x1”. In the blank period BP, the period of the first clock control signal CPV 1 a is “x2”, and the length of the period in which the first clock control signal CPV 1 a has the high level is “y2”. Accordingly, a second duty ratio of the high level of the first clock control signal CPV 1 a in the blank period BP is “y2/x2”. “x1” may be the same as the “x2”, and “y2” may be longer than the “y1”. Accordingly, the second duty ratio may be greater than the first duty ratio.

After a time point of entry into the blank period BP, a falling time point of each of the first clock control signal CPV 1 a and the second clock control signal CPV 2 a may be delayed. Accordingly, a high level period of each of the first clock control signal CPV a and the second clock control signal CPV 2 a may increase and, as a result, a detectable period DT 2 a in the blank period BP may be longer than a detectable period DT 1 a in the active period AP. The detectable period DT 2 a may be controlled to completely overlap with the detection period DPN. In other words, the entire detection period DPN may occur in the detectable period DT 2 a.

FIG. 8 is a timing diagram showing clock control signals and a current level of a clock signal according to an exemplary embodiment of the present inventive concept.

FIG. 8 shows a first clock control signal CPV 1 b , a second clock control signal CPV 2 b , and a current CKVC_b of a first clock signal. Hereinafter, different features of the first clock control signal CPV 1 b and the second clock control signal CPV 2 b from those of the first clock control signal CPV 1 (refer to FIG. 5 ) and the second clock control signal CPV 2 (refer to FIG. 5 ) will be mainly described.

A frequency of each of the first clock control signal CPV 1 b and the second clock control signal CPV 2 b in the active period AP is different from a frequency of each of the first clock control signal CPV 1 b and the second clock control signal CPV 2 b in the blank period BP.

After a time point of entry into the blank period BP, a frequency of each of the first clock control signal CPV 1 b and the second clock control signal CPV 2 b may be changed. For example, the frequency of each of the first clock control signal CPV 1 b and the second clock control signal CPV 2 b may be lowered. As a result, a detectable period DT 2 b in the blank period BP may be longer than a detectable period DT 1 a in the active period AP. The detectable period DT 2 b may be controlled to completely overlap with the detection period DPN. In other words, the entire detection period DPN may occur within the detectable period DT 2 b.

FIG. 9 is a timing diagram showing clock signals output during the blank period according to an exemplary embodiment of the present inventive concept.

In FIG. 5 , the first and second blank clock signals CKVB 1 and CKVB 2 are output in synchronization with the first and second clock control signals CPV 1 and CPV 2 in the blank period BP. When compared with FIG. 5 , in FIG. 9 , each of the blank clock signals CKVB may be output in the blank period BP independently of the clock control signals.

FIG. 9 shows a blank signal BLK and a plurality of blank clock signals CKVB. The blank signal BLK may be activated during the blank period BP. In FIG. 9 , the blank signal BLK is activated when the blank signal BLK has a low level.

The blank clock signals CKVB may include a first blank clock signal CKV 1 a , a first blank clock bar signal CKVB 1 a , a second blank clock signal CKV 2 a , and a second blank clock bar signal CKVB 2 a . However, the blank clock signals CKVB according to the present inventive concept are not limited to those shown in FIG. 9 .

The first blank clock signal CKV 1 a and the second blank clock signal CKV 2 a may be signals output to wirings adjacent to each other in the display panel 100 (refer to FIG. 1 ). In addition, the first blank clock bar signal CKVB 1 a and the second blank clock bar signal CKVB 2 a may be signals output to wirings adjacent to each other in the display panel 100 (refer to FIG. 1 ).

Referring to the first blank clock signal CKV 1 a and the second blank clock signal CKV 2 a , the first blank clock signal CKV 1 a is the signal output to the first gate line GL 1 (refer to FIG. 1 ) and the second blank clock signal CKV 2 a is the signal output to the second gate line adjacent to the first gate line GL 1 (refer to FIG. 1 ).

The first blank clock signal CKV 1 a and the second blank clock signal CKV 2 a may have different voltage levels from each other, and the first blank clock bar signal CKVB 1 a and the second blank clock bar signal CKVB 2 a may have different voltage levels from each other. The first blank clock signal CKV a and the first blank clock bar signal CKVB 1 a may have opposite phases to each other in the active period AP, but may have the same phase as each other in the blank period BP.

As an example, the first blank clock signal CKV 1 a may have the high level, and the second blank clock signal CKV 2 a may have the low level in a portion of the blank period BP. The high level may be the gate-on voltage, and the low level may be the gate-off voltage. In other words, signals applied to wirings adjacent to each other may have different voltage levels from each other. Since there is a relatively high probability that the wirings or the voltage terminals adjacent to each other are short-circuited to each other, the overcurrent may be more easily detected by outputting the signals having different voltage levels from each other to the wirings adjacent to each other.

For example, the blank period BP may include a masking period MT and an overcurrent detecting period OCDP. When the active period AP is changed to the blank period BP, the current flowing through the voltage terminal may be maintained at a stable level after the predetermined time elapses. Accordingly, the overcurrent is detected after the masking period MT. This way, a noise component of a current observed during the predetermined time is not mistaken for an overcurrent.

Accordingly, the first blank clock signal CKV 1 a , the second blank clock signal CKV 2 a , the first blank clock bar signal CKVB 1 a , and the second blank clock bar signal CKVB 2 a have the low level during the masking period MT. During the overcurrent detecting period OCDP, the first blank clock signal CKV 1 a and the second blank clock signal CKV 2 a have different voltage levels from each other, and the first blank clock bar signal CKVB 1 a and the second blank clock bar signal CKVB 2 a may have different voltage levels from each other. When the voltage generator 221 (refer to FIG. 2 ) generates the blank clock signals CKVB during the blank period BP, the voltage generation circuit 220 (refer to FIG. 1 ) may receive the clock control signal CPV shown in FIG. 4 or the clock control signals CPV 1 a and CPV 1 b shown in FIG. 7 .

FIG. 10 is a timing diagram showing clock signals output during a blank period according to an exemplary embodiment of the present inventive concept.

FIG. 10 shows a first blank clock signal CKV 1 a , a first blank clock bar signal CKVB 1 a , a second blank clock signal CKV 2 a , and a second blank clock bar signal CKVB 2 a of an (n+1)th frame. FIG. 9 shows these signals in an n-th frame, for example.

Referring to FIGS. 9 and 10 , the first blank clock signal CKV 1 a , the first blank clock bar signal CKVB 1 a , the second blank clock signal CKV 2 a , and the second blank clock bar signal CKVB 2 a of the (n+1)th frame are output at voltages obtained by inverting the voltages of the first blank clock signal CKV 1 a (refer to FIG. 9 ), the first blank clock bar signal CKVB 1 a (refer to FIG. 9 ), the second blank clock signal CKV 2 a (refer to FIG. 9 ), and the second blank clock bar signal CKVB 2 a (refer to FIG. 9 ) of the n-th frame. When the display panel 100 (refer to FIG. 1 ) is the liquid crystal display panel, and the blank clock signals are inverted every frame as described with reference to FIG. 10 , the pixels can be prevented from burning and deteriorating.

Although the inventive concept has been shown and described with reference to exemplary embodiments thereof, it is understood by those of ordinary skill in the art that various changes in form and detail can be made thereto without departing from the spirit and scope of the inventive concept as hereinafter claimed.