Display device

This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2018-236407, filed Dec. 18, 2018, the entire contents of which are incorporated herein by reference.

Embodiments described herein relate generally to a display device.

Recently, in display devices, various technologies for suppressing reduction in reliability have been considered. In one example, from the perspective of securing desired adhesive strength, the following technology has been disclosed. That is, a transparent conductive film is provided between an alignment film which is in contact with a sealant and an inorganic insulating film which serves as a base for the alignment film.

In another example, in a liquid crystal display device comprising a touch sensor, from the perspective of suppressing noise caused by a high-frequency pulse for touch sensing, the following technology has been disclosed. That is, a mesh-patterned shield formed of a metal material is provided on sensor feed lines.

FIG. 1 is a plan view showing a configuration example of a display device DSP of the present embodiment.

FIG. 2 is a plan view showing a configuration example of a first substrate SUB 1 shown in FIG. 1 .

FIG. 3 is an enlarged plan view of a region including sensor electrodes Rx 1 and Rx 11 shown in FIG. 2 .

FIG. 4 is a cross-sectional view of a display panel PNL taken along line A-B shown in FIG. 3 .

FIG. 5 is a plan view showing a configuration example of a non-display portion NDA including a scanning line drive circuit GD 1 .

FIG. 6 is a circuit configuration example of a part of the scanning line drive circuit GD 1 shown in FIG. 5 .

FIG. 7 is a cross-sectional view of the display panel PNL taken along line C-D including a connection portion CN shown in FIG. 5 .

FIG. 8 is a cross-sectional view of the display panel PNL taken along line E-F including an opening OP shown in FIG. 5 .

In general, according to one embodiment, a display device includes a display portion in which a plurality of pixels are arranged in a matrix in a first direction and a second direction, a non-display portion around the display portion, a scanning line located in the display portion and extending in the first direction, a feed line at a common potential located in the non-display portion and extending in the second direction, a scanning line drive circuit located in the non-display portion and supplying a scanning signal to the scanning line, a first wiring line group located between the feed line and the scanning line drive circuit and connected to the scanning line drive circuit, and a transparent conductive film electrically connected to the feed line and covering the feed line, the first wiring line group and the scanning line drive circuit. The transparent conductive film has an opening overlapping the first wiring line group.

Embodiments will be described hereinafter with reference to the accompanying drawings. The disclosure is merely an example, and proper changes in keeping with the spirit of the invention, which are easily conceivable by a person of ordinary skill in the art, come within the scope of the invention as a matter of course. In addition, in some cases, in order to make the description clearer, the widths, thicknesses, shapes, etc., of the respective parts are illustrated schematically in the drawings, rather than as an accurate representation of what is implemented. However, such schematic illustration is merely exemplary, and in no way restricts the interpretation of the invention. In addition, in the specification and drawings, structural elements which function in the same or a similar manner to those described in connection with preceding drawings are denoted by like reference numbers, detailed description thereof being omitted unless necessary.

In the present embodiment, a liquid crystal display device will be described as an example of a display device DSP. Note that the main configurations disclosed in the present embodiment are also applicable to self-luminous display devices including organic electroluminescent display elements, μLEDs, etc., electronic paper type display devices including electrophoretic elements, display devices employing micro-electromechanical systems (MEMS), and display devices employing electrochromism.

FIG. 1 is a plan view showing a configuration example of the display device DSP of the present embodiment. In one example, a first direction X, a second direction Y and a third direction Z are orthogonal to one another but may cross one another at an angle other than 90 degrees. The first direction X and the second direction Y correspond to directions parallel to the surface of a substrate constituting the display device DSP, and the third direction Z corresponds to the thickness direction of the display device DSP.

The display device DSP includes a display panel PNL, an IC chip 1 and a flexible printed circuit 2 . The display panel PNL includes a display portion DA in which an image is displayed, and a frame-shaped non-display portion NDA which surrounds the display portion DA. The display portion DA includes a plurality of pixels PX arranged in a matrix in the first direction (row direction) X and the second direction (column direction) Y.

The display panel PNL is, for example, a liquid crystal display panel, and includes a first substrate SUB 1 , a second substrate SUB 2 , a liquid crystal layer LC and a sealant SE. The second substrate SUB 2 faces the first substrate SUB 1 . The sealant SE is located in the non-display portion NDA, and bonds the first substrate SUB 1 and the second substrate SUB 2 together and seals in the liquid crystal layer LC. The first substrate SUB 1 includes a mounting portion MA which extends more in the second direction Y than the second substrate SUB 2 does.

The IC chip 1 and the flexible printed circuit 2 are mounted on the mounting portion MA. Note that the IC chip 1 may be mounted on the flexible printed circuit 2 .

FIG. 2 is a plan view showing a configuration example of the first substrate SUB 1 shown in FIG. 1 . The first substrate SUB 1 includes the above-described display portion DA and non-display portion NDA. The first substrate SUB 1 has substrate end portions E 1 to E 4 . The substrate end portions E 1 and E 2 extend in the second direction Y and correspond to, for example, long sides. The substrate end portions E 3 and E 4 extend in the first direction X and correspond to, for example, short sides.

The first substrate SUB 1 includes a touch sensor TS in the display portion DA and includes the IC chip 1 in the non-display portion NDA.

A display driver DD and a touch controller TC are incorporated in the IC chip 1 . The display driver DD outputs a signal necessary for image display such as a video signal to the display panel PNL in an image display mode of displaying an image. The touch controller TC controls the touch sensor TS in a touch sensing mode of detecting approach of an object to or contact of an object with the display device DSP. Note that the touch controller TC may be incorporated in an IC chip other than the display driver DD.

Although the touch sensor TS will be described as a self-capacitance type touch sensor, the touch sensor TS may be a mutual capacitance type touch sensor. The touch sensor TS includes a plurality of sensor electrodes Rx and a plurality of sensor lines L. The sensor electrodes Rx are located in the display portion DA and are arranged in a matrix in the first direction X and the second direction Y. In the display portion DA, the sensor lines L extend in the second direction Y and are arranged in the first direction X. Each sensor line L is provided at, for example, a position overlapping a signal line S which will be described later. In addition, each sensor line L is drawn to the non-display portion NDA, is electrically connected to the IC chip 1 , and is electrically connected to the touch controller TC inside the IC chip 1 .

Here, attention will be focused on the relationship between sensor lines L 1 to L 3 arranged in the first direction X and sensor electrodes Rx 1 to Rx 3 arranged in the second direction Y. The sensor line L 1 overlaps the sensor electrodes Rx 1 to Rx 3 and is electrically connected to the sensor electrode Rx 1 .

The sensor line L 2 overlaps the sensor electrodes Rx 2 and Rx 3 and is electrically connected to the sensor electrode Rx 2 . A dummy line D 21 is spaced apart from the sensor line L 2 . The dummy line D 21 overlaps the sensor electrode Rx 1 and is electrically connected to the sensor electrode Rx 1 . The sensor line L 2 and the dummy line D 21 are located on the same signal line as will be described later.

The sensor line L 3 overlaps the sensor electrode Rx 3 and is electrically connected to the sensor electrode Rx 3 . A dummy line D 31 overlaps the sensor electrode Rx 1 and is electrically connected to the sensor electrode Rx 1 . A dummy line D 32 is spaced apart from the dummy line D 31 and the sensor line L 3 . The dummy line D 32 overlaps the sensor electrode Rx 2 and is electrically connected to the sensor electrode Rx 2 . The sensor line L 3 and the dummy lines D 31 and D 32 are located on the same signal line.

In the touch sensing mode, the touch controller TC applies a sensor drive voltage to the sensor lines L. Consequently, the sensor drive voltage is applied to the sensor electrodes Rx, and touch sensing in the sensor electrodes Rx is performed. Sensor signals corresponding to the results of sensing in the sensor electrodes Rx are output to the touch controller TC via the sensor lines L. Based on the sensor signals, the touch controller TC or an external host detects the presence or absence of approach of an object to or contact of an object with the display device DSP and the position coordinates of the object.

In the image display mode, a common voltage (Vcom) different from the sensor drive voltage is applied to the sensor electrodes Rx. The common voltage is applied from, for example, a voltage supply portion included in the display driver DD via the sensor lines L.

The first substrate SUB 1 includes scanning line drive circuits GD 1 and GD 2 , a feed line F, and wiring lines W 1 and W 2 in the non-display portion NDA. The scanning line drive circuit GD 1 is provided between the substrate end portion E 1 and the display portion DA. The scanning line drive circuit GD 2 is provided between the substrate end portion E 2 and the display portion DA.

The feed line F is provided along the substrate end portions E 1 to E 3 . In the example illustrated, the feed line F is provided between the substrate end portion E 1 and the scanning line drive circuit GD 1 , and is provided between the substrate end portion E 2 and the scanning line drive circuit GD 2 . The feed line F is electrically connected to, for example, the IC chip 1 , and the IC chip 1 supplies the common voltage to the feed line F. Furthermore, the common voltage supplied to the feed line F in the image display mode and the common voltage supplied to the feed line F in the touch sensing mode may have the same potential or may have different potentials.

Each of the wiring lines W 1 and W 2 is in the form of a frame surrounding the display portion DA. The wiring line W 1 is provided between the feed line F and the wiring line W 2 . The wiring line W 2 is provided between the wiring line W 1 and the display portion DA. The potential of the wiring line W 1 is different from the potential of the feed line F and the wiring line W 2 and is, for example, a fixed potential. In addition, the potential of the wiring line W 2 is the same as the potential of the feed line F. The potential of the wiring line W 1 may be relatively lower or may be relatively higher than the potential of the wiring line W 2 . If the potential of the wiring line W 1 is lower than the potential of the wiring line W 2 , the wiring line W 1 functions as an ion trap line which traps impurity ions having positive polarity. Alternatively, if the potential of the wiring line W 1 is higher than the potential of the wiring line W 2 , the wiring line W 1 functions an ion trap line which traps impurity ions having negative polarity. In one example, the potential of the wiring line W 2 is the same as the potential of a low-potential power supply VGL.

FIG. 3 is an enlarged plan view of a region including sensor electrodes Rx 1 and Rx 11 shown in FIG. 2 . Scanning lines G 1 to G 3 extend in the first direction X, and are arranged and spaced apart from one another in the second direction Y. The scanning lines G 1 to G 3 are electrically connected to the scanning line drive circuits GD 1 and GD 2 . Signal lines S 1 to S 5 extend in the second direction Y, and are arranged and spaced apart from one another in the first direction X. The signal lines S 1 to S 5 are electrically connected to the display driver DD. Note that the signal lines S 1 to S 5 are still assumed to extend in the second direction Y even if parts of the signal lines S 1 to S 5 are bent.

Common electrodes CE 1 and CE 2 are arranged and spaced apart from each other in the first direction X. The common electrode CE 1 corresponds to the sensor electrode Rx 1 shown in FIG. 2 , and the common electrode CE 2 corresponds to the sensor electrode Rx 11 shown in FIG. 2 .

A plurality of pixel electrodes PE overlap each of the common electrodes CE 1 and CE 2 . Each pixel electrode PE is electrically connected to one of the signal lines S 1 to S 5 via a switching element SW. For example, a switching element SW 1 shown in the drawing is electrically connected to the scanning line G 2 and the signal line S 3 . A pixel electrode PE 1 overlaps the common electrode CE 1 and is electrically connected to the signal line S 3 via the switching element SW 1 . In addition, a pixel electrode PE 2 overlaps the common electrode CE 2 and is electrically connected to the signal line S 4 via a switching element SW 2 .

Metal lines M 1 to M 5 extend in the second direction Y and are arranged in the first direction X. The metal lines M 1 to M 5 overlap the signal lines S 1 to S 5 , respectively. For example, the metal lines M 1 and M 2 correspond to the dummy line D 31 shown in FIG. 2 , and the metal line M 4 corresponds to the sensor line L 4 shown in FIG. 2 .

The common electrode CE 1 overlaps the metal lines M 1 and M 2 , and is electrically connected to the metal lines M 1 and M 2 in connection portions P 11 and P 12 , respectively.

The common electrode CE 2 overlaps the metal lines M 4 and M 5 , and is electrically connected to the metal line M 5 in a connection portion P 15 . In the example illustrated, the common electrode CE 2 and the metal line M 4 are not electrically connected to each other. The metal line M 4 is electrically connected to the touch controller TC.

FIG. 4 is a cross-sectional view of the display panel PNL taken along line A-B shown in FIG. 3 . The example illustrated corresponds to a case where a display mode using a lateral electric field is applied.

The first substrate SUB 1 includes an insulating substrate 10 , insulating films 11 to 16 , the signal lines S 2 to S 4 , the metal lines M 2 to M 4 , the common electrodes CE 1 and CE 2 , the pixel electrodes PE 1 and PE 2 , an alignment film AL 1 , and the like. The insulating substrate 10 is a light transmissive substrate such as a glass substrate or a flexible resin substrate. The insulating films 11 to 13 are arranged in the third direction Z in this order on the insulating substrate 10 . Although not shown in the drawing, a semiconductor layer provided in the switching element SW is located between the insulating films 11 and 12 , and the scanning line G is located between the insulating films 12 and 13 . The signal lines S 2 to S 4 are located between the insulating films 13 and 14 . In one example, the signal lines S 2 to S 4 are formed of a layered product of titanium (Ti), aluminum (Al) and titanium (Ti) which are stacked one on top of another, but the signal lines S 2 to S 4 may be formed of other metal materials. The metal lines M 2 to M 4 are located between the insulating films 14 and 15 . The metal lines M 2 to M 4 are located directly above the signal lines S 2 to S 4 , respectively. In one example, the metal lines M 2 to M 4 are formed of a layered product of titanium (Ti), aluminum (Al) and titanium (Ti) which are stacked one on top of another or a layered product of molybdenum (Mo), aluminum (Al) and molybdenum (Mo) which are stacked one on top of another, but the metal lines M 2 to M 4 may be formed of other metal materials.

The common electrodes CE 1 and CE 2 are located between the insulating films 15 and 16 . The insulating film 15 has a through hole CH 12 corresponding to the connection portion P 12 . The common electrode CE 1 is connected to the metal line M 2 in the through hole CH 12 .

The pixel electrodes PE 1 and PE 2 are located on the insulating film 16 and are covered with the alignment film AL 1 . The pixel electrode PE 1 is located directly above the common electrode CE 1 , and the pixel electrode PE 2 is located directly above the common electrode CE 2 . Each of the common electrodes CE 1 and CE 2 and the pixel electrodes PE 1 and PE 2 is a transparent electrode formed of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO).

Each of the insulating films 11 to 13 and the insulating film 16 is an inorganic insulating film of silicon oxide, silicon nitride, silicon oxynitride or the like, and may have a single layer structure or a multilayer structure. Each of the insulating films 14 and 15 is, for example, an organic insulating film such as acrylic resin. Note that the insulating film 15 may be an inorganic insulating film.

The second substrate SUB 2 includes an insulating substrate 20 , a light-shielding layer BM, a color filter layer CF, an overcoat layer OC, an alignment film AL 2 , and the like. The insulating substrate 20 is a light transmissive substrate such as a glass substrate or a resin substrate similarly to the insulating substrate 10 . The light-shielding layer BM and the color filter layer CF are located on a side of the insulating substrate 20 which faces the first substrate SUB 1 . The color filter layer CF includes a red color filter CFR, a green color filter CFG and a blue color filter CFB. In the example illustrated, the color filter CFB is located directly above the pixel electrode PE 1 , and the color filter CFR is located directly above the pixel electrode PE 2 . The overcoat layer OC covers the color filter layer CF. The alignment film AL 2 covers the overcoat layer OC. The alignment film AL 1 and the alignment film AL 2 are formed of, for example, a material exhibiting horizontal alignment properties.

The liquid crystal layer LC is located between the first substrate SUB 1 and the second substrate SUB 2 and is held between the alignment film AL 1 and the alignment film AL 2 .

An optical element OD 1 including a polarizer PL 1 is bonded to the insulating substrate 10 . An optical element OD 2 including a polarizer PL 2 is bonded to the insulating substrate 20 .

FIG. 5 is a plan view showing a configuration example of the non-display portion NDA including the scanning line drive circuit GD 1 . Note that the non-display portion NDA including the scanning line drive circuit GD 2 is configured similarly to the configuration example shown in FIG. 5 .

As indicated by a dash-dot line in FIG. 5 , the scanning line drive circuit GD 1 includes scan direction switching circuits SS 1 and SS 2 , shift registers SR 1 and SR 2 , gate switches GS 1 to GS 8 , and wiring line groups WG 1 and WG 2 . The scan direction switching circuits SS 1 and SS 2 and the wiring line group WG 1 are located between the feed line F and the shift registers SR 1 and SR 2 in the first direction X. The wiring line group WG 2 is located between the shift registers SR 1 and SR 2 and the gate switches GS 1 to GS 8 in the first direction X. The gate switches GS 1 to GS 8 are located between the wiring line group WG 2 and the wiring line W 1 in the first direction X.

Although the configuration examples of the respective parts will be described later, an example of wiring lines W 11 to W 19 constituting the wiring line group WG 1 will be briefly described below. The wiring line W 11 is a wiring line for an output monitor (OUTV), and the wiring line W 12 is a wiring line for supplying a vertical start pulse (STV). The wiring line W 13 is a wiring line for supplying a clock which sets a scan direction to a forward direction (UP). The wiring lines W 14 and W 15 are wiring lines corresponding to internal nodes. The wiring line W 16 is a wiring line for supplying a clock which sets a scan direction to a backward direction (xUP). The wiring line W 17 is a wiring line for supplying a transfer clock (CKV). The wiring line W 18 corresponds to a high-potential power supply line (VGH). The wiring line W 19 corresponds to a low-potential power supply line (VGL).

Each of the wiring lines W 13 and W 16 is electrically connected to the scan direction switching circuits SS 1 an SS 2 . The wiring lines W 14 and W 15 electrically connect the scan direction switching circuits SS 1 and SS 2 which are adjacent to each other in the second direction Y. Each of the wiring lines W 17 to W 19 is electrically connected to the shift registers SR 1 and SR 2 . The shift register SR 1 operates based on an output signal from the scan direction switching circuit SS 1 and controls the gate switches GS 1 to GS 4 . The gate switches GS 1 to GS 4 are electrically connected to the scanning lines G 1 to G 4 and supply scanning signals to the scanning lines G 1 to G 4 , respectively. The shift register SR 2 is configured similarly to the shift register SR 1 .

The wiring lines constituting the wiring line group WG 2 include wiring lines connected to the gate switches GS and power supply lines. The gate switches GS 1 to GS 4 are provided with corresponding wiring lines of the wiring line group WG 2 , and these wiring lines supply gate voltages to the scanning lines G 1 to G 4 , respectively.

A transparent conductive film TF is arranged so as to cover the feed line F and the scanning line drive circuit GD 1 . The transparent conductive film TF is electrically connected to the feed line F in a connection portion CN. That is, the potential of the transparent conductive film TF is a common potential similarly to the feed line F. In the present embodiment, the transparent conductive film TF does not cover the entire scanning line drive circuit GD 1 and has a plurality of openings OP overlapping the scanning line drive circuit GD 1 . The openings OP are arranged in the second direction Y.

In the region overlapping the scanning line drive circuit GD 1 , the openings OP are formed in a region close to the feed line F or a region close to the substrate end portion E 1 than the display portion DA. More specifically, the openings OP overlap the wiring line group WG 1 . In the present embodiment, the transparent conductive film TF covers the scan direction switching circuits SS 1 and SS 2 , and in the region overlapping the wiring line group WG 1 , the opening OP is formed in a region between the scan direction switching circuits SS 1 and SS 2 which are adjacent to each other. Note that the transparent conductive film TF may not cover the scan direction switching circuits SS 1 and SS 2 . In that case, openings OP will be formed also in portions overlapping the scan direction switching circuits SS 1 and SS 2 , respectively, in the transparent conductive film TF located between the openings OP.

An end portion Ell on the display portion DA side of the transparent conductive film TF overlaps the gate switches GS 1 to GS 8 . That is, the transparent conductive film TF covers parts of the gate switches GS 1 to GS 8 between the wiring line group WG 2 and the wiring line W 1 . On the other hand, the end portion Ell of the transparent conductive film TF does not overlap the wiring lines W 1 and W 2 . Note that, although not shown in the drawing, a transparent conductive film in a layer different from the transparent conductive film TF may overlap each of the wiring lines W 1 and W 2 .

As indicated by a dash-dot-dot line in FIG. 5 , the sealant SE overlaps the feed line F and a part of the transparent conductive film TF in a planar view. In addition, the sealant SE overlaps the openings OP in its central portion, and the end portions of the sealant SE do not overlap the openings OP. Furthermore, the sealant SE overlaps a part of the scanning line drive circuit GD 1 , that is, the wiring line group WG 1 , the scan direction switching circuits SS 1 and SS 2 and the shift registers SR 1 and SR 2 . An end portion E 21 on the display portion DA side of the sealant SE overlaps the wiring line group WG 2 . That is, the sealant SE covers a part of the wiring line group WG 2 between the shift registers SR 1 and SR 2 and the wiring line W 1 . In addition, the end portion Ell of the transparent conductive film TF is located between the end portion E 21 of the sealant SE and the display portion DA.

FIG. 6 is a circuit configuration example of a part of the scanning line drive circuit GD 1 shown in FIG. 5 . The scan direction switching circuit SS 1 includes switches SW 11 and SW 12 . Each of the switches SW 11 and SW 12 is formed of a P-type transistor and an N-type transistor which are connected in parallel. The scan direction switching circuit SS 2 is configured similarly to the scan direction switching circuit SS 1 .

The shift register SR 1 includes a NOR circuit NR and switches SW 13 to SW 16 . One end of the NOR circuit NR is connected to the wiring line W 18 which is the high-potential power supply line (VGH), and the other end of the NOR circuit NR is connected to the wiring line W 19 which is the low-potential power supply line (VGL). The switch SW 13 which is a P-type transistor is connected in series to the switch SW 14 which is an N-type transistor. The switch SW 13 side is connected to the wiring line W 17 , and the switch SW 14 side is connected to the wiring line W 19 . The switch SW 15 which is a P-type transistor is connected in series to the switch SW 16 which is an N-type transistor. The switch SW 15 side is connected to the wiring line W 18 , and the switch SW 16 side is connected to the wiring line W 19 .

The shift register SR 2 includes a NAND circuit ND and switches SW 17 to SW 20 . The switch SW 17 is formed of two P-type transistors which are connected in parallel. The switch SW 17 is connected in series to the switch SW 18 which is an N-type transistor. The switch SW 17 side is connected to the wiring line W 18 , and the switch SW 18 side is connected to the wiring line W 17 . The switch SW 19 which is a P-type transistor is connected in series to the switch SW 20 which is an N-type transistor. The switch SW 19 side is connected to the wiring line W 18 , and the switch SW 20 side is connected to the wiring line W 19 .

Note that the circuit configuration of the scanning line drive circuit GD 1 is not limited to the example illustrated.

FIG. 7 is a cross-sectional view of the display panel PNL taken along line C-D including the connection portion CN shown in FIG. 5 . Note that the optical elements OD 1 and OD 2 shown in FIG. 4 are not illustrated. In In the first substrate SUB 1 , the feed line F is located between the insulating films 13 and 14 . The insulating film 14 has a through hole CH 11 penetrating to the feed line F. A connection electrode CN 1 is located between the insulating films 14 and 15 and is in contact with the feed line F in the through hole CH 11 . The insulating film 15 has the through hole CH 12 penetrating to the connection electrode CN 1 . A connection electrode CN 2 is located between the insulating films 15 and 16 and is in contact with the connection electrode CN 1 in the through hole CH 12 . The insulating film 16 has a through hole CH 13 penetrating to the connection electrode CN 2 . The transparent conductive film TF is located between the insulating film 16 and the alignment film AL 1 and is in contact with the connection electrode CN 2 in the through hole CH 13 .

In the example illustrated, the through holes CH 11 to CH 13 are deviated from one another in the second direction Y such that the through holes CH 11 to CH 13 will not overlap one another. That is, the insulating film 15 is arranged in the through hole CH 11 , and the insulating film 16 is arranged in the through hole CH 12 . Note that the through holes CH 11 to CH 13 may be arranged such that at least two of the through holes CH 11 to CH 13 will overlap each other.

The feed line F is a metal line located in the same layer as the signal line S 2 , etc., shown in FIG. 4 and formed of the same material as the signal line S 2 . The connection electrode CN 1 is a metal electrode located in the same layer as the metal line M 2 , etc., and formed of the same material as the metal line M 2 . The connection electrode CN 2 is a transparent electrode located in the same layer as the common electrode CE 1 , etc., and formed of the same material as the common electrode CE 1 . The transparent conductive film TF is located in the same layer as the pixel electrode PE 1 , etc., and is formed of the same material as the pixel electrode PE 1 .

The sealant SE is provided between the alignment films AL 1 and AL 2 and overlaps the connection portion CN. An upper surface ALA of the alignment film AL 1 is in contact with the sealant SE. An upper surface TFA of the transparent conductive film TF is in contact with the alignment film AL 1 . A lower surface TFB of the transparent conductive film TF is in contact with the insulating film 16 .

FIG. 8 is a cross-sectional view of the display panel PNL taken along line E-F including the opening OP shown in FIG. 5 . Note that the optical elements OD 1 and OD 2 shown in FIG. 4 are not illustrated. In the example illustrated, the feed line F and the wiring lines W 11 to W 19 are located in the same layer and are located between the insulating films 13 and 14 . The transparent conductive film TF is located directly above the feed line F and the wiring lines W 18 and W 19 . The opening OP is formed directly above the wiring lines W 11 to W 17 . In the opening OP, the alignment film AL 1 is in contact with the insulating film 16 .

Meanwhile, suppose that a voltage corresponding to a minimum grayscale value and a voltage corresponding to a maximum grayscale value are alternately applied to the signal lines S when a specific pattern such as a checker pattern is displayed in the display portion DA. At this time, the metal line M (and the common electrode CE electrically connected to the metal line M) overlapping the signal line S is capacitively coupled to the signal line S. Therefore, when the fluctuation of the potential of the signal line S is large, the fluctuation of the potential of the common electrode CE is large. The potential fluctuation of the common electrode CE is transferred to the feed line F via the IC chip 1 which is the supply source of the common potential, and may cause malfunction of the scanning line drive circuits GD 1 and GD 2 which the feed line F overlaps. In particular, the wiring line which supplies the clock or start pulse of the wiring line group WG 1 is more vulnerable to the influence of malfunction than the power supply line of the wiring line group WG 1 and the wiring line group GW 2 .

According to the present embodiment, the transparent conductive film TF electrically connected to the feed line F has the openings OP overlapping the scanning line drive circuits GD 1 and GD 2 . Therefore, even if the potential fluctuation of the common electrode CE is transferred to the feed line F, the influence can be reduced. Consequently, malfunction of the scanning line drive circuits GD 1 and GD 2 can be suppressed, and reduction in reliability can be suppressed.

In addition, the openings OP overlap the wiring line group WG 1 , and parasitic capacitance can be reduced. Furthermore, the transparent conductive film TF overlaps the circuit portions (the scan direction switching circuits SS 1 and SS 2 and the shift registers SR 1 and SR 2 ) of the scanning line drive circuit GD 1 and the high-potential power supply line W 18 , and blocks an electric field from the circuit portions to the liquid crystal layer LC.

Furthermore, in the region overlapping the sealant SE, the transparent conductive film TF is firmly bonded to the alignment film AL 1 and the insulating film 16 on both the substrate end portion E 1 side and the display portion DA side across the opening OP. For this reason, interlayer peeling in the region overlapping the sealant SE can be suppressed.

In the present embodiment, the shift register SR 1 corresponds to the first shift register, and the shift register SR 2 corresponds to the second shift register. The scan direction switching circuit SS 1 corresponds to the first scan direction switching circuit, and the scan direction switching circuit S 22 corresponds to the second scan direction switching circuit. The wiring line group WG 1 corresponds to the first wiring line group, and the wiring line group WG 2 corresponds to the second wiring line group.

The end portion Ell of the transparent conductive film TF corresponds to the first end portion, and the end portion E 21 of the sealant SE corresponds to the second end portion. The insulating film 14 corresponds to the first insulating film, and the through hole CH 11 corresponds to the first through hole. The insulating film 15 corresponds to the second insulating film, and the through hole CH 12 corresponds to the second through hole. The insulating film 16 corresponds to the third insulating film, and the through hole CH 13 corresponds to the third through hole. The connection electrode CN 1 corresponds to the first connection electrode, and the connection electrode CN 2 corresponds to the second connection electrode.

As described above, according to the present embodiment, a display device which can suppress reduction in reliability can be provided.

While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.