Write assist circuitry

This section is intended to provide information relevant to understanding the various technologies described herein. As the section's title implies, this is a discussion of related art that should in no way imply that it is prior art. Generally, related art may or may not be considered prior art. It should therefore be understood that any statement in this section should be read in this light, and not as any admission of prior art.

Memory compilers utilize configuration data to generate physical layout designs of memory circuitry for read and write access operations. Traditional memory compilers examine characterized data to develop various memory instances that cover the memory compiler space. However, some traditional techniques typically introduce accuracy errors in reference to memory instance data. In some cases, various leakage, timing, power and noise data for the memory instances is stored, and some traditional memory compilers typically analyze error prone memory instances related to entire memory circuits, gather results, and then compute a final result. These accuracy errors often effect reliability of memory instances. Thus, traditional layout techniques can be inefficient, time-consuming and unreliable, and traditional layout techniques can cause accuracy errors due to some memory instances having sensitivity to a number of rows (e.g., bitcells, columns, and/or wordline drivers). As such, there exists a need to improve physical design implementation of memory circuits to provide for more reliable read and write access operations.

Implementations of various techniques are described herein with reference to the accompanying drawings. It should be understood, however, that the accompanying drawings illustrate only various implementations described herein and are not meant to limit embodiments of various techniques described herein.

FIGS. 1A-1D illustrate memory circuitry that uses write assist schemes and techniques in accordance with various implementations described herein.

FIGS. 2A-2D illustrate memory circuitry that uses other write assist schemes and techniques in accordance with implementations described herein.

FIG. 3 illustrates memory circuitry that uses other write assist schemes and techniques in accordance with implementations described herein.

FIG. 4 illustrates other memory circuitry that uses write assist schemes and techniques in accordance with implementations described herein.

FIGS. 5A-5B illustrate other memory circuitry that uses write assist schemes and techniques in accordance with implementations described herein.

Various implementations described herein are directed to write assist schemes and techniques that may improve read and write operations in physical layout design of memory architecture. For instance, various schemes and techniques described herein may provide for a system or device having a single port memory architecture that supports dual wordline circuitry. In some instances, the access schemes and techniques described herein may be configured to provide write assist circuitry for dual y-mux memory with no impact on read operations, and the write assist circuitry may have optimized area, e.g., with no need to duplicate column multiplexers on upper and lower bitcell arrays. Also, the write assist circuitry may improve the reliability of memory while writing actual bitcells and with no impact on reference bitcells. The memory architecture may refer to static random access memory (SRAM) or magneto-resistive random access memory (MRAM). The memory architecture may include memory circuitry having a core array of bitcells that are accessible via bitlines. In SRAM, bitlines may refer to complementary bitlines (BL, NBL), and in MRAM, bitlines may refer to a bitline (BL) and a source line (SL).

Various implementations of read and write access schemes and techniques will be described in detail herein with reference to FIGS. 1A-5B .

FIGS. 1A-1D illustrate memory circuitry 100 that utilizes write assist schemes and techniques in accordance with some implementations described herein. In particular, FIG. 1A shows a configurational diagram 100 A of the memory circuitry 100 , FIG. 1B shows a write_0 operational diagram 100 B of the memory circuitry 100 , FIG. 1C shows a write_1 operational diagram 100 C of the memory circuitry 100 , and FIG. 1D shows a read operational diagram 100 D of the memory circuitry 100 .

In some instances, the memory circuitry 100 may be implemented as a system or device having various circuit components that are arranged and/or coupled together as an assemblage or some combination of parts that provide for a physical layout design and related structures. Also, in some instances, a method of designing, providing and building the memory circuitry 100 may involve use of various circuit components described herein so as to implement write assist schemes and techniques associated therewith.

As shown in FIG. 1A , the memory circuitry 100 may include various circuitry, such as, e.g., write assist circuitry 120 , a core array 122 of bitcells (BC) 108 , and column multiplexer circuitry 124 . In some instances, the write assist circuitry 120 may include various circuit components, such as, e.g., multiple passgates T 1 -T 4 , that are coupled to one or more bitlines (BL, NBL). Also, in some instances, the column multiplexer circuitry 124 may include various circuit components, such as, e.g., multiplexers 112 A, 112 B and read-write circuitry 126 , that are coupled to the bitlines (BL, NBL). The read-write circuitry 126 may include write driver circuitry 114 and sense amplifier circuitry 118 .

The memory circuitry 100 may be implemented with one or more core arrays 122 in various multi-bank configurations, wherein each bank has an array of memory cells or bitcells. Each bitcell may be configured to store at least one data bit value (e.g., data value related to a logical ‘0’ or ‘1’). The one or more core arrays 108 include any number of bitcells arranged in various configurations, such as, e.g., two-dimensional (2D) memory arrays having any number of columns and any number of rows of multiple bitcells, which may be arranged in a 2D grid pattern for read and write memory access. Each bitcell may be implemented with any type of memory, including, e.g., static random access memory (SRAM), magneto-resistive RAM (MRAM), and/or any other type of similar memory. Also, each bitcell may include a multi-transistor static RAM (SRAM) cell, including various types of SRAM cells, such as, e.g., any type of complementary MOS (CMOS) SRAM cells, such as, e.g., 4T, 6T, 8T, 10T, or more transistors per bit. In other instances, each bitcell may include a multi-layer MRAM bitcell having free-layers and pinned layers. In SRAM, the bitlines may refer to complementary bitlines (BL, NBL), and in MRAM, the bitlines may refer to a bitline (BL) and a source line (SL).

The write assist circuitry 120 may include the passgates T 1 , T 2 , T 3 , T 4 that are coupled to the bitcells 108 via the bitlines (BL, NBL). The passgates may include a first passgate T 1 coupled to the bitcells 108 via a first bitline BL and a second passgate T 2 coupled to the bitcells 108 via a second bitline NBL. In some instances, a gate of the first passgate T 1 may receive a global write enable (GWEN) signal or a write controlled clock, and a gate of the second passgate T 2 may be coupled to the first bitline BL. The first passgate T 1 may be a first N-type transistor, and the second passgate T 2 may be a second N-type transistor. However, in other configurations, the first passgate T 1 and/or the second passgate T 2 may be implemented with a P-type transistor.

The write assist circuitry 120 may include at least one transmission gate (T 3 , T 4 ) that is coupled to the first bitline BL between the first passgate T 1 and the bitcells 108 in the core array 122 , and the gate of the second passgate T 2 may be coupled between the transmission gate (T 3 , T 4 ) and the first passgate T 1 . The transmission gate (T 3 , T 4 ) may include a third passgate T 3 (e.g., a P-type transistor) and a fourth transistor T 4 (e.g., an N-type transistor). In some instances, a gate of the third passgate T 3 may receive a first global write enable signal (e.g., GWEN), and a gate of the fourth passgate T 4 may receive a second global write enable signal (e.g., NGWEN) that is complementary to the first global write enable signal (e.g., GWEN). The third passgate T 3 may be a P-type transistor, and the fourth passgate T 4 may be a third N-type transistor. However, in other configurations, the third passgate T 3 may be implemented with an N-type transistor, and the fourth passgate T 4 may be implemented with an N-type transistor.

The column multiplexer circuitry 124 may include the multiplexers (Mux) 112 A, 112 B and the read-write circuitry 126 having the write driver circuitry 114 and the sense amplifier circuitry 118 that are coupled to the bitlines (BL, NBL). The multiplexers (Mux) 112 A, 112 B may include a first multiplexer (Mux) 112 A that is coupled to the bitcells 108 via the first bitline BL between the bitcells 108 and a first data input (d) of the read-write circuitry 126 . The multiplexers (Mux) 112 A, 112 B may include a second multiplexer (Mux) 112 B that is coupled to the bitcells 108 via the second bitline NBL between the bitcells 108 and a second data input (nd) of the read-write circuitry 126 .

The memory circuitry 100 may be implemented as an integrated circuit (IC) in various types of memory, such as, e.g., random access memory (RAM), including static RAM (SRAM), magneto-resistive RAM (MRAM), and/or any similar memory. The memory circuitry 100 may also be implemented as an IC with single-port memory architecture and related circuitry. The memory circuitry 100 may also be integrated with computing circuitry and related components on a single chip. The memory circuitry 100 may be implemented in various embedded systems for various electronic, mobile and Internet-of-things (IoT) applications, including low power sensor nodes.

As shown in FIG. 1B , the write_0 operational diagram 100 B of the memory circuitry 100 shows a signal path flow of logic_1 on the first bitline BL through at least one bitcell 108 to a logic_0 on the second bitline NBL. In this instance, transistor T 1 receives the GWEN signal in a logic_0 state, which deactivates transistor T 1 , and thus, transistor T 2 is ON by activation signal (logic_1) via the first bitline (BL) at node (n 1 ). Also, transistor T 3 receives the GWEN signal in a logic_0 state, which activates transistor T 3 (ON), and transistor T 4 receives the NGWEN signal in a logic_1 state, which activates transistor T 4 (ON). In MRAM, the second bitline may be referred to as a source line (SL).

As shown in FIG. 1C , the write_1 operational diagram 100 C of the memory circuitry 100 shows a signal path flow of logic_0 on the first bitline BL through at least one bitcell 108 to a logic_1 on the second bitline NBL. In this instance, transistor T 1 receives the GWEN signal in a logic_0 state, which deactivates transistor T 1 , and thus, transistor T 2 is OFF by activation signal (logic_0) via the first bitline BL at node (n 1 ). Also, transistor T 3 receives the GWEN signal in a logic_0 state, which activates transistor T 3 (ON), and transistor T 4 receives the NGWEN signal in a logic_1 state, which activates transistor T 4 (ON). In MRAM, the second bitline may be referred to as a source line (SL).

As shown in FIG. 1D , the read operational diagram 100 D of the memory circuitry 100 shows the transmission gate (T 3 , T 4 ) as deactivated (OFF). For instance, transistor T 3 receives the GWEN signal in a logic_1 state, which deactivates transistor T 3 (OFF), and transistor T 4 receives the NGWEN signal in a logic_0 state, which deactivates transistor T 4 (OFF). In this instance, transistor T 1 receives the GWEN signal in a logic_1 state, which activates transistor T 1 , which passes ground to the first bitline BL, and thus, transistor T 2 is OFF by the grounded signal (logic_0) via the first bitline BL at node (n 1 ). In SRAM, the bitlines may refer to complementary bitlines (BL, NBL), and in MRAM, the bitlines may refer to a bitline (BL) and a source line (SL).

FIGS. 2A-2D illustrate memory circuitry 100 that utilizes write assist schemes and techniques in accordance with some implementations described herein. In particular, FIG. 2A shows a configurational diagram 200 A of the memory circuitry 200 , FIG. 2B shows a write_0 operational diagram 200 B of the memory circuitry 200 , FIG. 2C shows a write_1 operational diagram 200 C of the memory circuitry 200 , and FIG. 2D shows a read operational diagram 200 D of the memory circuitry 200 .

In some instances, the memory circuitry 200 may be implemented as a system or device having various circuit components that are arranged and/or coupled together as an assemblage or some combination of parts that provide for a physical layout design and related structures. Also, in some instances, a method of designing, providing and building the memory circuitry 200 may involve use of various circuit components described herein so as to implement write assist schemes and techniques associated therewith.

As shown in FIG. 2A , the memory circuitry 200 may include various circuitry, such as, e.g., write assist circuitry 220 , the core array 122 of bitcells 108 , and the column multiplexer circuitry 124 . In some instances, the write assist circuitry 220 may include various circuit components, such as, e.g., multiple passgates M 1 -M 3 and T 3 -T 4 , that are coupled to one or more bitlines (BL, NBL). Also, the column multiplexer circuitry 124 may include various circuit components, such as, e.g., the multiplexers 112 A, 112 B and the read-write circuitry 126 , that are coupled to the bitlines (BL, NBL). The read-write circuitry 126 may include the write driver circuitry 114 and the sense amplifier circuitry 118 . In SRAM, the bitlines may refer to complementary bitlines (BL, NBL), and in MRAM, the bitlines may refer to a bitline (BL) and a source line (SL).

The write assist circuitry 220 may include the passgates M 1 , M 2 , M 3 , T 3 , T 4 that are coupled to the bitcells 108 via the bitlines (BL, NBL). The passgates may include a first passgate M 1 coupled to the bitcells 108 via a first bitline BL and a second passgate M 2 coupled to the bitcells 108 via a second bitline NBL. In some instances, a gate of the first passgate M 1 may be coupled to the second bitline NBL, and a gate of the second passgate M 2 may be coupled to the first bitline BL, wherein the gates of the passgates (M 1 , M 2 ) are cross-coupled to the bitlines (BL, NBL). The passgates may also include a third passgate M 3 that is coupled between the gate of the second passgate M 2 and ground e.g., Vss or Gnd), and a gate of the third passgate M 3 may receive the global write enable (GWEN) signal. The first passgate M 1 may be a first N-type transistor, the second passgate M 2 may be a second N-type transistor, and also, the third passgate M 3 may be a third N-type transistor. However, the first passgate M 1 , the second passgate M 2 , and/or the third passgate M 3 may be implemented with a P-type transistor.

The write assist circuitry 120 may include the transmission gate (T 3 , T 4 ) that is coupled to the first bitline BL between the first passgate M 1 and the bitcells 108 in the core array 122 , and the gate of the second passgate M 2 may be coupled between the transmission gate (T 3 , T 4 ) and the first passgate M 1 . The transmission gate (T 3 , T 4 ) may include the third passgate T 3 (e.g., a P-type transistor) and the fourth transistor T 4 (e.g., an N-type transistor). In some instances, a gate of the third passgate T 3 may receive the first global write enable signal (e.g., GWEN), and the gate of the fourth passgate T 4 may receive a second global write enable signal (e.g., NGWEN) that is complementary to the first global write enable signal (e.g., GWEN). Also, the third passgate T 3 may be a P-type transistor, and the fourth passgate T 4 may be a third N-type transistor. However, in other configurations, the third passgate T 3 may be implemented with an N-type transistor, and the fourth passgate T 4 may be implemented with an N-type transistor.

The memory circuitry 200 may be implemented as an integrated circuit (IC) in various types of memory, such as, e.g., random access memory (RAM), including static RAM (SRAM), magneto-resistive RAM (MRAM), and/or any similar memory. The memory circuitry 200 may also be implemented as an IC with single-port memory architecture and related circuitry. The memory circuitry 200 may also be integrated with computing circuitry and related components on a single chip. The memory circuitry 200 may be implemented in various embedded systems for various electronic, mobile and Internet-of-things (IoT) applications, including low power sensor nodes.

As shown in FIG. 2B , the write_0 operational diagram 200 B of the memory circuitry 200 shows a signal path flow of logic_1 on the first bitline BL through at least one bitcell 108 to a logic_0 on the second bitline NBL. In this instance, transistor M 1 receives the logic_0 signal from the second bitline NBL via node (n 3 ), which deactivates transistor M 1 (OFF), and also, transistor M 2 receives the logic_1 signal from the first bitline via node (n 2 ), which activates transistor M 2 (ON). Also, in this instance, transistor M 3 receives the GWEN signal in a logic_0 state, which deactivates transistor M 3 (OFF) and blocks the first bitline signal from going to ground. In the transmission gate (T 3 , T 4 ), transistor T 3 receives the GWEN signal in a logic_0 state, which deactivates transistor T 3 (ON), and transistor T 4 receives the NGWEN signal in a logic_1 state, which activates transistor T 4 (ON). In MRAM, the second bitline may be referred to as a source line (SL).

As shown in FIG. 2C , the write_1 operational diagram 200 C of the memory circuitry 200 shows a signal path flow of logic_0 on the first bitline BL through at least one bitcell 108 to a logic_1 on the second bitline NBL. In this instance, transistor M 1 receives the logic_1 signal from the second bitline NBL via node (n 3 ), which activates transistor M 1 (ON), and also, transistor M 2 receives the logic_0 signal from the first bitline via node (n 2 ), which deactivates transistor M 2 (OFF). Also, in this instance, transistor M 3 receives the GWEN signal in a logic_0 state, which deactivates transistor M 3 (OFF) and blocks the first bitline signal from going to ground. In the transmission gate (T 3 , T 4 ), transistor T 3 receives the GWEN signal in a logic_0 state, which deactivates transistor T 3 (ON), and transistor T 4 receives the NGWEN signal in a logic_1 state, which activates transistor T 4 (ON). In MRAM, the second bitline may be referred to as a source line (SL).

As shown in FIG. 2D , the read operational diagram 200 D of the memory circuitry 200 shows the transmission gate (T 3 , T 4 ) as deactivated (OFF). For instance, in the transmission gate (T 3 , T 4 ), transistor T 3 receives the GWEN signal in a logic_1 state, which deactivates transistor T 3 (OFF), and transistor T 4 receives the NGWEN signal in a logic_0 state, which deactivates transistor T 4 (OFF). Also, in this instance, transistor M 1 is OFF, transistor M 2 is OFF, and transistor M 3 is ON. In addition, as shown in FIG. 2D , transistor M 3 receives the GWEN signal in a logic_1 state, which activates transistor M 3 (ON), which coupled the gate of transistor M 2 to ground (e.g., Vss or Gnd). In SRAM, the bitlines may refer to complementary bitlines (BL, NBL), and in MRAM, the bitlines may refer to a bitline (BL) and a source line (SL).

FIG. 3 illustrates memory circuitry 300 that uses other write assist schemes and techniques in accordance with implementations described herein. In particular, the memory circuitry 300 of FIG. 3 is similar to the memory circuitry 100 of FIG. 1 , except for addition of a fifth passgate T 5 and inverter (i 1 ) coupled to the first bitline BL.

As shown in FIG. 3 , the memory circuitry 300 may include various circuitry, such as, e.g., write assist circuitry 320 , the core array 122 of bitcells 108 , and the column multiplexer circuitry 124 . In some instances, the write assist circuitry 220 may include various circuit components, such as, e.g., multiple passgates T 1 -T 5 , that are coupled to one or more bitlines (BL, NBL). Also, the column multiplexer circuitry 124 may include various circuit components, such as, e.g., the multiplexers 112 A, 112 B and the read-write circuitry 126 , that are coupled to the bitlines (BL, NBL). The read-write circuitry 126 may include the write driver circuitry 114 and the sense amplifier circuitry 118 . In SRAM, the bitlines may refer to complementary bitlines (BL, NBL), and in MRAM, the bitlines may refer to a bitline (BL) and a source line (SL).

The write assist circuitry 220 may include the passgates M 1 , M 2 , M 3 , M 4 along with passgate M 5 that are coupled to the bitcells 108 via the bitlines (BL, NBL). As shown, the passgates may include the passgate T 1 coupled to the bitcells 108 via the bitline BL and the passgate T 2 coupled to the bitcells 108 via the bitline NBL. The gate of passgate T 1 may be coupled to the bitline NBL, and the gate of the passgate T 2 may be coupled to the bitline BL. The passgate T 5 may be coupled to the first bitline (BL) between the first passgate (T 1 ) and ground (e.g., Vss or Gnd), and the inverter (i 1 ) may be coupled between the first bitline (BL) and a gate of the passgate T 5 . The passgate T 1 may be an N-type transistor, the passgate T 2 may be an N-type transistor, and the passgate T 5 may be an N-type transistor. Also, the passgate T 3 may be a P-type transistor, and passgate T 4 may be an N-type transistor. However, in some configurations, one or more passgates T 1 , T 2 , T 5 may be implemented with a P-type transistor.

FIG. 4 illustrates other memory circuitry 400 that uses write assist schemes and techniques in accordance with various implementations described herein.

In some instances, the memory circuitry 400 may be implemented as a system or device having various circuit components that are arranged and/or coupled together as an assemblage or some combination of parts that provide for a physical layout design and related structures. Also, in some instances, a method of designing, providing and building the memory circuitry 400 may involve use of various circuit components described herein so as to implement write assist schemes and techniques associated therewith.

As shown in FIG. 4 , the memory circuitry 400 may include various circuitry, such as, e.g., write assist circuitry 420 , a first core array 422 A of first bitcells (BC) 408 A, and a second core array 422 B of second bitcells (BC) 408 B. In some instances, the write assist circuitry 420 may include various circuit components, such as, e.g., passgate logic 432 , 434 and write drivers (WD 1 , WD 2 ), that are coupled to one or more bitlines (BL, NBL). In some instances, the memory circuitry 400 may include clock circuitry 430 that receives an address signal (A), e.g., as an input clock pulse, and provides one or more selection signals (S 0 , S 1 ), e.g., as one or more output clock pulses. In some instances, the clock circuitry 430 may include multiple series-coupled inverters (i 4 , i 5 ). In SRAM, the bitlines may refer to complementary bitlines (BL, NBL), and in MRAM, the bitlines may refer to a bitline (BL) and a source line (SL).

The memory circuitry 400 may be implemented with one or more core arrays 422 A, 422 B in various multi-bank configurations, wherein each bank may have an array of memory cells or bitcells. For instance, the core arrays 422 A, 422 B may include a first bank 422 A or bottom segment (Bot_Seg), and the core arrays 422 A, 422 B may include a second bank 422 B or top segment (Top_Seg). It should be appreciated that reference to top and/or bottom may be relative to the positional orientation of the memory circuitry 400 , and reference to top and/or bottom may be referred to as upper and/or lower. In various instances, the bitlines (BL, NBL) may have resistive factors associated therewith, wherein, e.g., the bitline BL may have a resistance coefficient factor RBL, and also, the other bitline NBL may have another resistance coefficient factor RNBL.

In some instances, each bitcell may be configured to store at least one data bit value (e.g., a data value related to a logical ‘0’ or ‘1’). The one or more core arrays 422 A, 422 B include any number of bitcells arranged in various configurations, such as, e.g., two-dimensional (2D) memory arrays having any number of columns and any number of rows of multiple bitcells, which may be arranged in a 2D grid pattern for read and write memory access. Each bitcell may be implemented with any type of memory, including, e.g., static random access memory (SRAM), magneto-resistive RAM (MRAM), and/or any other type of similar memory. Also, each bitcell may include a multi-transistor static RAM (SRAM) cell, including various types of SRAM cells, such as, e.g., any type of complementary MOS (CMOS) SRAM cells, such as, e.g., 4T, 6T, 8T, 10T, or more transistors per bit. In other instances, each bitcell may include a multi-layer MRAM bitcell having free-layers and pinned layers. In SRAM, the bitlines may refer to complementary bitlines (BL, NBL), and in MRAM, the bitlines may refer to a bitline (BL) and a source line (SL).

The write assist circuitry 420 may include passgate logic circuitry, such as, e.g., first passgate logic 432 and second passgate logic 434 . The first passgate logic 432 may include one or more transistors (e.g., T 10 , T 11 ) that are coupled in parallel to a power supply input of a write driver (e.g., WD 1 ). The second passgate logic 434 may include one or more transistors (e.g., T 12 , T 13 ) that are also coupled in parallel to a power supply input of another write driver (e.g., WD 2 ). The first passgate logic 432 may provide a first voltage (VBL) to the power supply input of the write driver WD 1 , and the second passgate logic 434 may provide a second voltage (VNBL) to the power supply input of the other write driver WD 2 . In some configurations, transistors T 10 , T 11 , T 12 , T 13 may be parallel-coupled P-type transistors. However, in other configurations, transistors T 10 , T 11 , T 12 , T 13 may be parallel-coupled N-type transistors.

In some implementations, the write assist circuitry 420 may include one or more write drivers (WD 1 , WD 2 ) that are coupled to the bitcells 408 A, 408 B via the bitlines (BL, NBL) including, e.g., a first write driver WD 1 coupled to the bitcells 408 A, 408 B via a first bitline BL and a second write driver WD 2 coupled to the bitcells 408 A, 408 B via a second bitline NBL that is complementary to the first bitline BL. In reference to MRAM, the second bitline may refer to a source line (SL). Also, the write assist circuitry 420 may include the first passgate logic 432 coupled to a first power supply input of the first write driver WD 1 , and the write assist circuitry 420 may include the second passgate logic 434 coupled to a second power supply input of the second write driver WD 2 . The write drivers (WD 1 , WD 2 ) may be implemented with inverters (i 2 , i 3 ). The first write driver WD 1 may receive a data signal (D) and provide an output signal to the bitline BL based on the power supply input, and the second write driver WD 2 may receive a complementary data signal (ND) and provide an output signal to the bitline NBL based on the power supply input.

In some instances, the first passgate logic 432 may include a first transistor T 10 coupled between a first voltage source supply VSL 1 and the first power supply input of the first write driver WD 1 . The first passgate logic 423 A may include a second transistor T 11 coupled in parallel with the first transistor T 10 between a second voltage source supply VSL 2 and the first power supply input of the first write driver WD 1 . Also, the second passgate logic 434 may include a third transistor T 12 coupled between the first voltage source supply VSL 1 and the second power supply input of the second write driver WD 2 . The second passgate logic 434 may include a fourth transistor T 13 coupled in parallel with the third transistor T 12 between the second voltage source supply VSL 2 and the second power supply input of the second write driver WD 2 . Also, the first voltage source supply VSL 1 may be similar to or different than the second voltage source supply VSL 2 , and in some instances, each of the core arrays 422 A, 422 B may be segmented and/or accessed separately and independently to save power.

In some instances, the gate of the first transistor T 10 and the gate of the third transistor T 12 may receive a first selection signal S 0 from the clock circuitry 430 , and the gate of the second transistor T 11 and the gate of the fourth transistor T 13 may receive a second selection signal S 1 that is complementary to the first selection signal S 0 . Thus, in reference to the first passgate logic 432 , the first transistor T 10 may provide the first voltage source supply VSL 1 to the first power supply input of the first write driver WD 1 when the first transistor T 10 is activated by the first selection signal S 0 , and the second transistor T 11 may provide the second voltage source supply VSL 2 to the first power supply input of the first write driver WD 1 when the second transistor T 11 is activated by the second selection signal S 1 . In reference to the second passgate logic 434 , the third transistor T 12 may provide the first voltage source supply VSL 1 to the second power supply input of the second write driver WD 2 when the third transistor T 12 is activated by the first selection signal S 0 , and the fourth transistor T 13 may provide the second voltage source supply VSL 2 to the second power supply input of the second write driver WD 2 when the fourth transistor T 13 is activated by the second selection signal S 1 .

In some instances, the first voltage source supply (VSL 1 ) is associated with the first part of the core array (Bot_Seg) 422 A, and the first voltage source supply (VSL 1 ) is selected by the first passgate logic 432 when any bitcell (BC) 408 A in the first part of the core array (Bot_Seg) 422 A is accessed. The second voltage source supply (VSL 2 ) is associated with the second part of the core array (Top_Seg) 422 B, and the second voltage source supply (VSL 2 ) is selected by the second passgate logic 434 when any bitcell (BC) 408 B in the second part of the core array (Top_Seg) 422 B is accessed. In this instance, VSL 1 may be associated with the first half of the core array 422 A (e.g., when accessing Bot_Seg of the core array 422 A), and VSL 1 may be selected when any bitcell (BC) 408 A is selected from the bottom portion of the core array 422 A. Also, VSL 2 may be associated with the second half of the core array 422 B (e.g., when accessing Top_Seg of the core array 422 B), and VSL 2 may be selected when any bitcell (BC) 408 B is selected from the top portion of the core array 422 A.

The memory circuitry 400 may be implemented as an integrated circuit (IC) in various types of memory, such as, e.g., random access memory (RAM), including static RAM (SRAM), magneto-resistive RAM (MRAM), and/or any similar memory. The memory circuitry 400 may also be implemented as an IC with single-port memory architecture and related circuitry. The memory circuitry 400 may also be integrated with computing circuitry and related components on a single chip. The memory circuitry 400 may be implemented in various embedded systems for various electronic, mobile and Internet-of-things (IoT) applications, including low power sensor nodes.

FIGS. 5A-5B illustrate other memory circuitry 500 that may utilize write assist schemes and techniques in accordance with some implementations described herein. In particular, FIG. 5A shows a configurational diagram 500 A of the memory circuitry 500 , FIG. 5B shows a configurational diagram 500 B of address decoder 540 .

In some instances, the memory circuitry 500 may be implemented as a system or device having various circuit components that are arranged and/or coupled together as an assemblage or some combination of parts that provide for a physical layout design and related structures. Also, in some instances, a method of designing, providing and building the memory circuitry 500 may involve use of various circuit components described herein so as to implement write assist schemes and techniques associated therewith.

As shown in FIG. 5A , the memory circuitry 500 may include various circuitry, such as, e.g., write assist circuitry 520 coupled to a number (N) of core arrays (e.g., 522 A . . . 522 N). In some instances, the write assist circuitry 520 may also include various circuit components, such as, e.g., passgate logic 532 , 534 and write drivers (WD 1 , WD 2 ), that are coupled to one or more bitlines (BL, NBL). In some instances, as shown in FIG. 5B , the memory circuitry 500 may utilize the address decoder 540 to receive a number (N) of address signals (e.g., A 0 , A 1 , A 2 , . . . , AN) as input clock pulses and provide a number (N) of selection signals (e.g., S 0 , S 1 , S 2 , . . . , SN) as output clock pulses that correspond to the input clock pulses. In SRAM, the bitlines may refer to complementary bitlines (BL, NBL), and in MRAM, the bitlines may refer to a bitline (BL) and a source line (SL).

The memory circuitry 500 may be implemented with multiple core arrays (e.g., 522 A, . . . , 522 N) in various multi-bank configurations, wherein each bank may have an array of memory cells or bitcells (e.g., 508 A, . . . , 508 N). For instance, the core arrays 522 A, . . . , 522 N may begin with a lower bank 422 A or bottom segment (Bot_Seg) and the conclude with an upper bank 522 N or top segment (Top_Seg). It should be appreciated that reference to top and/or bottom may be relative to positional orientation of the memory circuitry 500 . Also, in some instances, the bitlines may have resistance factors associated therewith, wherein, e.g., the bitline BL may have a resistance coefficient factor RBL, and also, the other bitline NBL may have another resistance coefficient factor RNBL.

In some instances, each bitcell may be configured to store at least one data bit value (e.g., a data value related to a logical ‘0’ or ‘1’). The one or more core arrays 522 A, . . . , 522 B include any number of bitcells arranged in various configurations, such as, e.g., two-dimensional (2D) memory arrays having any number of columns and any number of rows of multiple bitcells, which may be arranged in a 2D grid pattern for read and write memory access. Each bitcell may be implemented with any type of memory, including, e.g., SRAM, MRAM, and/or any other type of similar memory. Also, in some instances, each bitcell may include a multi-transistor static RAM (SRAM) cell, including various types of SRAM cells, such as, e.g., any type of complementary MOS (CMOS) SRAM cells, such as, e.g., 4T, 6T, 8T, 10T, or more transistors per bit. In other instances, each bitcell may include a multi-layer MRAM bitcell having free-layers and pinned layers. In SRAM, the bitlines may refer to complementary bitlines (BL, NBL), and in MRAM, the bitlines may refer to a bitline (BL) and a source line (SL).

The write assist circuitry 520 may include passgate logic circuitry, such as, e.g., first passgate logic 532 and second passgate logic 534 . The first passgate logic 532 may include a number (N) of transistors (e.g., T 1 A, . . . , T 1 N) that are coupled in parallel to a power supply input of the write driver (e.g., WD 1 ). The second passgate logic 534 may include a number (N) of transistors (e.g., T 2 A, . . . , T 2 N) that are also coupled in parallel to a power supply input of the other write driver (e.g., WD 2 ). In some configurations, the transistors (T 1 A, . . . , T 1 N and T 2 A, . . . , T 2 N) may be parallel-coupled P-type transistors. However, in other configurations, the transistors (T 1 A, . . . , T 1 N and T 2 A, . . . , T 2 N) may be parallel-coupled N-type transistors. Also, in some instances, the first passgate logic 532 may provide the first voltage (VBL) to the power supply input of the write driver WD 1 , and the second passgate logic 534 may provide the second voltage (VNBL) to the power supply input of the other write driver WD 2 .

In some implementations, the write assist circuitry 520 may include one or more write drivers (WD 1 , WD 2 ) that are coupled to the bitcells 508 A, 508 B via the bitlines (BL, NBL) including, e.g., a first write driver WD 1 coupled to the bitcells 508 A, 508 B via a first bitline BL and a second write driver WD 2 coupled to the bitcells 508 A, 508 B via a second bitline NBL that is complementary to the first bitline BL. In reference to MRAM, the second bitline may refer to a source line (SL). Also, the write assist circuitry 520 may include the first passgate logic 532 coupled to the first power supply input of the first write driver WD 1 , and the write assist circuitry 520 may include the second passgate logic 434 coupled to the second power supply input of the second write driver WD 2 . The write drivers (WD 1 , WD 2 ) may be implemented with inverters (i 2 , i 3 ). The first write driver WD 1 may receive a data signal (D) and provide an output signal to the bitline BL based on the power supply input, and the second write driver WD 2 may receive a complementary data signal (ND) and provide an output signal to the bitline NBL based on the power supply input.

In some instances, the first passgate logic 532 may include a first number (N) of transistors (T 1 A, . . . , T 1 N) that are coupled in parallel between a number (N) of voltage source supplies (VSL 1 , . . . , VSLN) and the first power supply input of the first write driver WD 1 . The second passgate logic 534 may include a second number (N) of transistors (T 2 A, . . . , T 2 N) that are coupled in parallel between the number (N) of voltage source supplies (VSL 1 , . . . , VSLN) and the second power supply input of the second write driver WD 2 . In some instances, each voltage source supply of the number (N) of voltage source supplies (VSL 1 , . . . , VSLN) may be similar to or different than each other voltage source supply of the number (N) of voltage source supplies (VSL 1 , . . . , VSLN). Also, in various instances, each of the core arrays ( 522 A, . . . , 522 N) may be segmented and/or accessed separately and independently to save power.

In various instances, gates of each first transistor (T 1 A, . . . , T 1 N) and gates of each second transistor (T 2 A, . . . , T 2 N) may receive corresponding selection signals (S 0 , . . . , SN) from the address decoder 540 . Thus, in reference to the first passgate logic 532 , each first transistor (T 1 A, . . . , T 1 N) may provide a corresponding voltage source supply (VSL 1 , . . . , VSLN) to the first power supply input of the first write driver WD 1 , when each first transistor (T 1 A, . . . , T 1 N) is activated by its corresponding selection signal (S 0 , . . . , SN). Also, in reference to the second passgate logic 534 , each second transistor (T 2 A, . . . , T 2 N) may provide a corresponding voltage source supply (VSL 1 , . . . , VSLN) to the second power supply input of the second write driver WD 2 , when each second transistor (T 2 A, . . . , T 2 N) is activated by its corresponding selection signal (S 0 , . . . , SN).

The memory circuitry 500 may be implemented as an integrated circuit (IC) in various types of memory, such as, e.g., random access memory (RAM), including static RAM (SRAM), magneto-resistive RAM (MRAM), and/or any similar memory. The memory circuitry 500 may also be implemented as an IC with single-port memory architecture and related circuitry. The memory circuitry 500 may also be integrated with computing circuitry and related components on a single chip. The memory circuitry 500 may be implemented in various embedded systems for various electronic, mobile and Internet-of-things (IoT) applications, including low power sensor nodes.

As shown in FIG. 5B , the memory circuitry 500 may include address decoder circuitry 540 that receives the number (N) of address signals (A 0 , A 1 , A 2 , . . . , AN) and provides the number (N) of selection signals (S 0 , S 1 , S 2 , . . . , SN) that corresponds to the number of address signals (A 0 , A 1 , A 2 , . . . , AN). In some instances, the address decoder circuitry 540 may provide the number (N) of selection signals (S 0 , S 1 , S 2 , . . . , SN) to the first power supply input of the first write driver WD 1 , and the address decoder circuitry 540 may also provide the number (N) of selection signals (S 0 , S 1 , S 2 , . . . , SN) to the second power supply input of the second write driver WD 2 .

In some instances, in reference to FIGS. 5A-5B , each voltage source supply of the number (N) of voltage source supplies (VSL 1 , . . . , VSLN) may be associated with a corresponding segment ( 522 A, . . . , 522 N) of bitcells (BC: 508 A, . . . , 508 N) in the core array. Also, each voltage source supply (VSL 1 , . . . , VSLN) may be selected by the first passgate logic 532 or the second passgate logic 534 when any bitcell in the corresponding segment ( 522 A, . . . , 522 N) of bitcells is accessed. For instance, VSL 1 may be associated with a first segment 522 A of the core array (e.g., when accessing the first segment 522 A of the core array), and VSL 1 may be selected when any bitcell (BC) 508 A is selected from the first segment 522 A of the core array. VSL 2 may be associated with a second segment 522 B of the core array (e.g., when accessing the second segment 522 B of the core array), and VSL 2 may be selected when any bitcell (BC) 508 B is selected from the second segment 522 B of the core array. Lastly, VSLN may be associated with an Nth segment 522 N of the core array (e.g., when accessing the Nth segment 522 N of the core array), and VSLN may be selected when any bitcell (BC) 508 N is selected from the Nth segment 522 N of the core array. Similar associations may be made for numbers C-N.

It should be intended that the subject matter of the claims not be limited to the implementations and illustrations provided herein, but include modified forms of those implementations including portions of implementations and combinations of elements of different implementations in accordance with the claims. It should be appreciated that in the development of any such implementation, as in any engineering or design project, numerous implementation-specific decisions should be made to achieve developers' specific goals, such as compliance with system-related and business related constraints, which may vary from one implementation to another. Moreover, it should be appreciated that such a development effort may be complex and time consuming, but may be referred to as a routine undertaking of design, fabrication, and manufacture for those of ordinary skill in the art having benefit of this disclosure.

Described herein are various implementations of a device. The device may include memory circuitry having a core array of bitcells. The device may include write assist circuitry having passgates coupled to the bitcells via bitlines. The passgates may include a first passgate coupled to the bitcells via a first bitline and a second passgate coupled to the bitcells via a second bitline, and a gate of the second passgate may be coupled to the first bitline.

Described herein are various implementations of a device. The device may include memory circuitry having a core array of bitcells. The device may include write assist circuitry having passgates coupled to the bitcells via bitlines. The passgates may include a first passgate coupled to the bitcells via a first bitline and a second passgate coupled to the bitcells via a second bitline. In some instances, a gate of the first passgate may be coupled to the second bitline, and a gate of the second passgate may be coupled to the first bitline.

Described herein are various implementations of a device. The device may include memory circuitry having a core array of bitcells. The device may include write assist circuitry having write drivers coupled to the bitcells via bitlines including a first write driver coupled to the bitcells via a first bitline and a second write driver coupled to the bitcells via a second bitline that is complementary to the first bitline. The write assist circuitry may include first passgate logic coupled to a first power supply input of the first write driver, and the write assist circuitry may include second passgate logic coupled to a second power supply input of the second write driver.

Reference has been made in detail to various implementations, examples of which are illustrated in the accompanying drawings and figures. In the following detailed description, numerous specific details are set forth to provide a thorough understanding of the disclosure provided herein. However, the disclosure provided herein may be practiced without these specific details. In some other instances, well-known methods, procedures, components, circuits and networks have not been described in detail so as not to unnecessarily obscure details of the embodiments.

It should also be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element. The first element and the second element are both elements, respectively, but they are not to be considered the same element.

The terminology used in the description of the disclosure provided herein is for the purpose of describing particular implementations and is not intended to limit the disclosure provided herein. As used in the description of the disclosure provided herein and appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. The term “and/or” as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items. The terms “includes,” “including,” “comprises,” and/or “comprising,” when used in this specification, specify a presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and/or groups thereof.

As used herein, the term “if” may be construed to mean “when” or “upon” or “in response to determining” or “in response to detecting,” depending on the context. Similarly, the phrase “if it is determined” or “if [a stated condition or event] is detected” may be construed to mean “upon determining” or “in response to determining” or “upon detecting [the stated condition or event]” or “in response to detecting [the stated condition or event],” depending on the context. The terms “up” and “down”; “upper” and “lower”; “upwardly” and “downwardly”; “below” and “above”; and other similar terms indicating relative positions above or below a given point or element may be used in connection with some implementations of various technologies described herein.

While the foregoing is directed to implementations of various techniques described herein, other and further implementations may be devised in accordance with the disclosure herein, which may be determined by the claims that follow.

Although the subject matter has been described in language specific to structural features and/or methodological acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as example forms of implementing the claims.