Amplifier device

This application is a continuation-in-part of application Ser. No. 16/406,026, filed on May 8, 2019, which is a continuation-in-part of application Ser. No. 15/718,079, filed on Sep. 28, 2017, which claims the benefit of Taiwan application No. 105144234, filed on Dec. 30, 2016. The entire contents of the related applications are incorporated herein by reference.

The present disclosure relates to an amplifier device; in particular, to an amplifier device capable of improving linearity.

With the prevalence of mobile devices nowadays, amplifier devices are used in communication modules in great quantity. Due to the fact that the power-gain curve and power-phase curve of an amplifier device tend to be non-linear when they reach a certain level, amplifier devices are limited in power usage. Though the approaches of reducing the power or introducing a pre-distortion circuit may be utilized, the complexity of circuit design and cost would increase correspondingly. Moreover, the linearity of an amplifier device varies according to the input signal, voltage source or temperature, so that if a pre-distortion circuit is utilized as previously described, different control factors need thus be considered, and the circuit design would also become more complicated.

Therefore, providing an amplifier device with simple circuit and capable of self-adjusting linearity becomes a critical issue.

According to one embodiment, an amplifier device comprises an amplifying unit and a bias module. The amplifying unit has a first end coupled to a voltage source configured to receive a source voltage, a second end configured to receive an input signal, and a third end coupled to a first reference potential terminal configured to receive a first reference potential. The first end of the amplifying unit is configured to output an output signal amplified by the amplifying unit. The bias module is coupled to the second end of the amplifying unit, and configured to receive a voltage signal to provide a bias current to the amplifying unit. The voltage signal is a variable voltage. A supply current flowing into the amplifying unit and is adjusted in accordance with the voltage signal to stay within a predetermined range.

FIG. 1 shows a diagram of an amplifier device according to an embodiment of the present disclosure.

FIG. 2 shows a diagram of a first adjusting module and a second adjusting module according to an embodiment of the present disclosure.

FIGS. 3A-3Y show diagrams of an impedance unit implemented by different elements according to the embodiments of the present disclosure.

FIG. 4 shows a diagram of a power-gain curve of an amplifier device.

FIG. 5 shows a diagram of a power-phase curve of an amplifier device.

FIG. 6 shows a diagram of an amplifier device according to another embodiment of the present disclosure.

FIG. 7 is a circuit schematic of a first adjustment module for use in the amplifier device 1 in FIG. 1 .

FIG. 8 depicts a positively correlated relationship between the control voltage and the source voltage.

FIG. 9 is a schematic diagram of a first adjusting module according to another embodiment of the embodiment.

FIG. 10 is a schematic diagram of a first adjusting module according to yet another embodiment of the embodiment.

FIG. 11 depicts a positively correlated relationship and a negatively correlated relationship between the control voltage and the source voltage.

FIG. 12 is a schematic diagram of an amplifier device according to another embodiment of the present disclosure.

FIG. 13 shows a voltage response of a supply current without a compensation.

FIG. 14 depicts a voltage compensation scheme employing a bias current according to an embodiment of the invention.

FIG. 15 is a schematic diagram of the variable current source in FIG. 12 according to an embodiment of the invention.

FIG. 16 is a schematic diagram of the variable current source in FIG. 12 according to another embodiment of the invention.

FIG. 17 is a schematic diagram of an amplifier device according to another embodiment of the invention.

FIG. 18 is a schematic diagram of an amplifier device according to another embodiment of the invention.

FIG. 19 is a schematic diagram of an amplifier device according to another embodiment of the invention.

Below, exemplary embodiments will be described in detail with reference to accompanying drawings so as to be easily realized by a person having ordinary knowledge in the art. The inventive concept may be embodied in various forms without being limited to the exemplary embodiments set forth herein. Descriptions of well-known parts are omitted for clarity, and like reference numerals refer to like elements throughout.

The aforementioned illustrations and following detailed descriptions are exemplary for the purpose of further explaining the scope of the present disclosure. Other objectives and advantages related to the present disclosure will be illustrated in the subsequent descriptions and appended drawings.

Reference is made to FIG. 1 , FIG. 2 and FIGS. 3A-3Y , where FIG. 1 shows a diagram of an amplifier device according to an embodiment of the present disclosure, FIG. 2 shows a diagram of a first adjusting module and a second adjusting module according to an embodiment of the present disclosure, and FIGS. 3A-3Y show diagrams of an impedance unit implemented by different elements according to the embodiments of the present disclosure.

In the following description, for the sake of brevity, for elements with two ends in FIG. 1 and FIG. 2 , the upper end would be the first end and the lower end would be the second end if an element is placed vertically, and the left end would be the first end and the right end would be the second end if an element is placed horizontally. For elements with three or more ends in FIG. 1 and FIG. 2 , reference in the description would be made according to the end number as labeled in the figures.

The amplifier device 1 includes an amplifying unit 11 and a bias module 12 . The amplifying unit 11 includes a first end, a second end and a third end. The first end of the amplifying unit 11 connects to a voltage source Vsource, the second end of the amplifying unit 11 receives an input signal S 1 , the first end of the amplifying unit 11 is configured for outputting an output signal S 2 amplified by the amplifying unit, the third end of the amplifying unit 11 connects to a first reference potential Vref 1 . In the present embodiment, the amplifying unit 11 may be a bipolar junction transistor (BJT), and the voltage source Vsource is provided by a battery, with the voltage value being variable, e.g., time-varying. The amplifier device 1 may be installed in a mobile device (not shown in the figures), and may use the battery of the mobile device to provide the voltage source Vsource. The amplifier device 1 may be, such as, a power amplifier or a low noise amplifier, and a power amplifier is taken as exemplary in the present embodiment. Moreover, the input signal S 1 and the output signal S 2 may be AC signal, such as radio frequency (RF) signal.

The bias module 12 includes a power element 121 , a reference power module 122 , a first bias element 123 , a second bias element 124 and a third bias element 125 . The power element 121 has a first end, a second end and a third end. The first end of the power element 121 electrically connects to a bias voltage source Vbias, the third end of the power element 121 connects to the second end of the amplifying unit 11 . The bias module 12 adjusts a linearity of the amplifier device 1 according to a frequency value of the input signal S 1 , a voltage value of the voltage source Vsource or a temperature value of the amplifier device 1 . In the present embodiment, the bias voltage source Vbias and the voltage source Vsource may or may not have the same potential, and is not limited to either circumstance by the present disclosure.

The first bias element 123 has a first end and a second end. The first end of the first bias element 123 electrically connects to the reference power module 122 , the second end of the first bias element 123 electrically connects to the second end of the power element 121 . The second bias element 124 has a first end and a second end, and the first end of the second bias element 124 electrically connects to the second end of the first bias element 123 . In the present embodiment, the reference power module 122 is a current source which provides a reference current to the first bias element 123 of the bias module 12 . In other embodiments the reference power module 122 may be a voltage source or power modules with other kinds of power supplying.

The third bias element 125 has a first end and a second end, the first end of the third bias element 125 electrically connects to the second end of the second bias element 124 , the second end of the third bias element 125 electrically connects to a second reference potential Vref 2 or other reference potentials, and is not limited by the present disclosure.

In the present embodiment, the amplifier device 1 further includes a first default capacitor 13 , a second default capacitor 14 , an impedance unit 15 and a first adjusting module 16 , so as to adjust the linearity of the amplifier device 1 .

The first default capacitor 13 has a first end and a second end, and the first end of the first default capacitor 13 electrically connects to the bias module 12 . In the present embodiment, the first end of the first default capacitor 13 electrically connects to the second end of the power element 121 , the second end of the first bias element 123 and the first end of the second bias element 124 . The second end of the first default capacitor 13 connects to the impedance unit 15 . The first default capacitor 13 can be used to block DC (direct current) signal.

The second default capacitor 14 has a first end and a second end. The first end of the second default capacitor 14 connects to the first end of the first default capacitor 13 , and the second end of the second default capacitor 14 electrically connects to the second reference potential Vref 2 . The second default capacitor 14 can be used to block DC (direct current) signal.

In the present embodiment, the power element 121 may be, such as a bipolar junction transistor (BJT), the first element 123 is a resistor, and the second bias element 124 and the third bias element 125 are respectively a diode. In the present embodiment, the second bias element 124 and the third bias element 125 may be, but not limited to, a diode composed of a p-type semiconductor or an n-type semiconductor, e.g., a diode composed of bipolar junction transistor (BJT). In other embodiments, the second bias element 124 and the third bias element 125 may be other elements, or be replaced by equivalent circuit such as a metal-oxide-semiconductor field-effect transistor (MOSFET).

In the present embodiment, since the bias module 12 , the second default capacitor 14 and the impedance 15 are often disposed in the same vicinity in circuit design, the second default capacitor 14 , the impedance unit 15 and the third bias element 125 may be all electrically connected to the second reference potential Vref 2 as a common reference potential. In the present embodiment, the first reference potential Vref 1 and the second reference potential Vref 2 may be, but are not limited to, a ground potential or other reference potentials. Moreover, in the present embodiment, the reference power module 122 may be a variable current source, a constant voltage source or a variable voltage source, and current value of a reference current provided by the variable current source or voltage value of a reference voltage provided the variable voltage source may be adjusted according to a frequency value of the input signal S 1 , the voltage value of the voltage source Vsource or a temperature value of the amplifier device 1 , so as to adjust the bias voltage provided by the bias module 12 to the amplifying unit 11 . Comparing to the amplifier device that only has the amplifying unit 11 and the bias module 12 , the second capacitor 14 can be used to change the impedance viewed from the second end of the power element 121 to the external, such as the impedance to the AC signal, and the first default capacitor 13 and the impedance unit 15 can be further used to dynamically adjust the impedance viewed from the second end of the power element 121 to the external of the power element 121 .

In the present embodiment, the impedance value of the impedance unit 15 is variable, and by serially connecting the impedance unit 15 with the first default capacitor 13 , the equivalent impedance resulted from the first default capacitor 13 and the impedance unit 15 can be adjusted. In the present embodiment, the impedance unit 15 may be a variable resistor, a variable capacitor, a variable inductor, a switch or other equivalent circuit or electronic device capable of adjusting impedance value, such as a varactor, or the combination of the above-mentioned elements. The impedance unit 15 further includes an impedance control end Tctrl, which may receive a control signal. In the present embodiment, the amplifier device 1 further includes a first adjusting module 16 , configured to provide a first adjusting signal (e.g., the first adjusting voltage Vcontrol 1 ) to the control end Tctrl of the impedance unit 15 , for adjusting the impedance value of the impedance unit 15 . In other embodiments, the impedance value of the impedance unit 15 may be adjusted according to a frequency value of the input signal S 1 , the voltage value of the voltage source Vsource or the temperature value of the amplifier device 1 .

The first adjusting module 16 includes a first amplifier 160 , a first resistor 161 , a second resistor 162 , a third resistor 163 and a fourth resistor 164 . The first amplifier 160 has a first input end, a second input end and an output end. The first resistor 161 is connected between the first end of the first amplifier 160 and a third reference potential Vref 3 . The second resistor 162 connects the first input end of the first amplifier 160 and the voltage source Vsource. The third resistor 163 is connected between the second input end of the first amplifier 160 and the output end of the first amplifier 160 . The fourth resistor 164 is connected between the first reference voltage Vr 1 and the second input end of the first amplifier 160 . In the present embodiment, the output end of the first amplifier 160 of the first adjusting module 16 outputs a first adjusting voltage Vcontrol 1 to adjust the impedance value of the impedance unit 15 , i.e., the output end of the first amplifier 160 of the first adjusting module 16 electrically connects to the control end Tctrl of the impedance unit 15 . In the present embodiment, the third reference potential Vref 3 is a ground potential, i.e., 0V. In other embodiments, the third reference voltage Vref 3 may be other reference potentials.

In the present embodiment, the first adjusting module is a differential amplifier architecture, thus the first adjusting voltage Vcontrol 1 may be calculated and obtained according to the voltage value of the voltage source, the first reference voltage Vr 1 , the third reference potential Vref 3 , the impedance value of the first resistor 161 , the impedance value of the second resistor 162 , the impedance value of the third resistor 163 and the impedance value of the fourth resistor 164 . In the present embodiment, the third reference potential Vref 3 is 0V, and thus the first adjusting voltage Vcontrol 1 may be represented by the following equation 1:

In the equation above, R 1 is the impedance value of the first resistor 161 , R 2 is the impedance value of the second resistor 162 , R 3 is the impedance value of the third resistor 163 and R 4 is the impedance value of the fourth resistor 164 . Vcontrol 1 represents the first adjusting voltage and Vr 1 represents the first reference voltage.

According to equation 1, if the impedance value of the first resistor 161 equals to the impedance value of the third resistor 163 and the impedance value of the second resistor 162 equals to the impedance value of the fourth resistor 164 , equation 1 may be simplified to equation 2:

In the present embodiment, the first reference voltage Vr 1 is a constant, with only the voltage value of the voltage source being variable, and the impedance values of each resistor are also constant, which means that the first adjusting voltage Vcontrol 1 is a function value of the voltage source Vsource. In other embodiments, other kinds of circuit may be utilized for the design of the first adjusting voltage Vcontrol 1 , so long as the voltage source Vsource is the main variable of the first adjusting voltage Vcontrol 1 .

In the present embodiment, the impedance value of the impedance unit 15 is adjusted according the voltage value of the voltage source Vsource, which means, based on the voltage value of the voltage source Vsource, adjusting the equivalent impedance seen from the third end of the power element 121 to the internal of the power element 121 , and further adjusting the bias voltage provided by the bias module 12 to the amplifying unit 11 . In other embodiments, the impedance value of the impedance unit 15 may be adjusted according to the a frequency value of the input signal S 1 or other parameters, so as to further adjust the bias voltage provided by the bias module 12 to the amplifying unit 11 . For example, a frequency-voltage conversion circuit may first be used to detect the frequency of an input signal, the frequency is then converted into a voltage value, and then the impedance value of the impedance unit 15 may be adjusted by using the voltage value. In other embodiments, the amplifier device 1 may include a temperature sensor (not shown in the figures) for detecting the temperature of the amplifier device 1 . The impedance value of the impedance unit 15 may be adjusted according to the temperature of the amplifier device 1 , so as to further adjust the bias voltage provided by the bias module 12 to the amplifying unit 11 . In summary, in the embodiments of the present disclosure, the equivalent impedance seen from the third end of the power element 121 to the internal of the power element 121 may be adjusted according to the voltage value of the voltage source Vsource, a frequency value of the input signal S 1 and the temperature of the amplifier device 1 .

In the present embodiment, the first adjusting module 16 , based on the variation of the voltage source Vsource, adjusts the impedance value of the impedance unit 15 . Therefore, the impedance seen outwardly from the second end of the power element 121 of the bias module 12 may be adjusted, which effects the equivalent impedance seen from the third end of the power element 121 to the internal of the power element 121 , further adjusts the bias voltage provided bias module 12 to the amplifying unit, and effects the linearity of the power-gain curve or the power-phase curve of the amplifying unit 11 .

In the present embodiment, the impedance unit 15 may be that shown by the diagrams in FIGS. 3A-3Y , and may be, but not limited to, designed by using different resistors, capacitors, inductors, variable resistors, variable capacitors, variable inductors, switch elements (e.g., transistors or diodes), or the combination thereof.

[Embodiment of Amplifier Device With Two Adjusting Modules]

In the present embodiment, the amplifier device 1 further includes a second adjusting module 17 . The second adjusting module 17 includes a second amplifier 170 , a fifth resistor 171 , a sixth resistor 172 , a seventh resistor 173 and an eighth resistor 174 . The second amplifier 170 has a first input end, a second input end and an output end. The fifth resistor 171 is connected between the first input end of the second amplifier 170 and a fourth reference potential Vref 4 . The sixth resistor 172 is connected between the first input end of the second amplifier 170 and the voltage source Vsource. The seventh resistor 173 is connected between the second input end of the second amplifier 170 and the output end of the second amplifier 170 . The eighth resistor is connected between a second reference voltage Vr 2 and the second input end of the second amplifier 170 .

In the present embodiment, the varying interval of the voltage source Vsource is divided into two intervals, which means that the voltage source Vsource has a first voltage interval and a second voltage interval. When the voltage value of the voltage source Vsource is within the first voltage interval, the first adjusting module 16 provides a first adjusting voltage to adjust the impedance value of the impedance unit 15 , and when the voltage value of the voltage source Vsource is within the second voltage interval, the second adjusting module 17 provides a second adjusting signal (e.g., a second adjusting voltage) to adjust the impedance value of the impedance unit 15 . In the present embodiment, both the output end of the first amplifier 160 of the first adjusting module 16 and the output end of the second amplifier 170 of the second adjusting module 170 electrically connect to the control end Tctrl of the impedance unit 15 . In other embodiments, a user may set the first reference voltage Vr 1 and the second reference voltage Vr 2 for the setting of the first voltage interval and the second voltage interval. In the present embodiment, the first adjusting voltage Vcontrol 1 and the second adjusting voltage Vcontrol 2 , as described in the previous paragraph, are both a function value of the voltage source Vsource. In other embodiments, other circuits may be utilized for the design of the first adjusting voltage Vcontrol 1 and the second adjusting voltage Vcontrol 2 , so long as the voltage source Vsource is the main variable of the first adjusting voltage Vcontrol 1 and the second adjusting voltage Vcontrol 2 , the designs thereof not being limited to the above description.

In the present embodiment, the third reference potential Vref 3 and the fourth reference potential Vref 4 may be, but not limited to, a ground potential or other reference potentials.

In other embodiments, the first adjusting voltage Vcontrol 1 of the first adjusting module 16 may electrically connect to the first impedance control end Tctrl 1 as shown in FIG. 3S or FIG. 3T , the second adjusting voltage Vcontrol 2 may electrically connect to the second impedance control and Tctrl 2 as shown in FIG. 3S or FIG. 3T . A designer, by different practical demands, and according to the resistor-capacitor combination as shown in FIG. 3S or FIG. 3T , may select different resistances or capacitances to generate different equivalent impedances.

In other embodiments, the voltage-varying interval of the voltage source Vsource may be divided into more intervals, and the number of the adjusting modules should be increased accordingly to provide adjusting voltages.

Reference is made to FIG. 4 and FIG. 5 , where FIG. 4 shows a diagram of a power-gain curve of an amplifier device and FIG. 5 shows a diagram of a power-phase curve of an amplifier device.

The solid line as shown in FIG. 4 is the power-gain curve of an uncompensated amplifier device. In general, when the power of an uncompensated amplifier device exceeds a predetermined value, the gain curve extends downwardly and nonlinearly as shown in FIG. 4 . After that, if a pre-distortion circuit or other compensation circuit is introduced, it would be shown as the dotted line I and the dotted line II in FIG. 4 , where the dotted line I represents the gain linear area being drawn to higher power after the amplifier device is bias compensated, and when under higher power, the gain curve extends downwardly. The dotted line II represents, after the amplifier device is bias compensated, the linear area of the adjusted gain curve being not only drawn further, but also extended upwardly according to practical demand.

The solid line as shown in FIG. 5 is the power-phase curve of an amplifier device not being bias compensated. As shown in FIG. 5 , when the power is lower, the power-phase curve extends linearly, when the power increases to a predetermined value however, the power-phase curve starts to extend downwardly, and distortion occurs at the output end of the amplifier device. The dotted line III and the dotted line IV in FIG. 5 are the power-phase curve adjusted according to different demands of the amplifier device 1 according to an embodiment of the present disclosure. Therefore, a user may compensate the linearity of the amplifier device 1 according to different factors, so as to increase the linearity of the amplifier device 1 effectively.

Reference is made to FIG. 6 , which shows a diagram of an amplifier device according to another embodiment of the present disclosure. In the present embodiment, the amplifier device 1 as shown in FIG. 6 is similar to the amplifier device 1 as shown in FIG. 1 , one of the differences is that the first bias element 123 of the amplifier device 1 of FIG. 1 is replaced by a first bias element 127 . In the present embodiment, the first bias element 127 may be a variable resistor. The first bias element 127 has a third control end Tctrl 3 electrically connected with the first adjusting module 16 . Furthermore, in the present embodiment, the voltage source Vsource may have a constant voltage value.

In the present embodiment, when the power of the input signal S 1 and the output signal S 2 are changed, or the operation mode of the amplifying unit 11 is adjusted between a high power operation mode and a low power operation mode, a variable current I b , which flows into the second end of the power element 121 of the bias module 12 through the first bias element 127 from the reference power module 122 would be changed. For example, when the operation mode of the amplifying unit 11 is adjusted from the high power operation mode to the low power operation mode, the variable current I b would be decreased. In the meantime, the impedance value of the impedance unit 15 will be adjusted simultaneously in accordance with the corresponding linearity. Therefore, in the present embodiment, the linearity of the frequency-phase curve can be adjusted accordingly. That is to say, in the present embodiment, the variable current of the first bias element 127 and the impedance value of the impedance unit 15 are taken as the main factors of the first adjusted voltage Vcontrol 1 .

Therefore, in the present embodiment, the first adjusting module 16 can, according to the power of the input signal S 1 and the output signal S 2 or the operation mode of the amplifier device, output a first adjusting voltage Vcontrol 1 , and by adjusting the impedance value of the impedance unit 15 over the first control end Tctrl and the third control end Tctrl 3 , and by the variable current I b flows through the first bias element 127 , the linearity of the amplifier device 1 can be adjusted.

In other embodiments such as shown in FIG. 3Y , the impedance unit 15 includes a switch element. When the operation mode of the amplifying unit 11 is changed (e.g., the operation mode of the amplifying unit 11 is adjusted between a high power operation mode and a low power operation mode), the first adjusting module 16 can, according to the operation mode of the amplifier device, outputs the first adjusting voltage Vcontrol 1 corresponding to the operation mode, by controlling the switch element of the impedance unit 15 to be connected or disconnected through the first control end Tctrl 1 and the third control end Tctrl 3 , and the variable current I b passing through the first bias element 127 , an impedance value matching the operation mode can be provided, which further improves the linearity of the amplifier device.

FIG. 7 is a circuit schematic of a first adjustment module 7 for use in the amplifier device 1 in FIG. 1 . The first adjustment module 7 may compensate for a variation in a source voltage Vsource from the voltage source over time. Further, the first adjustment module 7 may compensate for a source voltage Vsource having multiple variations. For example, the first adjustment module 7 may adaptively compensate for a first variation of a source voltage Vsource increasing at a first rate and for a second variation of the source voltage Vsource increasing at a second rate. In particular, the first adjustment module 7 may compensate for the variation in the source voltage Vsource by generating a control voltage Vctrl correlated with the source voltage Vsource and adjusting the impedance unit 15 using the control voltage Vctrl. An adjustment of the impedance unit 15 may result in an adjustment of an input impedance looked out from the second end of the amplifying unit 11 to the bias module 12 and modification of a bias voltage to the amplifying unit 11 , thereby compensating for any voltage shift of the source voltage Vsource over time.

The first adjustment module 7 comprises a first amplifier 70 , a first resistance selection circuit 72 , a second resistance selection circuit 74 , a first feedback resistor 76 and a second feedback resistor 78 . The first amplifier 70 may be an operational amplifier having a first input end, a second input end and an output end, with the first input end being a non-inverting end, the second input end being an inverting end, and the output end outputting the control voltage Vctrl according to the source voltage Vsource and a first reference voltage Vr 3 to adjust the impedance value of the impedance unit. In some embodiments, it is desirable to generate a control voltage Vctrl positively correlated with the source voltage Vsource to compensate for changes in source voltage Vsource during operations of the amplifying unit 11 . FIG. 8 depicts a positively correlated relationship between the control voltage Vctrl and the source voltage Vsource. In such a case, the first resistance selection circuit 72 is electrically connected between the source voltage having the source voltage Vsource and the first input end of the first amplifier 70 , and the second resistance selection circuit 74 is electrically connected between a first reference voltage terminal having the first reference voltage Vr 3 and the second input end of the first amplifier 70 . The first reference voltage Vr 3 may be a bandgap reference voltage that is independent of voltage source variations. The first feedback resistor 76 is electrically connected between the second input end of the first amplifier 70 and the output end of the first amplifier 70 . The second feedback resistor 78 is electrically connected between the second input end of the first amplifier 70 and the first reference potential Vref 4 . The first reference potential Vref 4 may be a ground reference potential. The resistance Res_RF of the second feedback resistor 78 may be set to a multiple of the resistance Res_RF 1 of the first feedback resistor 76 to modify the slope of the line segments 80 and 82 in FIG. 8 . In one embodiment, the first feedback resistor and the second feedback resistor 78 may have substantially identical resistance.

As illustrated in FIG. 8 , the source voltage Vsource may change at a first rate when the source voltage Vsource is less than a threshold value Vt such as 4.5V, and change at a second rate when the source voltage Vsource exceeds the threshold value Vt, and subsequently, in FIG. 7 , the first resistance selection circuit 72 and the second resistance selection circuit 74 may be configured to generate the control voltage Vctrl to compensate for both the first and second rates of changes in the source voltage Vsource. Specifically, the first resistance selection circuit 72 comprises a first transistor M 1 , a resistor R 1 and a resistor R 2 . The first transistor M 1 comprises a first end, a second end and a control end, the first end of the first transistor M 1 is electrically connected to the voltage source having the source voltage Vsource, and the control end of the first transistor M 1 is configured to control an electrical connection between the first end and the second end of the first transistor M 1 according to the source voltage Vsource. The resistor R 1 is electrically connected between the first end and the second end of the first transistor M 1 . The resistor R 2 is electrically connected between the second end of the first transistor M 1 and the first input end of the first amplifier 70 , that is, the resistor R 2 is electrically connected serially with the first transistor M 1 . The second resistance selection circuit 74 comprises a second transistor M 2 , a resistor R 3 and a resistor R 4 . The second transistor M 2 comprises a first end, a second end and a control end, the first end of the second transistor M 2 is electrically connected to the first reference voltage terminal having the first reference voltage Vr 3 , and the control end of the second transistor M 2 is configured to control an electrical connection between the first end and the second end of the second transistor M 2 according to the source voltage Vsource. The resistor R 3 is electrically connected between the first end and the second end of the second transistor M 2 . The resistor R 4 is electrically connected between the second end of the second transistor M 2 and the second input end of the first amplifier 70 , that is, the resistor R 4 is electrically connected serially with the second transistor M 2 . In another embodiment, the resistor R 2 could be moved and electrically connected between the resistor R 1 and the voltage source, and/or the resistor R 4 could be moved and electrically connected between the resistor R 3 and the first reference voltage terminal having the first reference voltage Vr 3 . In one embodiment, the resistor R 1 and the resistor R 3 have substantially identical resistance, and the resistor R 2 and the resistor R 4 have substantially identical resistance. The control voltage Vctrl can be expressed by Equation 3:

V ctrl= k 1*( V source− V r 3 )  Equation 3

where Vr 3 is the first reference voltage; Vsource is the source voltage; k1=Res_RF/(Res 1 +Res 2 )=Res_RF/(Res 3 +Res 4 ) when the first transistor M 1 and the second transistor M 2 are turned off; k1=Res_RF/Res 2 =Res_RF/Res 4 when the first transistor M 1 and the second transistor M 2 are turned on; Res_RF is the resistance of the first feedback resistor 76 ; and Res 1 , Res 2 , Res 3 , Res 4 are the resistances of the resistor R 1 , the resistor R 2 , the resistor R 3 , and the resistor R 4 , respectively.

The slopes k1 of line segments 80 and 82 in FIG. 8 may be controlled by the first transistor M 1 and the second transistor M 2 . When the source voltage Vsource is less than the threshold value Vt, the first transistor M 1 may be turned off to electrically disconnect the first end from the second end of the first transistor M 1 and the second transistor M 2 may be turned off to electrically disconnect the first end from the second end of the second transistor M 2 , and consequently, a total resistance of the resistor R 1 and the resistor R 2 may be the equivalence resistance of the first resistance selection circuit 72 and a total resistance of the resistor R 3 and the resistor R 4 may be the equivalence resistance of the second resistance selection circuit 74 , producing a shallow slope of the line segment 80 in FIG. 8 . When the source voltage Vsource is greater than the threshold value Vt, the first transistor M 1 may be turned on to electrically connect the first end and the second end of the first transistor M 1 and the second transistor M 2 may be turned on to electrically connect the first end and the second end of the second transistor M 2 , and consequently, the resistor R 1 is bypassed and the resistance Res 2 of the second resistor R 2 may be the equivalence resistance of the first resistance selection circuit 72 , the resistor R 3 is bypassed and the resistance Res 4 of the resistor R 4 may be the equivalence resistance of the second resistance selection circuit 74 , producing a steep slope of the line segment 82 in FIG. 8 .

The first adjusting module 7 is not limited to generating a control voltage Vctrl positively correlated to a source voltage Vsource, and can be configured to generate a control voltage Vctrl negatively correlated to a source voltage Vsource by electrically connecting the first reference voltage terminal having the first reference voltage Vr 3 to the first end of the first amplifier 70 via the first resistance selection circuit 72 and electrically connecting the voltage source having the source voltage Vsource to the second end of the first amplifier 70 via the second resistance selection circuit 74 . Generally speaking, the first resistance selection circuit 72 may be electrically connected between the first input end of the first amplifier 70 and one of the voltage source and the first reference voltage terminal having the first reference voltage Vr 3 , and the second resistance selection circuit 74 may be electrically connected between the second input end of the first amplifier 70 and another one of the voltage source and the first reference voltage terminal. When the first resistance selection circuit 72 is electrically connected between the voltage source and the first input end of the first amplifier 70 , and the second resistance selection circuit 74 is electrically connected between the first reference voltage terminal and the second input end of the first amplifier 70 , the first amplifier 70 is configured to generate the control voltage Vctrl positively correlated with the source voltage Vsource. When the first resistance selection circuit 72 is electrically connected between the first reference voltage terminal and the first input end of the first amplifier 70 , and the second resistance selection circuit 74 is electrically connected between the voltage source and the second input end of the first amplifier 70 , the first amplifier 70 is configured to generate the control voltage Vctrl negatively correlated with the source voltage Vsource.

Furthermore, the first adjusting module 7 is not limited to compensation of variations in the source voltage Vsource, and can also be used to compensate for variations in temperature of the amplifier device 1 and power of the output signal. FIG. 9 depicts a schematic diagram of a first adjusting module 9 according to another embodiment of the embodiment. The first adjusting module 9 may compensate for variations in the source voltage Vsource, temperature of the amplifier device 1 and power of the output signal.

The first adjusting module 9 comprises the first amplifier 70 , the first resistance selection circuit 72 , the second resistance selection circuit 74 , the first feedback resistor 76 , the second feedback resistor 78 , and resistors R 5 through R 10 . The configuration and operations of the first amplifier 70 , the first resistance selection circuit 72 , the second resistance selection circuit 74 , the first feedback resistor 76 and the second feedback resistor 78 are identical to those in FIG. 7 , and explanations therefor have been provided in the preceding paragraphs and will be omitted here for brevity. The resistor R 5 is electrically connected between the first input end of the first amplifier 70 and a power input terminal, the power input terminal being configured to receive a power-correlated signal correlating to the power Vdet of the output signal. The resistor R 6 is electrically connected between the second input end of the first amplifier 70 and a second reference voltage terminal having a second reference voltage Vdet 0 . The second reference voltage Vdet 0 may be a reference voltage that is independent of power variations of the output signal. The resistor R 7 is electrically connected between the first input end of the first amplifier 70 and a temperature input terminal, the temperature input terminal being configured to receive a temperature-correlated signal VPTAT correlating to a temperature of the amplifier device 1 . The temperature-correlated signal VPTAT is proportional to absolute temperature (PTAT) signal. The resistor R 8 is electrically connected between the second input end of the first amplifier 70 and a third reference voltage terminal having a third reference voltage VBG. The third reference voltage VBG may be a bandgap reference voltage that is independent of temperature variations. The resistor R 9 is electrically connected between the first input end of the first amplifier 70 and a fourth reference voltage terminal configured to receive a fourth reference voltage Vr 4 . The fourth reference voltage Vr 4 may be a reference voltage that is independent of voltage source variations, temperature variations, and power variations of the output signal. That is, the bias module 12 could be further configured to adjust linearity of the amplifier device 1 according to the power of the output signal and/or the temperature of the amplifier device 1 by using the control voltage Vctrl with the resistors R 5 , R 6 and/or the resistors R 7 , R 8 correspondingly. The resistor R 10 is electrically connected between the second input end of the first amplifier 70 and the first reference potential terminal having the first reference potential Vref 4 . The resistor R 5 and the resistor R 6 may have substantially identical resistance, the resistor R 7 and the resistor R 8 may have substantially identical resistance, and the resistor R 9 and the resistor R 10 may have substantially identical resistance. The control voltage Vctrl output from the first amplifier 70 can be expressed by Equation 4:

V ctrl= k 1*( V source− V r 3 )+ k 2( V det− V det 0 )+ k 3( V PTAT− V BG)+ k 4( V r 4 −0)  Equation 4

where Vr 3 is the first reference voltage; Vsource is the source voltage; k1=Res_RF/(Res 1 +Res 2 )=Res_RF/(Res 3 +Res 4 ) when the first transistor M 1 and the second transistor M 2 are turned off; k1=Res_RF/Res 2 =Res_RF/Res 4 when the first transistor M 1 and the second transistor M 2 are turned on; k2=Res_RF/R 5 =Res_RF/R 6 ; k3=Res_RF/R 7 =Res_RF/R 8 ; k4=Res_RF/R 9 =Res_RF/R 10 ; Res_RF is the resistance of the first feedback resistor 76 ; and Res 1 through Res 10 are the resistances of the resistors R 1 through R 10 , respectively.

FIG. 10 is a schematic diagram of a first adjusting module 10 according to yet another embodiment of the embodiment. The first adjusting module 10 comprises the first amplifier 70 , a first resistance selection circuit 102 , the second resistance selection circuit 104 , the first feedback resistor 76 , the second feedback resistor 78 , and resistors R 5 through R 10 . The configuration and operations of the first amplifier 70 , the first feedback resistor 76 , the second feedback resistor 78 and the resistors R 5 through R 10 are identical to those in FIG. 9 , and explanations therefor have been provided in the preceding paragraphs and will be omitted here for brevity. In some embodiments, it is desirable to compensate for variations of the source voltage Vsource using positively correlated control voltages Vctrl as well as negatively correlated control voltages Vctrl, as depicted by line segments 110 and 112 in FIG. 11 . In such a case, the first adjusting module 10 may configure the first resistance selection circuit 102 and the second resistance selection circuit 104 as required to generate a control voltage Vctrl. More specifically, the first resistance selection circuit 102 may select one of the source voltage Vsource and the first reference voltage Vr 3 , and connect the corresponding terminal of the selected one to the first end of the first amplifier 70 , and similarly, the second resistance selection circuit 104 may select another one of the source voltage Vsource and the first reference voltage Vr 3 , and connect the corresponding terminal of the selected another one to the second end of the first amplifier 70 , thereby generating the control voltages Vctrl.

The first resistance selection circuit 102 comprises a first transistor M 1 , a second transistor M 2 and a resistor R 1 . The first transistor M 1 comprises a first end electrically connected to the voltage source having the source voltage Vsource, a second end and a control end. The second transistor M 2 comprises a first end electrically connected to the first reference voltage terminal having the first reference voltage Vr 3 , a second end electrically connected to the second end of the first transistor M 1 , and a control end. The resistor R 1 is electrically connected between the second end of the first transistor M 1 and the first input end of the first amplifier 70 . The second resistance selection circuit 104 comprises a third transistor M 3 , a fourth transistor M 4 and a resistor R 2 . The third transistor M 3 comprises a first end electrically connected to the voltage source having the source voltage Vsource, a second end, and a control end electrically connected to the control end of the second transistor M 2 . The fourth transistor M 4 comprises a first end electrically connected to the first reference voltage terminal having the first reference voltage Vr 3 , a second end electrically connected to the second end of the third transistor M 3 , and a control end electrically connected to the control end of the first transistor M 1 . The second resistor R 2 is electrically connected between the second end of the third transistor M 3 and the second input end of the first amplifier 70 . The transistors M 1 though M 4 may be BJT or FET, such as N-type or P-type metal-oxide semiconductor field-effect transistors (MOSFET). The transistors M 1 and M 4 are turned on or off simultaneously, and the transistors M 2 and M 3 are turned on or off simultaneously.

The transistors M 1 and M 2 operate in anti-phase, and the transistors M 3 and M 4 operate in anti-phase. When the first transistor M 1 and the fourth transistor M 4 are turned on, and the second transistor M 2 and the third transistor M 3 are turned off, the first amplifier 70 may generate the control voltage Vctrl positively correlated with the source voltage Vsource. When the first transistor M 1 and the fourth transistor M 4 are turned off, and the second transistor M 2 and the third transistor M 3 are turned on, the first amplifier 70 may generate the control voltage Vctrl negatively correlated with the source voltage Vsource. The control voltage Vctrl can be expressed by Equation 5:

V ctrl= k 1*( V source− V r 3 )+ k 2( V det− V det 0 )+ k 3( V PTAT− V BG)+ k 4( V r 4 −0)  Equation 5

where Vr 3 is the first reference voltage; Vsource is the source voltage; k1=Res_RF/Res 1 for the positively correlated control voltage Vctrl, and k1=−Res_RF/Res 1 for the negatively correlated control voltage Vctrl k2=Res_RF/R 5 =Res_RF/R 6 ; k3=Res_RF/R 7 =Res_RF/R 8 ; k4=Res_RF/R 9 =Res_RF/R 10 ; Res_RF is the resistance of the first feedback resistor 76 ; and Res 1 through Res 10 are the resistance of the resistors R 1 through R 10 , respectively.

The first adjusting modules 7 , 9 and 10 may generate a control voltage Vctrl to compensate for variations in the source voltage Vsource of the amplifying unit 1 , temperature of the amplifier device 1 and/or power of the output signal, thereby maintaining linearity of the amplifier device 1 .

FIG. 12 is a schematic diagram of an amplifier device 2 according to another embodiment of the present disclosure. The amplifier device 2 comprises the amplifying unit 11 and the bias module 12 . The amplifying unit 11 may draw a supply current Icc from the voltage source 24 receiving a source voltage Vsource. The source voltage Vsource is a time-varying voltage. As the source voltage Vsource varies with time, the supply current Icc varies accordingly. FIG. 13 shows a voltage response of a supply current Icc without a compensation, with the horizontal axis representing the source voltage Vsource in volts and the vertical axis representing the supply current Icc in milliamperes. A line 130 represents an ideal supply current Icc, a line 132 represents a real supply current Icc, and lines 134 and 136 represent first and second approximations of the real supply current Icc. In one embodiment, the source voltage Vsource may vary from 5.5V to 3.2V over time, and the amplifying unit 11 may operate over the range of the source voltage Vsource. Ideally, the supply current Icc should be maintained substantially at 140 mA, as indicated by the line 130 . In practice, the supply current Icc may vary between 120 mA and 160 mA, as indicated by the line 132 . For the source voltage Vsource ranging between 3.2V and 4.7V, the line 132 may be approximated by the line 134 , and for the source voltage Vsource ranging between 4.7V and 5.5V, the line 132 may be approximated by the line 136 . The lines 134 and 136 may have a first gradient and a second gradient, respectively.

FIG. 14 depicts a voltage compensation scheme employing a bias current Ibias according to an embodiment of the invention. Line segments 140 and 142 represent the bias current Ibias generated by the bias module 12 for the source voltage Vsource less than and exceeding a threshold value, respectively. The threshold value may be selected substantially at the voltage where the lines 134 and 136 in FIG. 13 intersect with each other, e.g., 4.7V. The line segments 140 and 142 show that the bias current Ibias are negatively correlated to the source voltage Vsource in FIG. 13 . Further, the line segment 140 has a first counter-gradient corresponding to the first gradient of the line 134 in FIG. 13 , and the line segment 142 has a second counter-gradient corresponding to the second gradient of the line 136 in FIG. 13 . The first counter-gradient may be negatively correlated to the first gradient, and the second counter-gradient may be negatively correlated to the second gradient. The amplifier device 2 may compensate for variations of the source voltage Vsource over time by adjusting the bias current Ibias according to the line segments 140 and 142 , thereby maintaining the amplifying unit 11 to operate substantially at a constant supply current, e.g., 140 mA, and enhancing the performance of the amplifier device 2 . In some embodiments, for the source voltage Vsource less than 4.7V, the bias module 12 may adjust the bias current Ibias according to the line segment 140 , and for the source voltage Vsource exceeding 4.7V, the bias module 12 may adjust the bias current Ibias according to the line segment 142 . In some embodiments, the amplifier device 2 may compensate for the variations of the source voltage Vsource according to the line segment 140 or the line segment 142 .

Although only two lines 134 and 136 are used to approximate the real supply current Icc (line 132 ) in FIG. 13 , those in the art would appreciate that more than two approximation lines may be used to approximate the real supply current Icc, and accordingly, more than two corresponding lines negatively correlated to the more than two approximation lines may be used to simulate the bias current Ibias over the desired operating range, and two or more threshold values may be used to determine which of the more than two corresponding lines may be used to simulate the bias current Ibias to compensate for variations of the source voltage Vsource. The counter-gradients of lines simulating the bias current Ibias and the threshold value (s) are not limited to the example provided in FIG. 14 , and may be selected based on actual applications and design requirements.

Referring to FIG. 12 , the amplifying unit 11 has a first end coupled to the voltage source 24 configured to receive the source voltage Vsource, and the supply current ICC flowing into the first end of the amplifying unit 11 , a second end configured to receive an input signal S 1 , and a third end coupled to a first reference potential terminal 20 . The amplifying unit 11 may be a BJT, and may serve as a power amplifier or a low noise amplifier. The amplifying unit 11 may be biased by the bias current Ibias to amplify the input signal S 1 , so as to output an output signal S 2 amplified by the amplifying unit 11 at the first end of the amplifying unit 11 . The first reference potential terminal 20 may receive a first reference potential Vref 1 . The first reference potential Vref 1 may be a ground reference potential or other reference potentials.

The bias module 12 may be coupled to the second end of the amplifying unit 11 , and may receive a voltage signal VCC 1 to provide the bias current Ibias to the amplifying unit 11 . The voltage signal VCC 1 may be substantially positively correlated to the time-varying source voltage Vsource, and therefore, the voltage signal VCC 1 may also be a time-varying variable voltage. In some embodiments, the voltage signal VCC 1 may be a fraction of the source voltage Vsource, and may be derived from the source voltage Vsource using a voltage divider, where VCC 1 =Vsource*K, and K may be 0.5. In other embodiments, the voltage signal VCC 1 may be substantially identical to the source voltage Vsource.

Since the voltage signal VCC 1 is substantially positively correlated to the source voltage Vsource, and the bias current Ibias represented by the line segments 140 and 142 in FIG. 14 is negatively correlated to the voltage signal VCC 1 , the bias module 12 may adjust the bias current Ibias according to the voltage signal VCC 1 . A decrease of the source voltage Vsource will result in an increase of the bias current Ibias, and consequently, an increase of the supply current Icc. Conversely, an increase of the source voltage Vsource will result in a decrease of the bias current Ibias, and consequently, a decrease of the supply current Icc. In this manner, variations of the supply current Icc owing to the variations of the source voltage Vsource may be compensated, and the supply current Icc may be adjusted in accordance with the voltage signal VCC 1 to stay within a predetermined range, e.g., within ±3% of 140 mA.

The bias module 12 may comprise a variable current source 1200 . In some embodiments, the variable current source 1200 may be a variable resistor configured to adjust the bias current Ibias according to the voltage signal VCC 1 . In other embodiments, as illustrated in FIG. 15 , the variable current source 1200 may comprise signal terminals 151 , 153 , a reference potential terminal 155 , an operational amplifier OP, a first resistance selection circuit 152 , a second resistance selection circuit 154 , resistors Rp 1 , Rn 1 , RF, RF 1 , a voltage-to-current converter 156 and switch control terminals 157 , 158 . In some embodiments, the resistance of the resistor Rn 1 may be adjusted to selectively remove the resistor RF 1 from the variable current source 1200 . The variable current source 1200 may receive the voltage signal VCC 1 and a reference signal VBG 2 to generate the bias current Ibias according to the line segments 140 and 142 in FIG. 14 . The reference signal VBG 2 may be a bandgap reference voltage or any other reference voltage that is substantially fixed with respect to the source voltage Vsource variations.

The operational amplifier OP may have a first input end, a second input end and an output end, with the first input end being a non-inverting end, the second input end being an inverting end, and the output end outputting an output voltage Vo. The first input end of the operational amplifier OP may be coupled to the signal terminal 151 and receive the reference signal VBG 2 , and the second input end of the operational amplifier OP may be coupled to the signal terminal 153 and receive the voltage signal VCC 1 . The output end of the operational amplifier OP may output the output voltage Vo according to a difference between the reference signal VBG 2 and the voltage signal VCC 1 . In other embodiments, the operational amplifier OP may be an adder.

The voltage-to-current convertor 156 may comprise a first end coupled to the output end of the operational amplifier OP, and a second end coupled to the second end of the amplifying unit 11 . The voltage-to-current convertor 156 may convert the output voltage Vo into the bias current Ibias, and may be a MOSFET, a BJT, or other types of transistors.

The resistor RF may comprise a first end coupled to the second input end of the operational amplifier OP, and a second end coupled to the output end of the operational amplifier OP. The resistor RF 1 may comprise a first end coupled to the first end of the resistor RF, and a second end coupled to the reference potential terminal 155 receiving a reference potential Vref 5 . The reference potential Vref 5 may be a ground reference potential or other reference potentials. In some embodiments, the reference potential Vref 5 and the first reference potential Vref 1 may have substantially identical reference potentials. In some embodiments, the resistors RF, RF 1 may have substantially identical resistance. In some embodiments, the resistors RF, RF 1 may be variable. In some embodiments, the resistance of the resistor RF 1 may be set as a multiple of the resistance of the resistor RF to modify the gradients of the line segments 140 and 142 in FIG. 14 .

The resistor Rp 1 may comprise a first end coupled to the signal terminal 151 via the first resistance selection circuit 152 , and a second end coupled to the first input end of the operational amplifier OP. The resistor Rn 1 may comprise a first end coupled to the signal terminal 153 via the second resistance selection circuit 154 , and a second end coupled to the second input end of the operational amplifier OP. The resistors Rp 1 , Rn 1 may be variable. The first resistance selection circuit 152 may comprise a first end coupled to the signal terminal 151 , and a second end coupled to the first end of the resistor Rp 1 . The second resistance selection circuit 154 may comprise a first end coupled to the signal terminal 153 , and a second end coupled to the first end of the resistor Rn 1 . The first resistance selection circuit 152 may comprise a switch SW 1 and a resistor Rp 2 . The switch SW 1 may comprise a first end coupled to the first end of the first resistance selection circuit 152 , a second end coupled to the second end of the first resistance selection circuit 152 , and a control end coupled to the switch control terminal 157 . The switch control terminal 157 may receive a first control signal to turn on or turn off the switch SW 1 . The resistor Rp 2 may be coupled between the first end of the switch SW 1 and the second end of the switch SW 1 . The second resistor selection circuit 154 may comprise a switch SW 2 and a resistor Rn 2 . The switch SW 2 may comprise a first end coupled to the first end of the second resistor selection circuit 154 , a second end coupled to the second end of the second resistor selection circuit 154 , and a control end coupled to the switch control terminal 158 . The switch control terminal 158 may receive a second control signal to turn on or turn off the switch SW 2 . The resistor Rn 2 may be coupled between the first end of the switch SW 2 and the second end of the switch SW 2 . The switches SW 1 and SW 2 may be MOSFET, BJT, or other types of transistors. The resistors Rp 2 , Rn 2 may be variable. The resistors Rp 1 , Rn 1 may have substantially identical resistance, and the resistors Rp 2 , Rn 2 may have substantially identical resistance. In some embodiments, the resistor Rp 1 and the first resistance selection circuit 152 may be swapped in place, that is, the first end of the resistor Rp 1 may be coupled to the signal terminal 151 , the second end of the resistor Rp 1 may be coupled to the first end of the first resistance selection circuit 152 , and the second end of the first resistance selection circuit 152 may be coupled to the first input end of the operational amplifier OP. Similarly, the resistor Rn 1 and the second resistance selection circuit 154 may be swapped in place, that is, the first end of the resistor Rn 1 may be coupled to the signal terminal 153 , the second end of the resistor Rn 1 may be coupled to the first end of the second resistance selection circuit 154 , and the second end of the second resistance selection circuit 154 may be coupled to the second input end of the operational amplifier OP.

The first resistance selection circuit 152 and the second resistor selection circuit 154 may be used to adjust a rate of change of the output voltage Vo and/or the bias current Ibias with respect to the difference of the reference signal VBG 2 and the voltage signal VCC 1 . Specifically, the switches SW 1 and SW 2 are turned on or off together to switch between the rates of change of the output voltage Vo and/or the bias current Ibias. The output voltage Vo can be expressed by Equation 6:

V o= k 1*( V BG 2 − VCC 1 )  Equation 6

where VBG 2 is the reference signal independent of source voltage variations; VCC 1 is the voltage signal; k1=Res_RF/(Res_Rp 1 +Res_Rp 2 )=Res_RF/(Res_Rn 1 +Res_Rn 2 ) when the switch SW 1 and the switch SW 2 are turned off; k1=Res_RF/Res_Rp 1 =Res_RF/Res_Rn 1 when the switch SW 1 and the switch SW 2 are turned on; and Res_RF, Res_Rp 1 , Res_Rn 1 , Res_Rp 2 , Res_Rn 2 are the resistances of the resistors RF, Rp 1 , Rn 1 , Rp 2 , Rn 2 , respectively.

The output voltage Vo may be determined by a difference (VBG 2 −VCC 1 ) and a gradient k1. Since the reference signal VBG 2 is independent of source voltage variations and the voltage signal VCC 1 is positively correlated to the source voltage Vsource, an increase of the source voltage Vsource will lead to a decrease of the difference (VBG 2 −VCC 1 ), and subsequently, a decrease of the output voltage Vo; and a decrease of the source voltage Vsource will lead to an increase of the difference (VBG 2 −VCC 1 ), and subsequently, an increase of the output voltage Vo. In this manner, the variations of the source voltage Vsource may be compensated to provide a substantially constant supply current Icc to the amplifying unit 11 .

Referring to FIG. 14 , the first counter-gradient of the line segment 140 and the second counter-gradient of the line segment 142 may be realized by the variable current source 1200 using the first resistance selection circuit 152 and the second resistor selection circuit 154 . When the source voltage Vsource is less than the threshold value, the switch SW 1 may be turned off to electrically disconnect the first end from the second end of the switch SW 1 , and the switch SW 2 may be turned off to electrically disconnect the first end from the second end of the switch SW 2 , and consequently, a total resistance (Res_Rp 1 +Res_Rp 2 ) of the resistor Rp 1 and the resistor Rp 2 and a total resistance (Res_Rn 1 +Res_Rn 2 ) of the resistor Rn 1 and the resistor Rn 2 may be used to produce a gentler gradient k1, e.g., the first counter-gradient of the line segment 140 . When the source voltage Vsource exceeds the threshold value, the switch SW 1 may be turned on to electrically connect the first end and the second end of the switch SW 1 , and the switch SW 2 may be turned on to electrically connect the first end and the second end of the switch SW 2 , and consequently, the resistance Res_Rp 1 of the resistor Rp 1 and the resistance Res_Rn 1 of the resistor Rn 1 may be used to produce a steeper gradient k1, e.g., the second counter-gradient of the line segment 142 . In some embodiments, one line having a single counter-gradient is used to simulate the bias current Ibias, the first resistance selection circuit 152 and the second resistor selection circuit 154 may be omitted from the variable current source 1200 . In some embodiments, the first resistance selection circuit 152 , the second resistor selection circuit 154 , and the resistors Rp 1 , Rn 1 may be removed from the variable current source 1200 and included in an external circuit other than the variable current source 1200 .

The variable current source 1200 is not limited to providing a bias current Ibias negatively correlated to the source voltage Vsource, and can be configured to provide a bias current Ibias positively correlated to the source voltage Vsource by swapping places of the first resistance selection circuit 152 and the resistor Rp 1 with the second resistance selection circuit 154 and the resistor Rn 1 . That is, sequentially connecting the first resistance selection circuit 152 and the resistor Rp 1 between the signal terminal 153 and the second input end of the operational amplifier OP, and sequentially connecting the second resistance selection circuit 154 and the resistor Rn 1 between the signal terminal 151 and the first input end of the operational amplifier OP. In such a configuration, the variable current source 1200 may generate the bias current Ibias positively correlated with the source voltage Vsource.

Furthermore, the variable current source 1200 is not limited to compensation for source voltage variations, and can also be used to compensate for temperature variations and signal power variations, as illustrated in FIG. 16 , in which a schematic diagram of a variable current source 1200 according to another embodiment is provided. The variable current source 1200 comprises the signal terminals 151 , 153 , the reference potential terminal 155 , the operational amplifier OP, the first resistance selection circuit 152 , the second resistance selection circuit 154 , the resistors Rp 1 , Rn 1 , RF, RF 1 , the voltage-to-current converter 156 , the switch control terminals 157 , 158 , resistors Rp 3 to Rp 6 , Rn 3 to Rn 6 , signal terminals 1601 to 1607 and a reference potential terminal 1608 . The variable current source 1200 may generate the bias current Ibias to compensate for source voltage variations, power variations of the input signal or the output signal, ambient temperature variations, and/or temperature variations of the amplifying unit. The configuration and operations of the operational amplifier OP, the first resistance selection circuit 152 , the second resistance selection circuit 154 , the resistors Rp 1 , Rn 1 , RF, RF 1 are identical to those in FIG. 15 , and explanations therefor have been provided in the preceding paragraphs and will be omitted here for brevity. In some embodiments, the resistance of the resistors Rn 1 , Rn 3 , Rn 4 , Rn 5 , Rn 6 or a combination thereof may be adjusted to selectively remove the resistor RF 1 from the variable current source 1200 .

The resistor Rp 3 may comprise a first end coupled to the signal terminal 1601 to receive a power signal Vdet 2 , and a second end coupled to the first input end of the operational amplifier OP. The resistor Rn 3 may comprise a first end coupled to the signal terminal 1602 to receive a reference signal Vdet 02 , and a second end coupled to the second input end of the operational amplifier OP. The power signal Vdet 2 may represent power of the input signal S 1 or the output signal S 2 . The reference signal Vdet 02 may be a reference voltage that is substantially fixed with respect to power variations of the input signal S 1 or the output signal S 2 .

The resistor Rp 4 may comprise a first end coupled to the signal terminal 1603 to receive a temperature signal VPTAT 2 , and a second end coupled to the first input end of the operational amplifier OP. The resistor Rn 4 may comprise a first end coupled to the signal terminal 1604 to receive a reference signal VBG 3 , and a second end coupled to the second input end of the operational amplifier OP. The temperature signal VPTAT 2 may be a proportional to absolute temperature (PTAT) signal. In some embodiments, a complementary to absolute temperature (CTAT) signal may also be employed for the temperature compensation. In the case of using the CTAT signal, the first end of the resistor Rp 4 may be configured to receive the reference signal VBG 3 via the signal terminal 1603 , and the first end of the resistor Rn 4 may be configured to receive the CTAT signal via the signal terminal 1604 . The reference signal VBG 3 may be a bandgap reference voltage that is substantially fixed with respect to temperature variations, and may be substantially identical to the reference signal VBG 2 . In some embodiments, the temperature signal VPTAT 2 and the reference signal VBG 3 may be generated from circuits on the same die of an integrated circuit (IC).

The resistor Rp 5 may comprise a first end coupled to the signal terminal 1605 to receive a temperature signal VD 0 , and a second end coupled to the first input end of the operational amplifier OP. The resistor Rn 5 may comprise a first end coupled to the signal terminal 1606 to receive a temperature signal Vat, and a second end coupled to the second input end of the operational amplifier OP. The temperature signal VD 0 may present a temperature on an IC that contains the amplifying unit 11 , indicating an ambient temperature. The temperature signal Vat may represent a temperature at a location close to the amplifying unit 11 , indicating a temperature of the amplifying unit 11 . In some embodiments, the temperature signal Vat and the temperature signal VD 0 may be generated from temperature detection circuits on the same die of an IC. In another embodiments, the temperature signal Vat and the temperature signal VD 0 may be generated by separate temperature detection circuits on different dies of an IC. Specifically, the temperature detection circuit for generating the temperature signal Vat and the amplifying unit 11 may be arranged on a die, and the temperature detection circuit for generating the temperature signal VD 0 may be arranged on another die and away from the amplifying unit 11 .

The resistor Rp 6 may comprise a first end coupled to the signal terminal 1607 to receive a reference signal Vr 5 , and a second end coupled to the first input end of the operational amplifier OP. The resistor Rn 6 may comprise a first end coupled to the reference potential terminal 1608 to receive the reference potential Vref 5 , and a second end coupled to the second input end of the operational amplifier OP. The reference signal Vr 5 may be a reference voltage that is substantially fixed with respect to source voltage variations.

The resistors Rp 3 to Rp 6 , Rn 3 to Rn 6 may be variable. The resistors Rp 3 and Rn 3 may have substantially identical resistance, the resistors Rp 4 and Rn 4 may have substantially identical resistance, the resistors Rp 5 and Rn 5 may have substantially identical resistance, and the resistors Rp 6 and Rn 6 may have substantially identical resistance. The output voltage Vo can be expressed by Equation 7:

V o= k 1*( V BG 2 − V CC 1 )+ k 2( V det 2 − V det 02 )+ k 3( V PTAT 2 − V BG 3 )+ k 4( V r 5 − V ref 5 )+ k 5( V D 0 − V at)  Equation 7

where VBG 2 is the reference signal independent of source voltage variations; VCC 1 is the voltage signal; Vdet 2 is the power signal; Vdet 02 is the reference signal independent of power variations of the input signal or the output signal; VPTAT 2 is the temperature signal; VBG 3 is the reference signal independent of temperature variations; Vr 5 is the reference signal independent of source voltage variations; Vref 5 is the reference potential; VD 0 is the temperature signal; Vat is the temperature signal; k1=Res_RF/(Res_Rp 1 +Res_Rp 2 )=Res_RF/(Res_Rn 1 +Res_Rn 2 ) when the switch SW 1 and the switch SW 2 are turned off; k1=Res_RF/Res_Rp 1 =Res_RF/Res_Rn 1 when the switch SW 1 and the switch SW 2 are turned on; k2=Res_RF/Res_Rp 3 =Res_RF/Res_Rn 3 ; k3=Res_RF/Res_Rp 4 =Res_RF/Res_Rn 4 ; k4=Res_RF/Res_Rp 6 =Res_RF/Res_Rn 6 ; k5=Res_RF/Res_Rp 5 =Res_RF/Res_Rn 5 ; and Res_RF, Res_Rp 1 to Res_Rp 6 , Res_Rn 1 to Res Rn 6 are the resistances of the resistors RF, Rp 1 to Rp 6 , Rn 1 to Rn 6 , respectively.

The output voltage Vo may be determined by the difference (VBG 2 −VCC 1 ) and the gradient k1, a difference (Vdet 2 −Vdet 02 ) and a gradient k2, a difference (VPTAT 2 −VBG 3 ) and a gradient k3, a difference (Vr 5 −Vref 5 ) and a gradient k4, and a difference (VD 0 −Vat) and a gradient k5. The difference (VBG 2 −VCC 1 ) and the gradient k1 have been explained in the preceding paragraph, and explanation therefore will be omitted here.

The linearity of the amplifying unit 11 may vary with the power of the input signal S 1 or the output signal S 2 measured by the power signal Vdet 2 . The difference (Vdet 2 −Vdet 02 ) may represent quantities of power variations and may be used to compensate for the power variations. The output end of the operational amplifier OP may further output the output voltage Vo according to the power signal Vdet 2 and the reference signal Vdet 02 . Consequently, the bias module 12 may adjust the bias current Ibias in accordance with the power of the input signal S 1 or the power of the output signal S 2 . In some embodiments, the bias current Ibias may be increased as the power of the input signal S 1 or the output signal S 2 increases, and decreased as the power of the input signal S 1 or the output signal S 2 decreases, thereby maintaining the linearity of the amplifying unit 11 and enhancing the efficiency of the amplifying unit 11 .

The gain of the amplifying unit 11 may vary with the ambient temperature measured by the temperature signal VPTAT 2 . Specifically, the gain of the amplifying unit 11 may be decreased with an increase of the ambient temperature, and increased with a decrease of the ambient temperature. The difference (VPTAT 2 −VBG 3 ) may represent quantities of ambient temperature variations and may be used to compensate for the ambient temperature variations. The output end of the operational amplifier OP may further output the output voltage Vo according to the temperature signal VPTAT 2 and the reference signal VBG 3 . Consequently, the bias module 12 may adjust the bias current Ibias and control the gain of the amplifying unit 11 to stay within a predetermined gain range, e.g., ±2 dB of a specific gain of the amplifying unit 11 . For example, the gain of the amplifying unit 11 may be adjusted to 28 dB at a high temperature, and to 32 dB at a low temperature, maintaining the gain of the amplifying unit 11 within 30 dB±2 dB over the range of temperature variations.

The gain of the amplifying unit 11 may vary with the temperature of the amplifying unit 11 measured by the temperature signal Vat. For example, the temperature of the amplifying unit 11 may increase with the operating time, resulting in a decrease of the gain. The difference (VD 0 −Vat) may represent quantities of variations between ambient temperatures and amplifying unit temperatures and may be used to compensate for the amplifying unit temperature variations. The output end of the operational amplifier OP may further output the output voltage Vo according to the temperature signal VD 0 and the temperature signal Vat. Consequently, the bias module 12 may adjust the bias current Ibias and control the gain of the amplifying unit 11 to stay within a predetermined gain range, e.g., ±0.2 dB of a specific gain of the amplifying unit 11 . For example, after the amplifying unit 11 operates for a while, the amplifying unit temperature may gradually rise, the gain of the amplifying unit 11 may be adjusted to 29.8 dB or 30.2 dB, maintaining gain of the amplifying unit 11 within 30 dB±0.2 dB.

The difference (Vr 5 −Vref 5 ) may represent a base quantity for generating the bias current Ibias, i.e., a base value of the bias current Ibias to properly bias the amplifying unit 11 at an operating point. The output end of the operational amplifier OP may further output the output voltage Vo according to the reference signal Vr 5 and the reference potential Vref 5 . Consequently, the bias module 12 may adjust the bias current Ibias. In some embodiments, the signal terminals 1607 , the reference potential terminal 1608 and the resistors Rp 6 and Rn 6 may be removed from the variable current source 1200 . The base value of the bias current Ibias may be provided by another bias current generation circuit.

Although only one possible gradient value is implemented for each of the gradients k2, k3, k4, k5 in FIG. 16 , two or more gradients values may be achieved for each of the gradients k2, k3, k4, k5 by adopting a circuit configuration similar to the first resistance selection circuit 152 and the second resistance selection circuit 154 of the FIG. 15 .

The variable current source 1200 in FIGS. 15 and 16 may generate a bias current Ibias to compensate for the source voltage variations, the input/output signal power variations, the ambient temperature variations, and/or the amplifying unit temperature variations, thereby enhancing the performance of the amplifier device 2 .

Further, in some embodiments, rather than adopting the exact circuit configuration of the variable current source 1200 in FIG. 16 , the circuit configuration in FIG. 16 may be adapted based on actual applications and design requirements to compensate for one or a selected combination of the input/output signal power variations, the ambient temperature variations and the amplifying unit temperature variations on top of the source voltage variations. In some embodiments, the first resistance selection circuit 152 , the second resistor selection circuit 154 , and the resistors Rp 1 , Rp 3 to Rp 6 , Rn 1 , Rn 3 to Rn 6 may be removed from the variable current source 1200 and included in an external circuit other than the variable current source 1200 .

FIG. 17 is a schematic diagram of the amplifier device 2 according to another embodiment of the invention. The bias module 12 may comprise the variable current source 1200 and a transistor 1201 . The transistor 1201 may comprise a first end coupled to a bias voltage source 190 , a second end coupled to the variable current source 1200 , and a third end coupled to the second end of the amplifying unit 11 . The bias voltage source 190 may receive a supply voltage V 1 . The variable current source 1200 may be implemented by the embodiments in FIGS. 15 and 16 . In some embodiments, the transistor 1201 may be a MOSFET, a BJT, or other types of transistors.

FIG. 18 is a schematic diagram of the amplifier device 2 according to another embodiment of the invention. The bias module 12 may comprise the transistor 1201 , the variable current source 1200 , a resistor 1203 and diodes 1204 , 1205 . The configurations of the transistor 1201 and the variable current source 1200 are identical to those in FIG. 17 , and explanation therefore will be omitted for brevity. The resistor 1203 may comprise a first end coupled to the variable current source 1200 , and a second end coupled to the second end of the transistor 1201 . The diode 1204 may comprise a first end coupled to the second end of the resistor 1203 , and a second end. The diode 1205 may comprise a first end coupled to the second end of the diode 1204 , and the second end coupled to a reference potential terminal 30 . The reference potential terminal 30 may receive the reference potential Vref 5 . In some embodiments, the diodes 1204 , 1205 may be diode connected transistors.

FIG. 19 is a schematic diagram of the amplifier device 2 according to another embodiment of the invention. The bias module 12 may comprise the transistor 1201 , the variable current source 1200 , the resistor 1203 , a transistor 1206 and a resistor 1207 . The configurations of the transistor 1201 , the variable current source 1200 , and the resistor 1203 are identical to those in FIG. 18 , and explanation therefore will be omitted for brevity. The resistor 1207 may comprise a first end, and a second end coupled to the third end of the transistor 1201 . The transistor 1206 may comprise a first end coupled to the second end of the resistor 1203 , a second end coupled to the first end of the resistor 1207 , and a third end coupled to the reference potential terminal 30 . The reference potential terminal 30 may receive the reference potential Vref 5 . In some embodiments, the transistor 1206 may be a MOSFET, a BJT, or other types of transistors.

The amplifier devices 2 in FIGS. 12 and 17 to 19 employ the variable current source 1200 in FIGS. 15 and 16 may generate a bias current Ibias to compensate for the source voltage variations, input or output signal power variations, ambient temperature variations, and/or amplifying unit temperature variations, thereby enhancing the performance of the amplifier devices 2 . In some embodiments, the reference power module 122 in FIGS. 1 and 6 may be implemented by the variable current sources 1200 in FIGS. 15 and 16 .

The amplifier devices as provided in some of the preset disclosure are capable of output adjustment for bias modules according to different linearity factors, and are capable of bias compensation for amplifier devices according to the voltage value of a voltage source, the frequency value of an input signal or a temperature value. The other amplifier devices as provided in some of the preset disclosure are capable of impedance adjustment according to a power of the input signal, a power of the output signal or an operation mode of the amplifying unit. Therefore, the linearity or the tendency of the power-gain curve or the power-phase curve of an amplifier device may be adjusted accordingly to meet with practical demands. Furthermore, the other amplifier devices as provided in some of the preset disclosure are capable of bias current adjustment for bias modules according to different various factors, and are capable of source voltage compensation, signal power compensation, ambient temperature compensation, and/or the amplifying unit temperature compensation for amplifier devices, thereby enhancing the performance of the amplifier devices.

The descriptions illustrated supra set forth simply the preferred embodiments of the present disclosure; however, the characteristics of the present disclosure are by no means restricted thereto. All changes, alterations, or modifications conveniently considered by those skilled in the art are deemed to be encompassed within the scope of the present disclosure delineated by the following claims.

Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.