Level conversion device and method

This application is a continuation of the U.S. application Ser. No. 16/410,886, filed May 13, 2019, now U.S. Pat. No. 10,483,950, issued Nov. 19, 2019, which is a continuation of the U.S. application Ser. No. 16/219,525, filed Dec. 13, 2018, now U.S. Pat. No. 10,291,210, issued on May 14, 2019, which is a continuation of U.S. application Ser. No. 15/851,403, filed Dec. 21, 2017, now U.S. Pat. No 10,164,615, issued Dec. 25, 2018, which is a continuation of U.S. application Ser. No. 14/942,909, filed Nov. 16, 2015, now U.S. Pat. No. 9,866,205, issued Jan. 9, 2018, all of which are herein incorporated by reference.

With rapid development of manufacturing process technology, low power design has been widely utilized in many applications. For example, level shifters are generally used to interface voltage signals between diversely different circuits that operate with different power voltages from each other. However, when operating at a lower power voltage, for example, a sub-threshold voltage, the operations of the level shifter are failed due to leakage currents.

Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

FIG. 1 is a schematic diagram of a device, in accordance with various embodiments of the present disclosure;

FIG. 2 is a circuit diagram of the device in FIG. 1 , in accordance with various embodiments of the present disclosure;

FIG. 3 is a flow chart of operations of the device in FIG. 2 when the input signal VIN has a logic value of 1, in accordance with various embodiments of the present disclosure;

FIG. 4 is a flow chart of operations of the device in FIG. 2 when the input signal VIN has a logic value of 0, in accordance with various embodiments of the present disclosure;

FIG. 5 is a circuit diagram of the device in FIG. 1 , in accordance with various embodiments of the present disclosure;

FIG. 6 is a circuit diagram of the device in FIG. 1 , in accordance with various embodiments of the present disclosure;

FIG. 7 is a circuit diagram of the device in FIG. 1 , in accordance with various embodiments of the present disclosure;

FIG. 8 is a circuit diagram of the device in FIG. 1 , in accordance with various embodiments of the present disclosure;

FIG. 9 is a circuit diagram of the device in FIG. 1 , in accordance with various embodiments of the present disclosure; and

FIG. 10 is a circuit diagram of the device in FIG. 1 , in accordance with various embodiments of the present disclosure.

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

The terms used in this specification generally have their ordinary meanings in the art and in the specific context where each term is used. The use of examples in this specification, including examples of any terms discussed herein, is illustrative only, and in no way limits the scope and meaning of the disclosure or of any exemplified term. Likewise, the present disclosure is not limited to various embodiments given in this specification.

Although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the embodiments. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.

FIG. 1 is a schematic diagram of a device 100 , in accordance with various embodiments of the present disclosure. In some embodiments, the device 100 is implemented in a level converter or as a level converter.

As illustratively shown in FIG. 1 , the device 100 includes an input signal generator 120 , a level shifter 140 , a selector 160 , and an output stage 180 . For illustration, the input signal generator 120 includes an inverter 120 A. The input signal generator 120 is configured to input an input signal VIN, and further output an input signal VINB, by the inverter 120 A, in response to the input signal VIN. In other words, in some embodiments, the input signal VIN is an inverse of the input signal VINB. In some embodiments, the input signal VINB is a phase shift of the input signal VIN. In some embodiments, the input signal VINB is generated by a logical or arithmetical operations of the input signal VIN.

The level shifter 140 is configured to adjust the voltage level of the input signal VIN to generate an output signal VO 1 and an output signal VO 2 . For illustration, the maximum voltage of the voltage level of the input signal VIN is set to a voltage VDDI. The level shifter 140 is able to adjust the maximum voltage of the input signal VIN from the voltage VDDI to a voltage VDDO, in which the voltage VDDO is different from the voltage VDDI.

The selector 160 is configured to transmit one of the output signal VO 1 and the output signal VO 2 to the output stage 180 according to the input signals VIN and VINB. The output stage 180 is configured to adjust the voltage swing of the one of the output signal VO 1 and the output signal VO 2 transmitted from the selector 160 , in order to generate an output signal VO 4 . In some embodiments, the output stage 180 includes one or more buffers that pull the voltage swing of one of the output signals VO 1 and VO 2 to full range, to generate the output signal VO 4 . Effectively, the driving ability of the device 100 is increased by the output stage 180 . For illustration, the full range of the voltage swing is configured from a voltage VSS which is, for example, a ground voltage, to the voltage VDDO which is, for example, a power voltage.

In some embodiments, the input signal generator 120 operates with the voltage VDDI, while the level shifter 140 , the selector 160 , and the output stage 180 operate with the voltage VDDO. In some embodiments, the voltage VDDI is lower than or equal to the voltage VDDO. For example, the voltage VDDI ranges from about 0.2 Volts to about 1.2 Volts, and the voltage ranges VDDO is about 1.2 Volts. Alternatively, in some other embodiments, the voltage VDDI is higher than or equal to the voltage VDDO. For example, the voltage VDDI is about 1.2 Volts, and the voltage VDDO ranges from about 0.2 Volts to about 1.2 Volts. In other words, in some embodiments, the level shifter 140 is able to pull up the voltage level of the input signal VIN to a higher voltage. Alternatively, in some embodiments, the level shifter 140 is able to pull down the voltage level of the input signal VIN to a lower voltage.

The arrangements of the voltage VDDI and the voltage VDDO are given for illustrative purposes. Various arrangements of the voltage VDDI and the voltage VDDO are within the contemplated scope of the present disclosure.

Reference is now made to FIG. 2 . FIG. 2 is a circuit diagram of the device 100 in FIG. 1 , in accordance with various embodiments of the present disclosure.

In some embodiments, the level shifter 140 includes switches M 1 -M 4 and current limiters 141 and 142 . The level shifter 140 generates the output signal VO 1 at a first terminal of the current limiter 141 , and generates the output signal VO 2 at a second terminal of the current limiter 141 .

For illustration, a first terminal of the switch M 1 is configured to receive the voltage VDDO, a second terminal of the switch M 1 is coupled to the first terminal of the current limiter 141 , and a control terminal of the switch M 1 is coupled to a second terminal of the current limiter 142 and receives a control signal VC. A first terminal of the switch M 2 is coupled to the second terminal of the current limiter 141 , a second terminal of the switch M 2 is configured to receive the voltage VSS, and a control terminal of the switch M 2 is configured to receive the input signal VIN. A first terminal of the switch M 3 is configured to receive the voltage VDDO, a second terminal of the switch M 3 is coupled to a first terminal of the current limiter 142 , and a control terminal of the switch M 3 is coupled to the second terminal of the current limiter 141 to receive the output signal VO 2 . A first terminal of the switch M 4 is coupled to the second terminal of the current limiter 142 , a second terminal of the switch M 4 is configured to receive the voltage VSS, and a control terminal of the switch M 4 is configured to receive the input signal VINB. In some embodiments, the voltage VSS is lower than the voltage VDDO.

In some embodiments, the switches M 1 and M 3 operate as pulling-up units of the level shifter 140 . For illustration, when the switch M 1 is turned on by the control signal VC, the voltage level of the first terminal of the current limiter 141 is thus pulled up to the voltage VDDO through the switch M 1 . Accordingly, the first terminal of the current limiter 141 generates the output signal VO 1 corresponding to the pulled up voltage level. When the switch M 3 is turned on by the output signal VO 2 , the voltage level of the first terminal of the current limiter 142 is pulled up to the voltage VDDO through the switch M 3 .

Corresponding to the switches M 1 and M 3 , the switches M 2 and M 4 operate as pulling-down units of the level shifter 140 . For illustration, when the switch M 2 is turned on by the input signal VIN, the voltage level of the second terminal of the current limiter 141 is pulled down to the voltage VSS through the switch M 2 . When the switch M 4 is turned on by the input signal VINB, the voltage level of the second terminal of the current limiter 142 is pulled down to the voltage VSS. Accordingly, the second terminal of the current limiter 142 generates the control signal VC corresponding to the pulled down voltage level.

With the arrangements for the switches M 1 -M 4 , a self-control mechanism is implemented in the level shifter 140 . Detailed operations are described below with reference to FIG. 3 and FIG. 4 .

In some approaches without using the current limiters 141 and 142 , when the input signal VIN is a sub-threshold voltage having, for example, a voltage level of about 0.2 Volts, the switch M 1 and the switch M 2 are turned on at the same time. In such a condition, if a current IM 1 flowing from the switch M 1 to the switch M 2 is greater than a current IM 2 flowing through the switch M 2 , the pulling-down operation of the switch M 2 is failed. Effectively, the operations of the level shifter 140 are failed. Based on the above, the device in these approaches cannot be operated with a sub-threshold voltage.

Compared with the aforementioned approaches, in some embodiments, the current limiter 141 is utilized to reduce the current IM 1 flowing from the switch M 1 to the switch M 2 , and the current limiter 142 is utilized to reduce a current IM 3 flowing from the switch M 3 to the switch M 4 . Alternatively stated, the current limiter 141 is configured to generate a voltage drop between the switches M 1 and M 2 , in which the voltage drop is sufficient to reduce the current IM 1 . The current limiter 142 is configured to generate a voltage drop between the switches M 3 and M 4 , in which the voltage drop is sufficient to reduce the current IM 3 . With such arrangements, the switch M 2 is able to pull down the voltage level of the second terminal of the current limiter 141 to the voltage VSS when the input signal VIN is a low voltage, for example, the sub-threshold voltage.

In some embodiments, the current limiter 141 and the current limiter 142 are resistive devices. In various embodiments, the current limiter 141 and the current limiter 142 are diodes. In further embodiments, the diodes for implementing the current limiter 141 and the current limiter 142 are formed with various types of transistors. For illustration, as shown in FIG. 2 , the current limiter 141 includes a diode-connected metal-oxide-silicon field-effect transistor (MOSFET) M 5 , and the current limiter 142 includes a diode-connected MOSFET M 6 . Effectively, the diode-connected MOSFET M 5 provides the voltage drop, i.e., the threshold voltage of the diode-connected MOSFET M 5 , between the switches M 1 and M 2 . The diode-connected MOSFET M 6 also provides a voltage drop, i.e., the threshold voltage of the diode-connected MOSFET M 6 , between the switches M 3 and M 4 . As a result, the current IM 1 flowing toward the switch M 2 and the current IM 3 flowing toward the switch M 4 are reduced.

The configurations of the current limiters 141 and 142 are given for illustrative purposes. Various configurations of the current limiters 141 and 142 are within the contemplated scope of the present disclosure.

With continued reference to FIG. 2 , in some embodiments, the selector 160 includes switches M 7 and M 8 . The switch M 7 is coupled between the first terminal of the current limiter 141 and the output stage 180 . The switch M 7 is configured to be turned on according to the input signal VIN, to transmit the output signal VO 1 from the first terminal of the current limiter 141 to the output stage 180 . The switch M 8 is coupled between the second terminal of the current limiter 141 and the output stage 180 . The switch M 8 is configured to be turned on according to the input signal VIN, to transmit the output signal VO 2 from the second terminal of the current limiter 141 to the output stage 180 .

Reference is now made to both of FIG. 2 and FIG. 3 . FIG. 3 is a flow chart 300 of operations of the device 100 in FIG. 2 when the input signal VIN has a logic value of 1, in accordance with various embodiments of the present disclosure.

In various embodiments, the input signal VIN is able to have a logic value of 1 or 0. As shown in FIG. 3 , operations of the device 100 in FIG. 2 are described with respect to the input signal VIN having a logic value of 1.

In operation S 310 , the switch M 2 is turned on by the input signal VIN. In operation S 320 , the voltage level of the second terminal of the MOSFET M 5 is pulled down to the voltage VSS. Accordingly, the output signal VO 2 corresponding to the pulled down voltage level of the second terminal of the MOSFET M 5 is generated. In operation S 330 , the switch M 8 is turned on by the input signal VIN to transmit the output signal VO 2 to the output stage 180 . In operation S 340 , the output stage 180 outputs the output signal VO 4 in response to the output signal VO 2 .

In some embodiments, the voltage swing of the input signals VIN and VINB ranges from the voltage VSS to the voltage VDDI, in which the voltage VSS corresponds to the logic value of 0, and the voltage VDDI corresponds to the logic value of 1. For illustration, as shown in FIG. 2 , when the input signal VIN has the logic value of 1, the input signal VINB accordingly has the logic value of 0. The switch M 2 is thus turned on by the input signal VIN. Accordingly, the voltage level of the second terminal of the MOSFET M 5 is pulled down to the voltage VSS, in order to generate the output signal VO 2 having the level of the voltage VSS. The voltage level of the first terminal of the MOSFET M 5 is then transited to the voltage VSS+VTH 5 through the diode-connected MOSFET M 5 , in which VTH 5 is a threshold voltage of the MOSFET M 5 . Furthermore, the switch M 8 is turned on by the input signal VIN to transmit the output signal VO 2 to the output stage 180 . The output stage 180 generates the output signal VO 4 having the logic value of 1 according to the output signal VO 2 .

As described above, in the operations S 310 -S 340 illustrated above, the diode-connected MOSFET M 5 provides a voltage drop i.e., the threshold voltage of the MOSFET M 5 , between the switches M 1 and M 2 . In other words, the diode-connected MOSFET M 5 effectively operate as a resistive device between the switches M 1 and M 2 , to provide a resistance to reduce the current flowing from the switch M 5 to the switch M 2 , compared to the approaches using no current limiter. With such arrangements, the current IM 1 flowing from the switch M 1 to the switch M 2 is reduced. As a result, the pulling down operation of the switch M 2 is able to be performed with a sub-threshold voltage.

Reference is now made to both of FIG. 2 and FIG. 4 . FIG. 4 is a flow chart 400 of operations of the device 100 in FIG. 2 when the input signal VIN has the logic value of 0, in accordance with various embodiments of the present disclosure.

Alternatively, as shown in FIG. 4 , operations of the device 100 in FIG. 2 are described with the input signal VIN having the logic value of 0. In operation S 410 , the switch M 2 is turned off by the input signal VIN. In operation S 420 , the switch M 4 is turned on by the input signal VINB. In operation S 430 , the voltage level of the second terminal of the MOSFET M 6 is pulled to the voltage VSS, to generate the control signal VC. In operation S 440 , the switch M 1 is turned on by the control signal VC. In operation S 450 , the voltage level of the first terminal of the MOSFET M 5 is pulled up to the voltage VDDO. Accordingly, the output signal VO 1 corresponding to the pulled up voltage level of the second terminal of the MOSFET M 5 is generated. In operation S 460 , the switch M 7 is turned on by the input signal VIN to transmit the output signal VO 1 to the output stage 180 . In operation S 470 , the output stage 180 outputs the output signal VO 4 in response to the output signal VO 1 .

For illustration, as shown in FIG. 2 , when the input signal VIN has the logic value of 0, the input signal VINB accordingly has the logic value of 1. The switch M 2 is thus turned off by the input signal VIN. The switch M 4 is thus turned on by the input signal VINB, to transmit the voltage VSS to the second terminal of the MOSFET M 6 . Accordingly, the voltage level of the second terminal of the MOSFET M 6 is pulled down to the voltage VSS, to generate the control signal VC. The switch M 1 is turned on by the control signal VC. Accordingly, the voltage level of the first terminal of the MOSFET M 5 is pulled up to the voltage VDDO, to generate the output signal VO 1 having the level of the voltage VDDO. The voltage level of the second terminal of the MOSFET M 5 is then transited to the voltage VDDO-VTH 5 . The switch M 7 is also turned on by the input signal VIN, to transmit the output signal VO 1 to the output stage 180 . As a result, the output stage 180 generates the output signal VO 4 having the logic value of 0 according to the output signal VO 2 .

It is noted that, in the operations S 410 -S 470 illustrated above, the diode-connected MOSFET M 6 provides a voltage drop, i.e., a threshold voltage of the MOSFET M 6 , between the switches M 3 and M 4 . In other words, the diode-connected MOSFET M 6 effectively operates as a resistive device between the switches M 3 and M 4 , to provide a resistance to reduce the current flowing from the switch M 6 to the switch M 2 . With such arrangement, the current IM 3 flowing from the switch M 3 to the switch M 4 is reduced. As a result, the pulling down operation of the switch M 4 is able to be performed with a sub-threshold voltage.

In some embodiments, the operations illustrated in the flow chart 300 in FIG. 3 and the operations illustrated in the flow chart 400 in FIG. 4 are implemented as a level conversion method.

Reference is now made to FIG. 5 . FIG. 5 is a circuit diagram of the device 100 in FIG. 1 , in accordance with various embodiments of the present disclosure.

Compared with the device 100 in FIG. 2 , like elements in FIG. 5 are designated with the same reference numbers for ease of understanding. In some embodiments illustrated in FIG. 5 , the input signal generator 120 of the device 100 further includes an NAND gate 120 B. An output terminal of the NAND gate 120 B is coupled to an input terminal of the inverter 120 A. In some embodiments, the NAND gate 120 B operates as an enabling unit of the input signal generator 120 . For illustration, the NAND gate 120 B is configured to receive an initial input signal IN and an enable signal EN, and output the input signal VINB to the inverter 120 A according to the initial input signal IN and the enable signal EN. The inverter 120 A is further configured to output the input signal VIN according to the input signal VINB.

When the initial input signal IN and the enable signal EN both have the logic value of 1, the input signal VINB has the logic value of 0. Accordingly, the input signal VIN has the logic value of 1. With such arrangements, the level shifter 140 is enabled to perform the level conversion for the input signal VIN, as discussed above, when the enable signal EN has the logic value of 1.

When the initial input signal IN has the logic value of 1 and the enable signal EN has the logic value of 0, the device 100 is disabled. In such a condition, the NAND gate 120 B outputs the input signal VINB having the logic value of 1. The inverter 120 A then outputs the input signal VIN having the logic value of 0. Accordingly, the switch M 7 is turned on by the input signal VIN, to transmit the output signal VO 1 having the logic value of 1 to the output stage 180 , as discussed above in FIG. 4 . As a result, the output stage 180 receives the output signal VO 1 having the logic value of 1 and outputs the output signal VO 4 having the logic value of 0. In other words, when the device 100 is disabled, the device 100 keeps outputting the output signal VO 4 having the logic value of 0, instead of outputting a floating voltage.

In some embodiments, the NAND gate 120 B and the inverter 120 A operate with the voltage VDDI. In other words, both of the maximum voltage level of the input signals VIN and VINB and the maximum voltage level of the enable signal EN are set to the voltage VDDI.

Reference is now made to FIG. 6 . FIG. 6 is a circuit diagram of the device 100 in FIG. 1 , in accordance with various embodiments of the present disclosure.

Compared with the device 100 in FIG. 2 , like elements in FIG. 6 are designated with the same reference numbers for ease of understanding. In some embodiments illustrated in FIG. 6 , the input signal generator 120 of the device 100 further includes an NOR gate 120 C. An output terminal of the NOR gate 120 C is coupled to an input terminal of the inverter 120 A. In some embodiments, the NOR gate 120 C operates as an enabling unit of the input signal generator 120 . For illustration, the NOR gate 120 C is configured to receive the initial input signal IN and an enable signal ENB, and accordingly output the input signal VINB to the inverter 120 A. The inverter 120 A is configured to output the input signal VIN according to the input signal VINB. In some embodiments, the NOR gate 120 C and the inverter 120 A operate with the voltage VDDI.

Furthermore, compared with the device 100 in FIG. 5 , in some embodiments illustrated in FIG. 6 , the device 100 is enabled when the enable signal ENB has the logic value of 0. When the enable signal ENB has the logic value of 1, the NOR gate 120 C outputs the input signal VINB having the logic value of 0. The inverter 120 A thus generates the input signal VIN having the logic value of 1. As a result, the output stage 180 outputs the output signal VO 4 having the logic value of 1. In other words, when the device 100 is disabled, the device 100 keeps outputting the output signal VO 4 having the logic value of 1, instead of outputting a floating voltage.

The arrangements of the input signal generator 120 in FIGS. 5-6 are given for illustrative purposes. Various arrangements of the input signal generator 120 are within the contemplated scope of the present disclosure.

Reference is now made to FIG. 7 . FIG. 7 is a circuit diagram of the device 100 in FIG. 1 , in accordance with various embodiments of the present disclosure.

Compared with the device 100 in FIG. 2 , like elements in FIG. 7 are designated with the same reference numbers for ease of understanding. In some embodiments illustrated in FIG. 7 , the level shifter 140 further includes a switch M 9 . A first terminal of the switch M 9 is coupled to the second terminals of the switches M 2 and M 4 , a second terminal of the switch M 9 is configured to receive the voltage VSS, and a control terminal of the switch M 9 is configured to receive the enable signal EN. The switch M 9 is configured to be turned on according to the enable signal EN, so as to enable the switches M 1 -M 6 . In other words, in some embodiments, the switch M 9 operates as an enabling unit of the level shifter 140 .

Furthermore, compared with FIG. 2 , in some embodiments illustrated in FIG. 7 , the output stage 180 of the device 100 includes a buffer 182 , a control circuit 184 , and a buffer 186 . An input terminal of the buffer 182 is coupled to the selector 160 to receive one of the output signal VO 1 and the output signal VO 2 . The buffer 182 then outputs an output signal VO 3 according to the one of the output signal VO 1 and the output signal VO 2 . The control circuit 184 is coupled between the buffers 182 and 186 . The control circuit 184 is configured to output a buffer signal VB according to the output signal VO 3 and the enable signal EN. The buffer 186 is configured to output signal VO 4 according to the buffer signal VB. In some embodiments, the control circuit 184 includes an NAND gate 184 A. For illustration, as shown in FIG. 7 , when the enable signal EN has the logic value of 1, the switch M 9 is turned on to enable the switches M 1 -M 6 . In such condition, the logic value of the buffer signal VB is determined by the output signal VO 3 , as discussed above in FIGS. 3-4 . When the output signal VO 3 has the logic value of 1, the buffer signal VB has the logic value of 0. Alternatively, when the output signal VO 3 has the logic value of 0, the buffer signal VB has the logic value of 1. When the enable signal EN has the logic value of 0, the switch M 9 is turned off, and the switches M 1 -M 6 are also turned off. Effectively, the level shifter 140 is disabled. In such condition, the NAND gate 184 A outputs the buffer signal VB having the logic value of 1. As a result, the buffer 186 accordingly outputs the output level of the logic value of 0. With such arrangements, when the level shifter 140 is disabled, the device 100 keeps outputting the output signal VO 4 having the value of 0, instead of outputting a floating voltage.

In some embodiments, the switch M 9 and the output stage 180 operate with the voltage VDDO. In other words, the maximum voltage level of the enable signal EN is set to the voltage VDDO.

Reference is now made to FIG. 8 . FIG. 8 is a circuit diagram of the device 100 in FIG. 1 , in accordance with various embodiments of the present disclosure.

Compared with the device 100 in FIG. 7 , like elements in FIG. 8 are designated with the same reference numbers for ease of understanding. In some embodiments illustrated in FIG. 8 , the switch M 10 of the device 100 is coupled to the switches M 1 and M 3 . In some embodiments, the first terminal of the switch M 10 is configured to receive the voltage VDDO, the second terminal of the switch M 10 is coupled to both of the first terminals of the switches M 1 and M 3 , and the control terminal of the switch M 10 is configured to receive the enable signal ENB. The switch M 10 is configured to be turned on according to the enable signal ENB to enable the switches M 1 -M 6 . In some embodiments, the enable signal ENB is an inverse of the enable signal EN. For illustration, when the enable signal EN has the value of 1, the enable signal ENB has the value of 0. In such condition, the switch M 10 is turned on to enable the switches M 1 -M 6 . The logic value of the buffer signal VB is determined according the one of the output signal VO 1 and the output signal VO 2 transmitted from the level shifter 140 . Alternatively, when the enable signal EN has the logic value of 0, the enable signal ENB has the logic value of 1. In such condition, the switch M 9 is turned off. Effectively, the level shifter 140 is disabled. As a result, the NAND gate 184 A outputs the buffer signal VB having the logic value of 1, and the buffer 186 keeps outputting the output signal VO 4 having the logic value of 0.

Reference is now made to FIG. 9 . FIG. 9 is a circuit diagram of the device 100 in FIG. 1 , in accordance with various embodiments of the present disclosure.

Compared with the device 100 in FIG. 7 , like elements in FIG. 9 are designated with the same reference numbers for ease of understanding. In some embodiments illustrated in FIG. 9 , the control circuit 184 is coupled to an output terminal of the selector 160 and the buffer 182 . The control circuit 184 is configured to transmit the voltage VDDO to the buffer 182 according to the enable signal EN. The buffer 182 is configured to receive one of the output signals VO 1 and VO 2 , and the voltage VDDO, and accordingly output the output signal VO 3 . The buffer 186 is coupled to the buffer 182 to receive the output signal VO 3 , and outputs the output signal VO 4 in response to the output signal VO 3 .

In some embodiments, the control circuit 184 includes a switch M 11 . A first terminal of the switch M 11 is configured to receive the voltage VDDO, a second terminal of the switch M 11 is coupled to the selector 160 to receive one of the output signals VO 1 and VO 2 , and a control terminal of the switch M 11 is configured to receive the enable signal EN. For illustration, when the enable signal has the logic value of 1, the switch M 9 is turned on, and the switch M 11 is turned off. Accordingly, the switches M 1 -M 6 are enabled. As a result, the logic value of the output signal VO 4 is determined according to the input signal VIN, as discussed above in FIGS. 3-4 . Alternatively, when the enable signal EN has the logic value of 0, the switch M 9 is turned off to disable the switches M 1 -M 6 . In such condition, the switch M 11 is turned on by the enable signal EN, to transmit the voltage VDDO to the buffer 182 . Effectively, the buffer 182 receives a signal having the logic value of 1. As a result, the buffer 186 outputs the output signal VO 4 having the logic value of 1. With such arrangements, when the level shifter 140 is disabled, the device 100 keeps outputting the output signal VO 4 having the logic value of 1, instead of outputting a floating voltage.

Reference is now made to FIG. 10 . FIG. 10 is a circuit diagram of the device 100 in FIG. 1 , in accordance with various embodiments of the present disclosure.

Compared to the device 100 in FIG. 8 and FIG. 9 , like elements in FIG. 10 are designated with the same reference numbers for ease of understanding. In some embodiments illustrated in FIG. 10 , the control circuit 184 is coupled to an output terminal of the selector 160 and the buffer 182 . The arrangement of the control circuit 184 in FIG. 10 is same as the arrangement of the control circuit 184 in FIG. 9 . Thus, the related descriptions are not repeated here.

For illustration, as shown in FIG. 10 , when the enable signal EN has the logic value of 1, the enable signal ENB has the logic value of 0. Accordingly, the switch M 10 is turned on by the enable signal ENB, and the switch M 11 is turned off by the enable signal EN. As a result, the switches M 1 -M 6 are enabled, and the logic value of the output signal VO 4 is determined according to the input signal VIN, as discussed above in FIGS. 3-4 . Alternatively, when the enable signal EN has the logic value of 0, the enable signal ENB has the logic value of 1. Accordingly, the switch M 10 is turned off by the enable signal ENB to disable the switches M 1 -M 6 , and the switch M 11 is turned on by the enable signal EN to transmit the voltage VDDO to the buffer 182 . As a result, the buffer 186 outputs the output signal VO 4 having the logic value of 1.

As described above, the device 100 in the present disclosure is able to convert the sub-threshold voltage to a standard supply voltage for low-voltage circuits and systems. Moreover, the device 100 in the present disclosure is also able to convert the standard supply voltage the sub-threshold voltage according to practical applications. In other words, the device 100 in the present disclosure is able to operate with a wide voltage operation range.

In this document, the term “coupled” may also be termed as “electrically coupled,” and the term “connected” may be termed as “electrically connected”. “Coupled” and “connected” may also be used to indicate that two or more elements cooperate or interact with each other.

In some embodiments, a device is disclosed that includes a level shifter and an output stage. The level shifter is configured to generate a first output signal based on a logic value of a first input signal. The output stage configured to receive the first output signal transmitted according to the logic value of the first input signal, and to generate a second output signal. The second output signal has a logic value that is different from a logic value of the first output signal, and the second output signal and the first input signal has a same logic value.

Also disclosed is a device that includes a first switch, a second switch, and a level shifter. A first terminal of the first switch and a first terminal of the second switch are coupled at a first node. A second terminal of the first switch is coupled to a first output terminal of the level shifter, and a second terminal of the second switch is coupled to a second output terminal of the level shifter. One of the first switch and the second switch is configured to be turned on, in response to a first input signal received at control terminals of the first switch and the second switch, to output a first output signal at the first node. The level shifter is configured to output, in response to the first input signal and a second input signal, a second output signal to the first switch or a third output signal to the second switch. The first output signal, the second input signal, and the second output signal have a same logic value.

Also disclosed is a method that includes the operation below: adjusting, by a level shifter, a voltage level of an input signal to generate a first output signal having a first logic value and a second output signal having a second logic value different from the first logic value at two terminals of the level shifter, respectively; and generating, by an output stage, a third output signal according to the first output signal or the second output signal, in which the third output signal has a same logic value that is the same as a logic value of the first output signal or the second output signal.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.