Rectifier capable of adjusting gate voltage of transistor and alternator including rectifier

This application claims the priority benefit of Taiwan application serial no. 108133129, filed on Sep. 12, 2019. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.

The disclosure relates to an alternator and a rectifier, and particularly relates to a rectifier capable of adjusting a gate voltage of a rectifier transistor.

In an alternator, a rectifier is often used to rectify an alternating current (AC) input voltage and generate a rectified voltage that may be regarded as a direct current (DC) voltage. According to the related art, the input voltage is often rectified by switching on or off a diode or a transistor. However, when the alternator does not generate electricity, a leakage current of the transistor may consume energy of a battery. Moreover, since noise affects a drain and a source of the transistor, a drain-source voltage is oscillated. When the drain-source voltage is oscillated around a conductive voltage of the rectifier, the transistor may be switched on or off by mistake.

The disclosure is directed to an alternator and a rectifier, which are adapted to avoid switching on/off a transistor by mistake.

The disclosure provides a rectifier adapted to a transistor. The rectifier includes a gate driving circuit, a logic circuit, and a comparison circuit. The gate driving circuit is coupled to a control terminal of the transistor, and is configured to generate a gate voltage, and the control terminal of the transistor receives the gate voltage. The gate driving circuit receives a control signal, and adjusts the gate voltage according to the control signal, so as to control a conductivity degree of the transistor. The logic circuit is coupled to the gate driving circuit, and generates the control signal and a switch signal according to a comparison result, and selects a selected voltage according to the switch signal. The comparison result is generated by the comparison circuit by comparing a sensing voltage of a first terminal of the transistor with the selected voltage.

The disclosure provides an alternator including a rotor, a stator and a plurality of the aforementioned rectifiers. Each of the rectifiers receives a corresponding AC input voltage as an input voltage, and the rectifiers collectively generate a rectified voltage.

Based on the above description, the rectifier of the disclosure detects a drain voltage of the rectifier transistor to adjust the gate voltage of the rectifier transistor, and switches a comparison reference of the comparison circuit to avoid switching on/off the transistor by mistake, so as to improve a working performance.

To make the aforementioned more comprehensible, several embodiments accompanied with drawings are described in detail as follows.

The accompanying drawings are included to provide a further understanding of the disclosure, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the disclosure and, together with the description, serve to explain the principles of the disclosure.

FIG. 1 is a schematic diagram of a rectifier according to an embodiment of the disclosure.

FIG. 2 is a schematic diagram of a state machine according to an embodiment of the disclosure.

FIG. 3 is a schematic diagram of a comparison circuit according to an embodiment of the disclosure.

FIG. 4 is a schematic diagram of a part of a rectifier according to an embodiment of the disclosure.

FIG. 5 is a schematic diagram of a part of a rectifier according to an embodiment of the disclosure.

FIG. 6 is a schematic diagram of a comparison circuit according to an embodiment of the disclosure.

FIG. 7 is a waveform schematic diagram according to an embodiment of the disclosure.

FIG. 1 is a schematic diagram of a rectifier according to an embodiment of the disclosure. Referring to FIG. 1 , the rectifier 100 is adapted to a transistor 110 , and the rectifier 100 includes a gate driving circuit 120 , a logic circuit 130 and a comparison circuit 140 . The gate driving circuit 120 is coupled to a control terminal of the transistor 110 , and the gate driving circuit 120 provides a gate voltage VG to the control terminal of the transistor 110 to control a conductivity degree of the transistor 110 . The logic circuit 130 is coupled to the gate driving circuit 120 , and is configured to provide control signals to the gate driving circuit 120 , and the gate driving circuit 120 adjusts the conductivity degree of the transistor 110 according to one of the control signals. The comparison circuit 140 is coupled to the logic circuit 130 , the comparison circuit 140 may compare one of a plurality of selection voltages with a drain voltage VD of the transistor 110 , and the logic circuit 130 generates the control signal according to a comparison result.

In the embodiment, the logic circuit 130 may provide a control signal ENON 1 , a control signal ENON 2 and a control signal ENOFF. The gate driving circuit 120 may adjust the output gate voltage VG according to the control signal ENON 1 , the control signal ENON 2 and the control signal ENOFF. For example, when the control signal ENON 1 has a high logic level, and the control signal ENON 2 and the control signal ENOFF all have a low logic level, the gate driving circuit 120 adjusts the gate voltage VG according to the control signal ENON 1 , such that the transistor 110 is switched on and has a first conductive impedance. When the control signal ENON 2 has the high logic level, and the control signal ENON 1 and the control signal ENOFF all have the low logic level, the gate driving circuit 120 adjusts the gate voltage VG according to the control signal ENON 2 , such that the transistor 110 is switched on and has a second conductive impedance. When the control signal ENOFF has the high logic level, and the control signal ENON 1 and the control signal ENON 2 all have the low logic level, the gate driving circuit 120 adjusts the gate voltage VG according to the control signal ENOFF, so as to switch off the transistor 110 , where the first conductive impedance is smaller than the second conductive impedance.

In the embodiment, the logic circuit 130 provides 3 control signals to the gate driving circuit 120 , which is only an example, and is not used for limiting an implementation scope of the disclosure. In other embodiments, the number of the control signals may be greater than or equal to 2, which is not particularly specified.

The logic circuit 130 may generate the control signals according to the comparison result of the comparison circuit 140 , and generates a switch signal CS according to the comparison result. The comparison circuit 140 may compare one of a plurality of selection voltages with a sensing voltage VD_S, where the sensing voltage VD_S may be a sensing value of the drain voltage VD. Moreover, the comparison circuit 140 may switch a plurality of the selection voltages according to the switch signal CS. To be specific, a negative input terminal of the comparison circuit 140 receives the sensing voltage VD_S, and a positive input terminal of the comparison circuit 140 receives one of the plurality of selection voltages. The comparison circuit 140 may switch one of the selection voltages to another one of the selection voltages according to the switch signal CS.

FIG. 2 is a schematic diagram of a state machine according to an embodiment of the disclosure. Referring to FIG. 1 and FIG. 2 , in the embodiment, the transistor 110 may be an N-type transistor, and the selection voltages are respectively a selection voltage V D_ON , a selection voltage V D_OCP and a selection voltage V D_OFF , where the selection voltage V D_ON is an initial selection voltage. The drain voltage VD decreases continuously after entering a negative half cycle. The comparison circuit 140 compares the sensing voltage VD_S with the selection voltage V D_ON , and when the sensing voltage VD_S is smaller than the selection voltage V D_ON , the logic circuit 130 generates the control signal ENON 1 with the high logic level according to the comparison result. Now, the other control signals ENON 2 and ENOFF may have the low logic level. The gate driving circuit 120 generates the gate voltage VG according to the control signal ENON 1 , and the transistor 110 is switched on and has the first conductive impedance. In this case, the transistor 110 may be completely switched on, so that the first conductive impedance of the transistor 110 is very tiny, and the drain voltage VD may be maintained be equal to or close to a voltage value of 0 volt. Now, the state machine is changed from a start state S 1 to a first stage conductive state S 2 . Moreover, when the sensing voltage VD_S is smaller than the selection voltage V D_ON , the logic circuit 130 adjusts the switch signal CS. Moreover, the comparison circuit 140 selects the selection voltage V D_OCP as a comparison reference according to the adjusted switch signal CS.

When the sensing voltage VD_S is smaller than or equal to the selection voltage V D_OCP , the state machine is maintained to the first stage conductive (rectifying) state S 2 . When the sensing voltage VD_S is greater than the selection voltage V D_OCP , the logic circuit 130 generates the control signal ENOFF with the high logic level according to the comparison result. Now, the other control signals ENON 1 and ENON 2 may have the low logic level. The gate driving circuit 120 generates the gate voltage VG according to the control signal ENOFF, so as to switch off the transistor 110 . Now, the state machine is changed from the first stage conductive (rectifying) state S 2 to the start state S 1 . Moreover, when the sensing voltage VD_S is greater than the selection voltage V D_OCP , the logic circuit 130 adjusts the switch signal CS. Moreover, the comparison circuit 140 selects the selection voltage V D_ON as a comparison reference according to the adjusted switch signal CS.

In an actual operation, various circuit anomalies may probably result in the sensing voltage VD_S larger than the selection voltage V D_OCP . Now, the gate driving circuit 120 may switch off the transistor 110 , and maintain the off state of the transistor 110 until the next negative half cycle of the drain voltage VD, so as to avoid oscillation of the sensing voltage VD_S near a conductive voltage of the transistor 110 to cause the transistor to switch on/off by mistake.

Comparatively, after the logic circuit 130 generates the control signal ENON 1 for a time interval TR, the logic circuit 130 generates the control signal ENON 2 with the high logic level. Now, the other control signals ENON 1 and ENOFF may have the low logic level. A time counting circuit can be set in the logic circuit 130 , and the time counting circuit may be implemented by a resistor-capacitor circuit or a timing circuit, so as to generate a value corresponding to a length of the time interval TR. The gate driving circuit 120 generates the gate voltage VG according to the control signal ENON 2 , so that the transistor 110 is partially switched on to have a second conductive impedance, where the second conductive impedance is greater than the first conductive impedance. Now, the state machine is changed from the first stage conductive (rectifying) state S 2 to a second stage conductive (rectifying) state S 3 . Moreover, when the logic circuit 130 generates the control signal ENON 1 , and maintains for the time interval TR, the logic circuit 130 adjusts the switch signal CS. The comparison circuit 140 selects the selection voltage V D_OFF as the comparison reference according to the adjusted switch signal CS.

When the sensing voltage VD_S is smaller than or equal to the selection voltage V D_OFF , the state machine is maintained to the second stage conductive (rectifying) state S 3 , and now the sensing voltage VD_S is equal to a regulation voltage V D_REG . When the sensing voltage VD_S is greater than the selection voltage V D_OFF , the logic circuit 130 generates the control signal ENOFF with the high logic level according to the comparison result. Now, the other control signals ENON 1 and ENON 2 may have the low logic level. The gate driving circuit 120 generates the gate voltage VG according to the control signal ENOFF, so as to switch off the transistor 110 . Now, the state machine is changed from the second stage conductive (rectifying) state S 3 to the start state S 1 . Moreover, when the sensing voltage VD_S is greater than the selection voltage V D_OFF , the logic circuit 130 adjusts the switch signal CS. Moreover, the comparison circuit 140 selects the selection voltage V D_ON as a comparison reference according to the adjusted switch signal CS.

Moreover, in case a drain and a source of the transistor 110 are short-circuited, a large current flows through the transistor 110 , and now a voltage value of the sensing voltage VD_S is rather high. Therefore, when the sensing voltage VD_S is equal to the regulation voltage V D_REG , the state machine is maintained to the second stage conductive (rectifying) state S 3 . When the sensing voltage VD_S is instantaneously larger than the selection voltage VD D_OCP , the state machine is quickly changed from the second stage conductive (rectifying) state S 3 to the start state S 1 . Through such mechanism, the transistor 110 may be quickly switched off, so as to avoid damage of the transistor 110 due to the large current.

In the embodiment, one of a plurality of control signals may be enabled, and has a first logic level. The gate driving circuit 120 may generate the gate voltage VG according to the control signal of the first logic level, and control the conductivity degree of the corresponding transistor through the gate voltage VG. In the embodiment, the first logic level may be the high logic level. Alternatively, in other embodiments of the disclosure, the first logic level may be the low logic level.

In this way, the rectifier 100 of the disclosure may adjust the gate voltage VG of the transistor 110 according to the drain voltage VD of the transistor 110 , so as to implement multi-stage control on the conductivity degree of the transistor 110 to achieve the rectifying effect. Implementation details of the gate driving circuit 120 , the logic circuit 130 and the comparison circuit 140 are described below.

The logic circuit 130 is configured to generate the control signal ENON 1 , the control signal ENON 2 and the control signal ENOFF according to the comparison result of the comparison circuit 140 . For example, when the sensing signal VD_S is smaller than the selection voltage V D_ON , the logic circuit 130 outputs the control signal ENON 1 of the high logic level, and now the control signal ENON 2 and the control signal ENOFF all have the low logic level.

The comparison circuit 140 is configured to compare the sensing signal VD_S with one selection voltage. Moreover, the comparison circuit 140 may select one of the selection voltage V D_ON , the selection voltage V D_OCP and the selection voltage V D_OFF as the comparison reference according to the switch signal CS.

FIG. 3 is a schematic diagram of a comparison circuit according to an embodiment of the disclosure. Referring to FIG. 3 , the comparison circuit 140 includes a voltage generating circuit 142 , a multiplexer 141 and an operational amplifier OP. The voltage generating circuit 142 is coupled to the multiplexer 141 , and the voltage generating circuit 142 receives the drain voltage VD, a source voltage VS, an operation power AVDD and a reference ground voltage GND.

The voltage generating circuit 142 includes a voltage source V 1 , a voltage source V 2 and a voltage source V 3 connected in series with each other. A first end of the voltage source V 3 may be coupled to the operation power AVDD through a resistor R 1 . A first end of the voltage source V 2 is coupled to a second end of the voltage source V 3 . A first end of the voltage source V 1 is coupled to a second end of the voltage source V 2 , and a second end of the voltage source V 1 may be coupled to the reference ground voltage GND through a resistor R 2 . The sensing voltage VD_S is provided to the first end of the voltage source V 1 , and the sensing voltage VD_S is generated by the drain voltage VD through a resistor R 3 . The source voltage VS is provided to one terminal of the resistor R 2 adjacent to the reference ground voltage GND. In the embodiment, the source voltage VS may be equal to the reference ground voltage GND.

A first input terminal of the multiplexer 141 receives a voltage of the first end of the voltage source V 3 , and a voltage of the first input terminal of the multiplexer 141 is equal to a sum of the sensing voltage VD_S and voltage values of the the voltage source V 2 and the voltage source V 3 . A second input terminal of the multiplexer 141 receives a voltage of the first end of the voltage source V 2 , and a voltage of the second input terminal of the multiplexer 141 is equal to a sum of the sensing voltage VD_S and the voltage source V 2 . A third input terminal of the multiplexer 141 receives a voltage of the second end of the voltage source V 1 , and a voltage of the third input terminal of the multiplexer 141 is equal to the sensing voltage VD_S minus the voltage source V 1 . The multiplexer 141 may output the voltage of the first input terminal of the multiplexer 141 , the voltage of the second input terminal of the multiplexer 141 , or the voltage of the third input terminal of the multiplexer 141 according to the switch signal CS.

The operational amplifier OP receives the operation voltage AVDD, the output voltage of the multiplexer 141 and a voltage source V 0 . The operational amplifier OP subtracts the output voltage of the multiplexer 141 from the voltage source V 0 to generate the comparison result.

In the embodiment, the voltage source V 0 may provide a voltage of 20 mV, the voltage source V 1 may provide a voltage of 10 mV, the voltage source V 2 may provide a voltage of 50 mV, and the voltage source V 3 may provide a voltage of 270 mV. In this way, the voltage of the first input terminal of the multiplexer 141 is the sensing voltage VD_S plus the voltage of 320 mV, the voltage of the second input terminal of the multiplexer 141 is the sensing voltage VD_S plus the voltage of 50 mV, and the voltage of the third input terminal of the multiplexer 141 is the sensing voltage VD_S minus the voltage of 10 mV. The operational amplifier OP subtracts the output voltage of the multiplexer 141 from the voltage source V 0 as the comparison result. When the output voltage of the multiplexer 141 is the sensing voltage VD_S plus the voltage of 320 mV, the comparison result is equivalent to a difference between the sensing voltage VD_S and a voltage of −300 mV. When the output voltage of the multiplexer 141 is the sensing voltage VD_S plus the voltage of 50 mV, the comparison result is equivalent to a difference between the sensing voltage VD_S and a voltage of −30 mV. When the output voltage of the multiplexer 141 is the sensing voltage VD_S minus the voltage of 10 mV, the comparison result is equivalent to a difference between the sensing voltage VD_S and a voltage of 30 mV.

Referring to FIG. 1 , the rectifier 100 may further include a start circuit 150 . The start circuit 150 is configured to provide the operation power AVDD of the comparison circuit 140 and a plurality of reference voltages Vref, where the reference voltages Vref may serve as the voltage sources V 0 -V 3 . FIG. 4 is a schematic diagram of a part of a rectifier according to an embodiment of the disclosure. Referring to FIG. 4 , the start circuit 150 may include an operation power generator 151 and a reference voltage generator 152 . A first terminal of the operation power generator 151 is coupled to a voltage VH, a second terminal of the operation power generator 151 is coupled to the reference ground voltage GND, and a third terminal of the operation power generator 151 provides the operation power AVDD. The reference voltage generator 152 receives the operation power AVDD, and provides the voltage source V 0 -V 3 according to an enabling signal EN.

An enabling signal generating circuit 160 is configured to provide the enabling signal EN according to the sensing signal VD_S. In FIG. 4 , the enabling signal generating circuit 160 includes a voltage shifter 161 , a transistor T 1 , a diode D 1 , a diode D 2 , a switch SW 1 , an inverter N 1 and a resistor R 3 . The diodes D 1 and D 2 may be diodes in the form of transistors. A first terminal of the resistor R 4 is coupled to the operation power AVDD, and a second terminal of the resistor R 4 provides the enabling signal EN. An input terminal of the inverter N 1 is coupled to the second terminal of the resistor R 4 to receive the enabling signal EN, and an output terminal of the inverter N 1 outputs an inverted enabling signal ENB. A first terminal of the transistor T 1 is coupled to a second terminal of the resistor R 4 , a second terminal of the transistor T 1 is coupled to an anode of the diode D 1 , and the transistor T 1 is controlled by an output voltage of the voltage shifter 161 . An anode of the diode D 2 is coupled to a cathode of the diode D 1 , and a cathode of the diode D 2 is coupled to the reference ground voltage. A first terminal of the switch SW 1 is coupled to the anode of the diode D 2 , a second terminal of the switch SW 1 is coupled to the cathode of the diode D 2 , and the switch SW 1 is controlled by the inverted enabling signal ENB. When the inverted enabling signal ENB has the high logic level, the switch SW 1 is switched on, and is configured to bypass the diode D 2 .

In another embodiment, the switch SW 1 may bypass the diode D 1 . In this case, the first terminal and the second terminal of the switch SW 1 may be respectively coupled to the anode and the cathode of the diode D 1 . In another embodiment, the number of the diodes may be greater than 2, and the switch SW 1 may be configured to bypass a plurality of diodes (for example, the diode D 1 and the diode D 2 ).

The voltage shifter 161 is configured to shift a voltage of the sensing signal VD_S, so as to provide the proper voltage to the transistor T 1 . Referring to FIG. 1 and FIG. 4 , the rectifier 100 may further include a resistor R 5 , a resistor R 6 , a diode D 3 and a capacitor C 1 . A first terminal of the resistor R 6 is coupled to the drain voltage VD, and a second terminal of the resistor R 6 provides the sensing signal VD_S. A first terminal of the resistor R 5 is coupled to the drain voltage VD. An anode of the diode D 3 is coupled to a second terminal of the resistor R 5 , and a cathode of the diode D 3 is coupled to the voltage VH. The capacitor C 1 is coupled between the voltage VH and the reference ground voltage GND.

Referring to FIG. 2 and FIG. 4 , when the drain voltage VD is greater than or equal to a sum of the conductive voltage of the transistor T 1 , a conductive voltage of the diode D 1 and a conductive voltage of the diode D 2 , the transistor T 1 is switched on to form a path P 1 . Now, the enabling signal EN is pulled down to the low logic level, and the inverted enabling signal ENB has the high logic level, the path P 1 is cut off, the path P 2 is formed, and the state machine is in a standby state S 0 . Namely, a start condition of the enabling signal generating circuit 160 is that the drain voltage VD is smaller than N×VT 1 , where VT 1 represents the conductive voltage of the transistor, and N is a positive integer. In the embodiment, N is equal to 2, and N×VT 1 may be provided by the transistor T 1 and the diode D 1 . When the drain voltage VD is smaller than N×VT 1 , the transistor T 1 provides an impedance, and the voltage of the enabling signal EN is pulled up and transited to the high logic level based on a voltage divider rule, and the inverted enabling signal ENB is transited to the low logic level, the path P 2 is cut off, and the path P 1 is formed. Now, the state machine is changed from the standby state S 0 to the start state S 1 .

Comparatively, when the drain voltage VD is greater than a voltage of (N+M)×VT 1 , the transistor T 1 is switched on, and the enabling signal EN is transited to the low logic level, and the inverted enabling signal ENB is transited to the high logic level. Now, the state machine is changed from the start state S 1 to the standby state S 0 . Where, M is a positive integer, and the voltage of M×VT 1 may be provided by the diode D 2 . In the embodiment, M is equal to 1.

FIG. 5 is a schematic diagram of a part of a rectifier according to an embodiment of the disclosure. A difference between FIG. 5 and FIG. 4 lies in an enabling signal generating circuit 160 ′, and descriptions of other components of FIG. 5 may refer to related description of the embodiment of FIG. 4 , which are not repeated. Referring to FIG. 5 , the enabling signal generating circuit 160 ′ includes resistors R 7 -R 9 , a transistor T 2 , an inverter N 2 , a switch SW 2 and a voltage shifter 161 ′. A first terminal of the resistor R 7 is coupled to the operation power AVDD, and a second terminal of the resistor R 7 provides the enabling signal EN. An input terminal of the inverter N 2 is coupled to the second terminal of the resistor R 7 to receive the enabling signal EN, and an output terminal of the inverter N 2 outputs the inverted enabling signal ENB. A first terminal of the transistor T 2 is coupled to the second terminal of the resistor R 7 , and a second terminal of the transistor T 2 is coupled to the reference ground voltage GND. A first terminal of the resistor R 8 is coupled to the first terminal of the transistor T 2 , a first terminal of the resistor R 9 is coupled to a second terminal of the resistor R 8 , and a second terminal of the resistor R 9 is coupled to the reference ground voltage GND. To be specific, the switch SW 2 and the resistor R 9 may form a variable resistor, the first terminal of the resistor R 9 is coupled to the first terminal of the switch SW 2 , the second terminal of the resistor R 9 is coupled to the reference ground voltage GND, and a third terminal of the resistor R 9 is coupled to the second terminal of the switch SW 2 . The switch SW 2 is constructed by a transistor, and is controlled by the enabling signal EN. In the embodiment, when the enabling signal EN has the high logic level, the switch SW 2 is switched on to decrease a resistance between the control terminal of the transistor T 2 and the reference ground voltage GND (which is smaller than a resistance R 9 ′ of the resistor R 9 ). Now, when the drain voltage is raised to [(R 9 ′+R 8 )/R 9 ′]×VT 2 from a low level, the transistor T 2 is switched on, and the enabling signal EN is changed from the high logic level to the low logic level. Comparatively, when the enabling signal EN has the low logic level, the switch SW 2 is switched off to increase the resistance between the control terminal of the transistor T 2 and the reference ground voltage GND (which is equal to the resistance of the resistor R 9 ). When the drain voltage is dropped to [(R 9 +R 8 )/R 9 ]×VT 2 from a high level, the transistor T 2 is switched off, and the enabling signal EN is changed from the low logic level to the high logic level.

According to the above description, it is learned that through the variable resistor formed by the switch SW 2 and the resistor R 9 , the conductivity degree of the transistor T 2 may be adjusted according to the enabling signal EN. Moreover, description of the voltage shifter 161 ′ is the same with that of the voltage shifter 161 of the embodiment of FIG. 4 , and detail thereof is not repeated.

In the embodiment of FIG. 5 , the resistor R 8 and the resistor R 9 are configured to provide N×VT 1 and (N+M)×VT 1 mentioned in the embodiment of FIG. 4 . Referring both of FIG. 2 and FIG. 5 , when the drain voltage VD is greater than or equal to (N+M)×VT 1 , a path P 3 is formed, and the transistor T 2 is controlled by the voltage of the first terminal of the resistor R 9 and is at least partially switched on, so that the enabling signal EN is pulled down to the low logic level. Now, the state machine is in the standby state S 0 . When the drain voltage VD is smaller than NXVT 1 , the voltage of the first terminal of the resistor R 9 is decreased, causing the transistor T 2 to be switched off and a path P 4 to be cut off. Now, the voltage of the enabling signal EN becomes higher based on the voltage divider rule, the enabling signal EN is accordingly transited to the high logic level, the inverted enabling signal ENB is transited to the low logic level, and a part of the resistor R 9 is bypassed by the switch SW 2 . Now, the sate machine is changed from the standby state S 0 to the start state S 1 .

Comparatively, when the drain voltage VD is greater than (N+M)×VT 1 , the transistor T 2 is switched on, and the enabling signal EN is transited to the low logic level, and the inverted enabling signal ENB is transited to the high logic level. Now, the state machine is changed from the start state S 1 to the standby state S 0 , where M×VT 1 may be provided by the transistor T 2 . In the embodiment, if R 9 =2×R 9 ′=2×R 8 , N is equal to 1.5 and M is equal to 0.5.

In the above embodiment, voltage values of the selection voltage V D_ON , the selection voltage V D_OCP and the selection voltage V D_OFF are respectively equal to −300 mV, 30 mV and −30 mV. In another embodiment, the voltage values of the selection voltage V D_ON , the selection voltage V D_OCP and the selection voltage V D_OFF may be directly provided to the positive input terminal of the operational amplifier OP. FIG. 6 is a schematic diagram of a comparison circuit according to an embodiment of the disclosure. Referring to FIG. 6 , the comparison circuit 140 ′ only includes the operational amplifier OP and the multiplexer 141 . In the embodiment, a reference voltage generator 152 ′ is configured to receive an operation power VHH and the drain voltage VD, and generates the operation power AVDD of the operational amplifier OP, the selection voltage V D_ON , the selection voltage V D_OCP and the selection voltage V D_OFF according to the enabling signal EN. The multiplexer 141 selects the selection voltage V D_ON , the selection voltage V D_OCP or the selection voltage V D_OFF according to the switch signal CS. The operational amplifier OP receives the operation power AVDD, the positive input terminal of the operational amplifier OP receives the output voltage of the multiplexer 141 , the negative input terminal of the operational amplifier OP is coupled to the sensing voltage VD_S, and the operational amplifier OP outputs a voltage difference between the positive input terminal and the negative input terminal. A generation detail of the enabling signal EN of the embodiment may refer to the related descriptions of the embodiments of FIG. 4 and FIG. 5 , which is not repeated.

FIG. 7 is a waveform schematic diagram according to an embodiment of the disclosure. In FIG. 7 , variations of a drain current IDS, the drain voltage VD, the enabling signal EN and the gate voltage VG are drawn. Referring to FIG. 2 and FIG. 7 , at a time point t 1 , the enabling signal EN is transited from the low logic level to the high logic level, and now the start circuit generates a plurality of reference voltages Vref. The drain voltage VD decreases continuously after entering a negative half cycle. When the drain voltage VD is greater than or equal to N×VT 1 , the state machine is maintained to the standby state S 0 . When the drain voltage VD is smaller than N×VT 1 (corresponding to the time point t 1 ), the state machine is changed from the standby state S 0 to the start state S 1 . When the drain voltage VD is smaller than the selection voltage V D_ON (corresponding to a time point t 2 ), the state machine is changed from the start state S 1 to the first stage conductive (rectifying) state S 2 , until a time point t 3 . Then, at the time point t 3 after the time interval TR, the state machine is changed to the second stage conductive (rectifying) state S 3 . Under the second stage conductive (rectifying) state S 3 , the drain voltage VD is decreased, and is maintained to the regulation voltage VD=V D_REG . When the drain voltage VD is raised and greater than the selection voltage V D_OFF (corresponding to a time point t 4 ), the state machine is changed to the start state S 1 . Now, the gate voltage VG is decreased, and the transistor executing the rectifying operation is switched off. When the drain voltage VD is greater than the selection voltage (N+M)×VT 1 (corresponding to a time point t 5 ), the state machine is changed to the standby state S 0 .

Moreover, in the disclosure, the enabling signal of the control circuit may also be switched off when power is not generated, so that the current consumption can be controlled to the minimum to reduce a leakage current of the transistor.

In summary, in the disclosure, the gate voltage may be adjusted by detecting the drain voltage. Through the configuration of the disclosure, the leakage current of the transistor may be reduced, so as to avoid excessive energy consumption. Moreover, during the rectification of the transistor, the selection voltage is switched to avoid switching on/off the transistor by mistake.

It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed embodiments without departing from the scope or spirit of the disclosure. In view of the foregoing, it is intended that the disclosure covers modifications and variations provided they fall within the scope of the following claims and their equivalents.