Operational amplifier and control method thereof

The present application is a continuation of international application No. PCT/CN2018/082868, filed on Apr. 12, 2018, of which is incorporated herein by reference in its entirety.

The present disclosure relates to an operational amplifier and, more particularly, to an operational amplifier used for a class AB amplifier to reduce voltage spikes generated when the class AB amplifier is turned on.

Class AB amplifiers are widely used in audio applications. In the audio applications, pop noise is one of typical specifications. Pop noise is an uncomfortable popping sound generated when an audio circuit/device is powered on or powered off. The uncomfortable popping sound is caused by instantaneous voltage spikes or direct current (DC) voltage variations generated at an output terminal of the audio circuit/device. Generally, when an offset voltage outputted by a class AB amplifier is less than 0.1 millivolt (mV) or a magnitude of a voltage spike is less than 10 mV, the human ear cannot hear pop noise. One may utilize an offset calibration technique to an operational amplifier (OPAMP) to thereby reduce an offset voltage of the class AB amplifier. However, a conventional voltage spike reduction method is not effective in reducing voltage spikes because of high sensitivity to process, voltage and temperature variations. A voltage spike of 10 mV to 100 mV is still generated. Please note that, in addition to reducing voltage spikes generated in response to the turning on of the class AB amplifier, it is desired to prevent an instantaneous circuit response, generated within the class AB amplifier during the turning on, from directly affecting an output of the class AB amplifier. In view of the foregoing, there is a need for improvement in the prior art.

Therefore, a main object of the present disclosure is to provide an operational amplifier used for a class AB amplifier and a related control method to reduce voltage spikes, thereby overcoming disadvantages of the related art.

To resolve the above issues, the present disclosure provides an operational amplifier. The operational amplifier comprises: a first amplifier stage, configured to generate a plurality of first output voltages according to a plurality of first input voltages; a second amplifier stage, coupled to the first amplifier stage, the second amplifier stage configured to generate a plurality of second output voltages according to the first output voltages; a second output stage circuit, coupled to the second amplifier stage and a first output stage circuit, the second output stage circuit configured to replicate an equivalent or a scaled-down version of the first output stage circuit; a first common-mode feedback circuit, coupled to the second amplifier stage and the second output stage circuit, the first common-mode feedback circuit configured to keep an output common-mode voltage of the second output stage circuit at a predetermined value; a logic loop circuit, coupled to the first amplifier stage, the logic loop circuit configured to adjust a difference between the first output voltages of the first amplifier stage; a bias circuit, configured to generate a voltage close to a common-mode voltage of a plurality of second input voltages of the second amplifier stage, wherein the common-mode voltage is produced after the operational amplifier is turned on; a second common-mode feedback circuit, coupled to the first amplifier stage, the second common-mode feedback circuit configured to keep an output common-mode voltage of the first output voltages of the first amplifier stage at a reference voltage, wherein the voltage generated by the bias circuit serves as the reference voltage; and a plurality of switches, configured to control connection between the first amplifier stage, the second amplifier stage, the first output stage circuit, the second output stage circuit, the first common-mode feedback circuit, the logic loop circuit and the second common-mode feedback circuit to enable the operational amplifier to operate in an offset calibration phase.

For example, the output common-mode voltage of the second output stage circuit is close to an output common-mode voltage produced after the operational amplifier is turned on.

For example, the first output stage circuit is coupled to a plurality voltage sources and the second output stage circuit through the switches; when the operational amplifier turns on, the first output stage circuit is turned on according to a switching status of the switches.

For example, when the logic loop circuit is configured to adjust the difference between the first output voltages of the first amplifier stage, the first output stage circuit is turned off.

For example, after the offset calibration phase finishes, and direct current calibration finishes, the difference between the first output voltages of the first amplifier stage is close to zero, the second output stage circuit, the first common-mode feedback circuit, the second common-mode feedback circuit and the logic loop circuit are turned off, and the first output stage circuit and a third common-mode feedback circuit are turned on.

For example, the third common-mode feedback circuit is coupled to the first amplifier stage, and configured to keep an output common-mode voltage of a plurality of output voltages of the operational amplifier at the predetermined value.

By establishing a voltage close to a stable voltage of each node in advance, the proposed operational amplifier can reduce voltage spikes to prevent generation of pop noise.

FIG. 1 illustrates an exemplary class AB amplifier in accordance with the embodiments of the present disclosure.

FIG. 2 illustrates an exemplary operational amplifier in accordance with some embodiments of the present disclosure.

FIG. 3 illustrates an exemplary control method in accordance with some embodiments of the present disclosure.

FIG. 4 illustrates a timing diagram of signals associated with an operational amplifier in accordance with some embodiments of the present disclosure.

Objectives, features and advantages of the present disclosure will be better understood by reference to the following detailed description of embodiments of the present disclosure, taken in conjunction with the accompanying drawings. It should be understood that the specific embodiments described herein are provided for illustrative purposes, and are not intended to limit the present disclosure.

Referring to FIG. 1 , a class AB amplifier 10 is illustrated in accordance with the embodiments of the present disclosure. The class AB amplifier 10 includes a plurality of input voltages V IN+ and V IN− , an operational amplifier 20 , a switch ∅ short and a plurality of feedback circuits F C . The operational amplifier 20 is configured to convert a plurality of input voltages V IP and V IN into a plurality of output voltages V OP and V ON . During offset calibration phase or in an offset calibration, the operational amplifier 20 can be configured to establish a voltage close to a stable voltage of each node therewithin in advance. As a result, when the class AB amplifier 10 is turned on, i.e. the operational amplifier 20 is turned on, an offset voltage can be reduced to lower/eliminate pop noise.

Specifically, referring to FIG. 2 , an implementation of the operational amplifier 20 is illustrated in accordance with some embodiments of the present disclosure. The operational amplifier 20 includes a first amplifier stage 202 , a second amplifier stage 204 , a first output stage circuit 206 , a second output stage circuit 208 , a first common-mode feedback circuit 210 , a logic loop circuit 212 , a second common-mode feedback circuit 214 , a bias circuit 216 , and a plurality of switches ∅ KDC and ∅ KDC .

The first amplifier stage 202 is configured to generate a plurality of first output voltages V ON1 and V OP1 according to the input voltages V IP and V IN of the operational amplifier 20 .

The second amplifier stage 204 , coupled to the first amplifier stage 202 , is configured to generate a plurality of second output voltages V ogp1 , V ogn1 , V ogp2 and V ogn2 according to the first output voltages V ON1 and V OP1 .

During offset calibration or in an offset calibration phase, the logic loop circuit 212 is configured to adjust a difference D between the first output voltages V ON1 and V OP1 of the first amplifier stage 202 .

After the operational amplifier 20 starts performing the offset calibration, the bias circuit 216 is configured to generate a voltage close to a stable voltage of an input node of the second amplifier stage 204 , wherein the stable voltage of the input node is produced after the operational amplifier 20 is turned on. The generated voltage can serve as a reference voltage of the second common-mode feedback circuit 214 .

An output terminal of the second common-mode feedback circuit 214 is coupled to the first amplifier stage 202 . During the offset calibration or in the offset calibration phase, the second common-mode feedback circuit 214 , serving as common-mode feedback of the first amplifier stage 202 , is configured to keep an output common-mode voltage of the first output voltages V ON1 and V OP1 of the first amplifier stage 202 at the aforementioned reference voltage.

The first output stage circuit 206 is coupled to a voltage HPVDD, a voltage HPVSS and the second output stage circuit 208 through the switches ∅ KDC and ∅ KDC . Connection between the first output stage circuit 206 and the second output stage circuit 208 is controlled by a switching status of the switches ∅ KDC and ∅ KDC .

The second output stage circuit 208 is coupled to the second amplifier stage 204 and the first output stage circuit 206 . In the offset calibration phase, the second output stage circuit 208 is configured to replicate the first output stage circuit 206 to provide an equivalent or a scaled-down version of the first output stage circuit 206 . After the operational amplifier is turned on, the second output stage circuit 208 is turned off.

The first common-mode feedback circuit 210 is coupled between the second amplifier stage 204 and the second output stage circuit 208 . In the offset calibration phase, the first common-mode feedback circuit 210 is configured to keep an output common-mode voltage V CPY of the second output stage circuit 208 at an output common-mode voltage V CM produced after the operational amplifier 20 is turned on.

In addition, the switches ∅ KDC and ∅ KDC disposed in the operational amplifier 20 is configured to control connection between the first amplifier stage 202 , the second amplifier stage 204 , the first output stage circuit 206 , the second output stage circuit 208 , the first common-mode feedback circuit 210 , the logic loop circuit 212 and the second common-mode feedback circuit 214 according to a control signal POW, thereby enabling the operational amplifier 20 to operate in the offset calibration phase or a turn-on phase.

As a result, during the offset calibration which is performed before the operational amplifier 20 is turned on, a common-mode voltage of the first amplifier stage 202 is close to a stable voltage of an input node of the second amplifier stage 204 which operates normally, thus preventing great variations in the first output voltages V ON1 and V OP1 when the operational amplifier 20 is turned on. Additionally, the operational amplifier 20 can replicate a voltage at each node of the first output stage circuit 206 with the use of the second output stage circuit 208 , and keep the output common-mode voltage V CPY at V CM with the use of the first common-mode feedback circuit 210 . As a result, during the offset calibration, the operational amplifier 20 can establish voltages, respectively close to stable voltages of nodes, in advance to thereby reduce voltage spikes generated when the operational amplifier 20 is turned on. The stable voltages of the nodes, i.e. the second output voltages V ogp1 , V ogn1 , V ogp2 and V ogn2 , are produced after the operational amplifier 20 is turned on.

The operational amplifier 20 further includes a third common-mode feedback circuit 218 and a plurality of compensation capacitors C M1 and C M2 . The third common-mode feedback circuit 218 , coupled to the first amplifier stage 202 , is turned on when the operational amplifier 20 is turned on, so as to provide feedback to the first amplifier stage 202 according to the output common-mode voltage V CM , thereby keeping the output voltages V OP and V ON of the operational amplifier 20 at the output common-mode voltage.

Referring to FIG. 3 , an operating principle of the operational amplifier 20 is illustrated. FIG. 3 is a diagram illustrating a control method 30 in accordance with some embodiments of the present disclosure. Before the operational amplifier 20 is turned on, the operational amplifier 20 can perform offset calibration according to the control method 30 to thereby establish a voltage close to a stable voltage of each node in advance. The control method 30 can be described in detail below.

Step 302 : Enable the operational amplifier 20 to enter an offset calibration phase according to a control signal POW.

Step 304 : Before the operational amplifier 20 is turned on, the bias circuit 216 generates a voltage close to a stable voltage of an input node of the second amplifier stage 204 . The stable voltage is produced after the operational amplifier 20 is turned on. The voltage close to the stable voltage can serve as a reference voltage of the second common-mode feedback circuit 214 .

Step 306 : The second common-mode feedback circuit 214 , serving as common-mode feedback of the first amplifier stage 202 , keeps an output common-mode voltage of the first output voltages V ON1 and V OP1 of the first amplifier stage 202 at the reference voltage.

Step 308 : The logic loop circuit 212 adjusts the difference D between the first output voltages V ON1 and V OP1 of the first amplifier stage 202 to be close to zero.

Step 310 : The first common-mode feedback circuit 210 keeps the output common-mode voltage V CPY of the second output stage circuit 208 at the output common-mode voltage V CM , which is produced after the operational amplifier 20 is turned on.

In view of the above, before the operational amplifier 20 is turned on, the control method 30 can perform the offset calibration according to steps 302 , 304 and 306 , thereby establishing a voltage close to a stable voltage of each node in advance. According to step 308 , the logic loop circuit 212 can adjust the difference D between the first output voltages V ON1 and V OP1 of the first amplifier stage 202 to zero, or approach zero. In other words, the first output voltages V ON1 and V OP1 can be adjusted to a same voltage level. As a result, when the operational amplifier 20 is turned on, voltage spikes can be reduced to avoid generation of pop noise.

It is worth noting that, during the offset calibration, the logic loop circuit 212 can adjust the difference D between the first output voltages V ON1 and V OP1 of the first amplifier stage 202 , while the first output stage circuit 206 of the operational amplifier 20 stays in an off state. In other words, during the offset calibration which is performed by the operational amplifier 20 according to the control method 30 , voltage variations at each node, e.g. variations in the first output voltages V ON1 and V OP1 , do not reflect in the output voltages V ON and V OP of the operational amplifier 20 such that voltage spikes would not be generated. In addition, when the difference D between the first output voltages V ON1 and V OP1 of the first amplifier stage 202 approaches zero, the offset calibration may come to an end. In the meantime, the second output stage circuit 208 , the first common-mode feedback circuit 210 , the logic loop circuit 212 and the second common-mode feedback circuit 214 are turned off, and the first output stage circuit 206 and the third common-mode feedback circuit 218 are turned on.

As a voltage close to a stable voltage of each node, i.e. the first output voltages V ON1 and V OP1 and the second output voltages V ogp1 , V ogn1 , V ogp2 and V ogn2 , has been established in advance, a voltage at each node will not vary greatly after the operational amplifier 20 is turned on, which can greatly reduce output voltage spikes in the operational amplifier 20 to thereby prevent generation of pop noise.

Next, referring to FIG. 4 , a timing diagram of signals associated with the operational amplifier 20 is illustrated in accordance with some embodiments of the present disclosure.

As shown in FIG. 4 , after a supply voltage is provided and stable, the control signal POW changes from a low level to a high level at a time t 1 . The operational amplifier 20 can perform offset calibration.

Between the time t 1 and a time t 2 , the logic loop circuit 212 can adjust the first output voltages V ON1 and V OP1 of the first amplifier stage 202 to thereby calibrate an offset voltage. As a result, the difference D between the first output voltages V ON1 and V OP1 of the first amplifier stage 202 can become smaller and smaller until the difference D between the first output voltages V ON1 and V OP1 is close to zero. In other words, each of the first output voltages V ON1 and V OP1 may approach a stable voltage of an input node of the second amplifier stage 204 , wherein the stable voltage is produced at the input node after the operational amplifier 20 is turned on. Additionally, the second output voltages V ogp1 , V ogn1 , V ogp2 and V ogn2 of the second amplifier stage 204 can finally approach respective stable voltages of nodes, respectively, with the use of the second output stage circuit 208 and the first common-mode feedback circuit 210 . During the offset calibration, i.e. between the times t 1 and t 2 , the first output stage circuit 206 of the operational amplifier 20 is turned off. As a result, during the offset calibration which is performed by the operational amplifier 20 according to the control method 30 , voltage variations at each node, e.g, variations in the first output voltages V ON1 and V OP1 , do not reflect in the output voltages V ON and V OP of the operational amplifier 20 such that voltage spikes would not be generated.

At the time t 2 , the offset calibration finishes. In the meantime, the second output stage circuit 208 , the first common-mode feedback circuit 210 , the logic loop circuit 212 and the second common-mode feedback circuit 214 are turned off, and the first output stage circuit 206 and the third common-mode feedback circuit 218 are turned on. As a voltage close to a stable voltage of each node has been established in advance, each node voltage of the operational amplifier 20 , i.e. the first output voltages V ON1 and V OP1 , the second output voltages V ogp1 , V ogn1 , V ogp2 and V ogn2 and the output voltages V ON and V OP , can achieve a smooth transient state to prevent large variations in voltage. As a result, by establishing a voltage close to a stable voltage of each node in advance, the operational amplifier 20 used for the class AB amplifier 10 can greatly reduce a voltage spike to a voltage level less than 1 mV.

It is worth noting that the aforementioned embodiments are provided for illustrating the spirit of the present disclosure. Those skilled in the art can recognize that the aforementioned embodiments can be appropriately modified. For example, the aforementioned switch can be implemented using a transistor switch or other types of switches. As another example, circuits such as a logic circuit can be implemented using, but not limited to, other circuits having identical functions. Such modifications can be applied to the present disclosure.

To sum up, by establishing a voltage close to a stable voltage of each node in advance, the proposed operational amplifier used for a class AB amplifier can reduce voltage spikes to prevent generation of pop noise.

The foregoing description provides merely several embodiments of the present disclosure, and is not intended to limit the present disclosure. Those skilled in the art should appreciate that all modifications, alterations and improvements, realized in accordance with the spirit and principles of the present disclosure, fall within the scope of the present disclosure.